JP7311561B2 - チップのテストパッド構造 - Google Patents
チップのテストパッド構造 Download PDFInfo
- Publication number
- JP7311561B2 JP7311561B2 JP2021126948A JP2021126948A JP7311561B2 JP 7311561 B2 JP7311561 B2 JP 7311561B2 JP 2021126948 A JP2021126948 A JP 2021126948A JP 2021126948 A JP2021126948 A JP 2021126948A JP 7311561 B2 JP7311561 B2 JP 7311561B2
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- Prior art keywords
- test
- test pads
- chip
- pads
- internal
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- H01—ELECTRIC ELEMENTS
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- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
- H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
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- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9211—Parallel connecting processes
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Automatic Analysis And Handling Materials Therefor (AREA)
- Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
- Magnetic Heads (AREA)
- Fittings On The Vehicle Exterior For Carrying Loads, And Devices For Holding Or Mounting Articles (AREA)
Description
Claims (16)
- チップ内に配置された複数の第1の内部テストパッドと、
前記チップ内に配置され、前記複数の第1の内部テストパッドとある距離だけ離隔している、複数の第2の内部テストパッドと、
前記チップ上に配置され、前記複数の第1の内部テストパッドに接続され、前記複数の第1の内部テストパッドの上方に配置され、信号または電力を前記第1の内部テストパッドに伝送し、第1の側面と、第2の側面と、を含む、複数の第1の延在テストパッドと、
前記チップ上に配置され、前記複数の第2の内部テストパッドに接続され、前記複数の第2の内部テストパッドの上方に配置され、信号または電力を前記第2の内部テストパッドに伝送し、第1の側面と、第2の側面と、を含む、複数の第2の延在テストパッドと、
を備え、
前記複数の第1の延在テストパッドの前記第2の側面が、前記複数の第2の延在テストパッドの前記第2の側面に対向しており、
前記複数の第1の延在テストパッドの前記第1の側面および前記複数の第2の延在テストパッドの前記第1の側面が、第1のテスト距離だけ離隔しており、
前記複数の第1の延在テストパッドの前記第2の側面および前記複数の第2の延在テストパッドの前記第2の側面が、第2のテスト距離だけ離隔しており、
前記第1のテスト距離が、前記第2のテスト距離よりも大きく、
テスト装置が、プローブ距離だけ離隔した2つのプローブを含み、
前記第1のテスト距離が、前記プローブ距離よりも大きく、
前記第2のテスト距離が、前記プローブ距離よりも小さい、チップのテストパッド構造。 - 前記複数の第1の延在テストパッドの面積が、前記複数の第1の内部テストパッドの面積よりも大きい、請求項1に記載のチップのテストパッド構造。
- 前記複数の第2の延在テストパッドの面積が、前記複数の第2の内部テストパッドの面積よりも大きい、請求項1に記載のチップのテストパッド構造。
- 前記複数の第1の延在テストパッドの長さが、前記複数の第1の内部テストパッドの長さよりも大きい、請求項1に記載のチップのテストパッド構造。
- 前記複数の第2の延在テストパッドの長さが、前記複数の第2の内部テストパッドの長さよりも大きい、請求項1に記載のチップのテストパッド構造。
- 前記複数の第1の延在テストパッドの幅が、前記複数の第1の内部テストパッドの幅以上である、請求項1に記載のチップのテストパッド構造。
- 前記複数の第2の延在テストパッドの幅が、前記複数の第2の内部テストパッドの幅以上である、請求項1に記載のチップのテストパッド構造。
- 前記複数の第1の延在テストパッドが、前記複数の第2の延在テストパッドの方へ延在する、請求項1に記載のチップのテストパッド構造。
- 前記複数の第2の延在テストパッドが、前記複数の第1の延在テストパッドの方へ延在する、請求項1に記載のチップのテストパッド構造。
- 前記複数の第1の延在テストパッドが、前記複数の第2の延在テストパッドから離れる方へ延在する、請求項1に記載のチップのテストパッド構造。
- 前記複数の第2の延在テストパッドが、前記複数の第1の延在テストパッドから離れる方へ延在する、請求項1に記載のチップのテストパッド構造。
- 前記複数の第1の延在テストパッドの側面と前記チップの側面との間の距離が、前記複数の第1の内部テストパッドの側面と前記チップの前記側面との間の距離よりも小さい、請求項1に記載のチップのテストパッド構造。
- 前記複数の第2の延在テストパッドの側面と前記チップの側面との間の距離が、前記複数の第2の内部テストパッドの側面と前記チップの前記側面との間の距離よりも小さい、請求項1に記載のチップのテストパッド構造。
- 前記複数の第1の延在テストパッドまたは/および前記複数の第2の延在テストパッドが、前記チップを越えて延在し;
前記複数の第1の内部テストパッドおよび前記複数の第2の内部テストパッドが、前記チップの内部に位置する、請求項1に記載のチップのテストパッド構造。 - 前記複数の第1の延在テストパッドがそれぞれ、
第1の本体と、
前記第1の本体および前記複数の第1の内部テストパッドに接続された、第1の接続部材と、
を含む、請求項1に記載のチップのテストパッド構造。 - 前記複数の第2の延在テストパッドがそれぞれ、
第2の本体と、
前記第2の本体および前記複数の第2の内部テストパッドに接続された、第2の接続部材と、
を含む、請求項1に記載のチップのテストパッド構造。
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US6180426B1 (en) * | 1999-03-01 | 2001-01-30 | Mou-Shiung Lin | High performance sub-system design and assembly |
TW479304B (en) * | 2001-02-06 | 2002-03-11 | Acer Display Tech Inc | Semiconductor apparatus and its manufacturing method, and liquid crystal display using semiconductor apparatus |
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US20060109014A1 (en) * | 2004-11-23 | 2006-05-25 | Te-Tsung Chao | Test pad and probe card for wafer acceptance testing and other applications |
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US10283424B1 (en) * | 2018-03-08 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer structure and packaging method |
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