JP4067502B2 - 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置 - Google Patents
半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置 Download PDFInfo
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- JP4067502B2 JP4067502B2 JP2004068411A JP2004068411A JP4067502B2 JP 4067502 B2 JP4067502 B2 JP 4067502B2 JP 2004068411 A JP2004068411 A JP 2004068411A JP 2004068411 A JP2004068411 A JP 2004068411A JP 4067502 B2 JP4067502 B2 JP 4067502B2
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- Prior art keywords
- bump
- semiconductor device
- dummy
- bump electrode
- bump electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Liquid Crystal (AREA)
Description
1a 第1辺
1b 第2辺
1c 第3辺
1d 第4辺
2 バンプ電極
2a 第1バンプ電極
2b 第2バンプ電極
2c 第3バンプ電極
2d 第4バンプ電極
3 ダミーバンプ
5 気泡
10 半導体基板
10a 半導体基板
10b 半導体基板
10c 半導体基板
21 ガラス基板
22 パッド22
30 異方性導電層
32 導電性粒子
34 絶縁性接着剤
100 液晶表示装置
Claims (7)
- 異方性導電層を介して、回路基板にフェイスダウン実装されるベアチップ型半導体装置であって、
少なくとも4つの辺を含む主面を有する半導体基板と、
前記半導体基板の前記主面の周辺領域に設けられ、前記少なくとも4つの辺の内の少なくとも1つの辺の近傍に、前記少なくとも1つの辺に沿って配列された複数のバンプ電極であって、隣接間隔が0.1mm以下で配列されたバンプ電極を含む第1バンプ電極群と、隣接間隔が0.1mm超で配列されたバンプ電極を含む第2バンプ電極群とを含む、複数のバンプ電極と、
前記複数のバンプ電極の内の少なくとも一部のバンプ電極を挟んで、前記少なくとも1つの辺と対向するように設けられた少なくとも1つのダミーバンプとを有しており、
前記少なくとも1つのダミーバンプは、前記第1バンプ電極群の前記隣接間隔0.1mm以下のバンプ電極と対応する位置に設けられ、前記第2バンプ電極群の前記隣接間隔0.1mm超のバンプ電極と対応する位置に設けられていない、半導体装置。 - 前記少なくとも1つのダミーバンプの少なくとも表面は、絶縁材料で形成されている、請求項1に記載の半導体装置。
- 前記少なくとも1つのダミーバンプと、前記複数のバンプ電極の内の前記少なくとも1つのダミーバンプに最近接のバンプ電極との距離は、10μm以上100μm以下の範囲にある、請求項1または2に記載の半導体装置。
- 前記少なくとも1つのダミーバンプの前記半導体基板の前記主面からの高さは、前記複数のバンプ電極の前記主面からの高さと等しい、請求項1から3のいずれかに記載の半導体装置。
- 請求項1から4のいずれかに記載の半導体装置と、回路基板とを備え、
前記半導体装置は前記回路基板に前記異方性導電層を介してフェイスダウンで実装されている、半導体装置の実装構造。 - 請求項5に記載の半導体装置の実装構造を備える、電子機器。
- 請求項5に記載の半導体装置の実装構造を備え、前記回路基板が透明基板である、表示装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004068411A JP4067502B2 (ja) | 2004-03-11 | 2004-03-11 | 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004068411A JP4067502B2 (ja) | 2004-03-11 | 2004-03-11 | 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005259924A JP2005259924A (ja) | 2005-09-22 |
JP4067502B2 true JP4067502B2 (ja) | 2008-03-26 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004068411A Expired - Fee Related JP4067502B2 (ja) | 2004-03-11 | 2004-03-11 | 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4067502B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11335668B2 (en) | 2019-10-30 | 2022-05-17 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009212209A (ja) * | 2008-03-03 | 2009-09-17 | Seiko Epson Corp | 半導体モジュール及びその製造方法 |
EP2432006A1 (en) * | 2009-06-16 | 2012-03-21 | Sharp Kabushiki Kaisha | Semiconductor chip and structure for mounting same |
CN104704621B (zh) * | 2012-10-11 | 2017-08-25 | 夏普株式会社 | 驱动芯片和显示装置 |
TW202349576A (zh) * | 2020-07-31 | 2023-12-16 | 矽創電子股份有限公司 | 晶片之導流結構 |
-
2004
- 2004-03-11 JP JP2004068411A patent/JP4067502B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11335668B2 (en) | 2019-10-30 | 2022-05-17 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
Also Published As
Publication number | Publication date |
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JP2005259924A (ja) | 2005-09-22 |
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