JP6960119B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6960119B2 JP6960119B2 JP2017228232A JP2017228232A JP6960119B2 JP 6960119 B2 JP6960119 B2 JP 6960119B2 JP 2017228232 A JP2017228232 A JP 2017228232A JP 2017228232 A JP2017228232 A JP 2017228232A JP 6960119 B2 JP6960119 B2 JP 6960119B2
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- 239000004065 semiconductor Substances 0.000 title claims description 386
- 239000012535 impurity Substances 0.000 claims description 29
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims 4
- 230000005684 electric field Effects 0.000 description 35
- 238000004088 simulation Methods 0.000 description 9
- 230000007423 decrease Effects 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000002411 adverse Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004645 scanning capacitance microscopy Methods 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Description
図面は模式的または概念的なものであり、各部分の厚さと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図1(a)及び図1(b)は、第1実施形態に係る半導体装置を例示する模式的断面図である。
図1(a)に示すように、実施形態に係る半導体装置110は、第1導電部51、半導体部10s及び第1絶縁部31を含む。半導体部10sは、炭化珪素を含む。
第1導電部51は、第2方向(X軸方向)における2つの端(端51a及び端51b)を有する。これらの2つの端(端51a及び端51b)の中点51cを通り、第1方向(Z軸方向)に沿う直線を直線L51とする。この直線L51は、第1部分p1の1つの位置P31(第2位置)を通過する。この位置P31(第2位置)における第1部分p1の第1方向(Z軸方向)に沿う長さを第1長さt1とする。
上記のように、第1導電部51は、第2方向(X軸方向)における2つの端(端51a及び端51b)を有する(図2参照)。これらの2つの端の中点51cを通り第1方向(Z軸方向)に沿う直線L51は、第4半導体領域14の位置P14(第1位置)を通過する。
図3に示すように、半導体装置110aは、第1導電部51、第1電極61、第2電極62、半導体部10s、第1絶縁部31及び第2絶縁部32に加えて、導電領域65a及び65bを含む。この場合も、半導体部10sは、炭化珪素を含む。半導体部10sは、上記の第1〜第8半導体領域11〜18に加えて第9半導体領域19及び半導体領域19aをさらに含む。
図4の横軸は、第1曲率半径R1(μm)である。図4の左の縦軸は、耐圧V1(V)である。耐圧V1は、ソース(第1電極61)及びゲート(第1導電部51)の電位を0ボルト(V)とし、ドレイン(第2電極62)に加える電圧を変化させたときに、ソース−ドレイン間に流れる電流が1μAを超えるときの、電圧である。耐圧V1は、オフ時の耐圧に対応する。図4の右の縦軸は、最大電界強度E1(MV/cm)である。最大電界強度E1は、ドレイン電極(第2電極62)に加える電圧が1200Vのときに第1絶縁部31に加わる電界の最大値である。
図5の横軸は、第1部分p1の厚さ(第1長さt1(μm))である。図5の左の縦軸は、耐圧V1(V)である。図5の右の縦軸は、最大電界強度E1(MV/cm)である。図5に示す例では、第2部分p2の厚さ(第2長さt2)は、0.08μmで一定である。第2曲率半径R2は、0.04μmで一定である。第1曲率半径R1は、0.37μmで一定である。
図6は、シミュレーションのモデルにおけるパラメータを示している。シミュレーションモデルにおいて、パラメータは、以下とされる。
図7の横軸は、基準位置x0に対する境界B1の相対距離pX(μm)である。相対距離pXが0のときは、境界B1は基準位置x0に位置する。相対距離pXが正のときは、境界B1が基準位置x0よりも外側(トレンチに重ならない)である状態に対応する。相対距離pXが負のときは、境界B1が基準位置x0よりも内側(トレンチに重なる)である状態に対応する。図7には、上記の基準位置x0、位置x1〜x3が示されている。図7の縦軸は、オン抵抗RonAである。
図8の横軸は、相対距離pX(μm)である。図4の左の縦軸は、耐圧V1(V)である。図8の右の縦軸は、最大電界強度E1(MV/cm)である。
図12に示すように、実施形態に係る別の半導体装置120においては、第1導電部51、半導体部10s、第1絶縁部31、第1電極61、第2電極62及び第2絶縁部32に加えて、第2導電部52及び第3絶縁部33が設けられる。この例では、第4絶縁部34がさらに設けられている。
本実施形態は、半導体装置110の製造方法に係る。以下では、半導体装置110の製造方法の例について説明する。
図13(a)に示すように、半導体部材10Mを準備する。半導体部材10Mは、炭化珪素を含む。半導体部材10Mは、第1半導体膜11f、第2半導体膜12f、第3半導体膜13f、第5半導体領域15及び第8半導体領域18を含む。第1半導体膜11f及び第2半導体膜12fは、第1導電形である。第3半導体膜13fは、第2導電形である。例えば、半導体層10Lの上に第1半導体膜11fが設けられる。第1半導体膜11fの上に第3半導体膜13fが設けられる。第3半導体膜13fの上に、第2半導体膜12f、第5半導体領域15及び第8半導体領域18が設けられる。第2半導体膜12fは、X軸方向において、第5半導体領域15と第8半導体領域18との間に位置する。第5半導体領域15は、第8半導体領域18と連続しても良い。
Claims (19)
- 第1導電部と、
炭化珪素を含む半導体部と、
第1絶縁部と、
を備え、
前記半導体部は、第1〜第4半導体領域を含み、
前記第1半導体領域は、第1導電形であり、第1部分領域及び第2部分領域を含み、前記第1部分領域は、第1方向において前記第1導電部から離れ、前記第1部分領域から前記第2部分領域への方向は、前記第1方向と交差し、
前記第2半導体領域は、前記第1導電形であり、前記第1導電部の一部から前記第2半導体領域への方向は前記第1方向と交差する第2方向に沿い、
前記第3半導体領域は、第2導電形であり、前記第1方向において前記第2部分領域と前記第2半導体領域との間に設けられ、
前記第4半導体領域は、前記第2導電形であり、前記第1方向において前記第1導電部と前記第1部分領域との間に設けられ、前記第4半導体領域から前記第2部分領域への方向は前記第2方向に沿い、
前記第1絶縁部は、第1〜第3部分を含み、
前記第1部分の少なくとも一部は、前記第1方向において前記第1導電部と前記第4半導体領域との間に位置し、
前記第2部分は、前記第2方向において前記第1導電部の前記一部と前記第2半導体領域との間、及び、前記第2方向において前記第1導電部と前記第3半導体領域との間に位置し、前記第2部分領域の一部は、前記第1方向において前記第2部分と重なり、
前記第3部分は、前記第1部分と前記第2部分との間に設けられ、
前記第3部分は、前記第1導電部に対向する第1面と、前記半導体部に対向する第2面と、を有し、
前記第1方向及び前記第2方向を含む断面における前記第1面の第1曲率半径は、前記断面における前記第2面の第2曲率半径よりも大きく、
前記第1部分の前記第1方向に沿う長さは、前記第2部分の前記第2方向に沿う長さ以下である、半導体装置。 - 前記第4半導体領域の一部は、前記第1方向において、前記第2部分と重なる、請求項1記載の半導体装置。
- 前記第2部分領域の前記一部は、前記第1方向において前記第1導電部と重なる、請求項1記載の半導体装置。
- 前記第1導電部は、前記第2方向における2つの端を有し、
前記2つの端の中点を通り前記第1方向に沿う直線は、前記第1部分の第2位置を通過し、
前記第1部分の第1端部は、前記第3部分と連続し、
前記第1端部の前記第1方向に沿う長さは、前記第2位置における前記第1部分の前記第1方向に沿う第1長さの1.1倍であり、
前記第2部分領域の前記一部は、前記第1方向において前記第1端部と重なる、請求項1記載の半導体装置。 - 前記第3部分の前記第1方向に沿う長さは、前記第1部分の前記第1方向に沿う前記長さよりも長く、
前記第3部分の前記第2方向に沿う長さは、前記第2部分の前記第2方向に沿う前記長さよりも長い、請求項1〜4のいずれか1つに記載の半導体装置。 - 前記第1曲率半径は、前記第2曲率半径の4倍以上である、請求項1〜5のいずれか1つに記載の半導体装置。
- 前記第1部分の前記第1方向に沿う前記長さは、0.25μm以下である、請求項1〜4のいずれか1つに記載の半導体装置。
- 前記第1導電部は、前記第2方向において、前記第1半導体領域と重なる、請求項1〜7のいずれか1つに記載の半導体装置。
- 前記第4半導体領域における前記第2導電形の不純物濃度は、前記第3半導体領域における前記第2導電形の不純物濃度よりも高い、請求項1〜8のいずれか1つに記載の半導体装置。
- 前記第2半導体領域における前記第1導電形の不純物濃度は、前記第1半導体領域における前記第1導電形の不純物濃度よりも高い、請求項1〜9のいずれか1つに記載の半導体装置。
- 前記第2半導体領域と電気的に接続された第1電極をさらに備え、
前記第2半導体領域は、前記第1方向において、前記第1電極の少なくとも一部と前記第3半導体領域との間に位置した、請求項1〜10のいずれか1つに記載の半導体装置。 - 第2絶縁部をさらに備え、
前記第2絶縁部は、前記第1方向において、前記第1電極の別の一部と前記第1導電部との間に位置した、請求項11記載の半導体装置。 - 前記半導体部は、前記第2導電形の第5半導体領域をさらに含み、
前記第2半導体領域は、前記第2方向において、前記第1導電部の前記一部と、前記第5半導体領域と、の間に位置し、
前記第1電極は、前記第5半導体領域と電気的に接続された、請求項11または12に記載の半導体装置。 - 前記第1半導体領域は、第3部分領域をさらに含み、
前記第4半導体領域は、前記第2方向において、前記第3部分領域と前記第2部分領域との間に位置し、
前記半導体部は、第6半導体領域及び第7半導体領域をさらに含み、
前記第6半導体領域は、前記第1導電形であり、前記第1導電部は、前記第2方向において、前記第6半導体領域と前記第2半導体領域との間に位置し、
前記第7半導体領域は、前記第2導電形であり、前記第1導電部は、前記第2方向において、前記第7半導体領域と前記第3半導体領域との間に位置し、
前記第7半導体領域は、前記第1方向において、前記第3部分領域と前記第6半導体領域との間に位置し、
前記第1絶縁部は、第4部分及び第5部分をさらに含み、
前記第4部分は、前記第2方向において前記第1導電部と前記第6半導体領域との間、及び、前記第2方向において前記第1導電部と前記第7半導体領域との間に位置し、前記第3部分領域の一部は、前記第1方向において前記第4部分と重なり、
前記第5部分は、前記第1部分と前記第4部分との間に設けられ、
前記第5部分は、前記第1導電部に対向する第3面と、前記半導体部に対向する第4面と、を有し、
前記断面における前記第3面の第3曲率半径は、前記断面における前記第4面の第4曲率半径よりも大きい、請求項11〜13のいずれか1つに記載の半導体装置。 - 前記半導体部は、前記第2導電形の第8半導体領域をさらに含み、
前記第6半導体領域は、前記第2方向において、前記第1導電部と、前記第8半導体領域と、の間に位置し、
前記第1電極は、前記第8半導体領域と電気的に接続された、請求項14記載の半導体装置。 - 第2導電部と、
第3絶縁部と、
第4絶縁部と、
をさらに備え、
前記第2半導体領域は、前記第2方向において、前記第1導電部と前記第2導電部との間に位置し、
前記第3半導体領域は、前記第2方向において、前記第1導電部と前記第2導電部との間に位置し、
前記第3絶縁部は、前記半導体部と前記第2導電部との間に設けられ、
前記半導体部は、前記第2導電形の第9半導体領域をさらに含み、
前記第9半導体領域は、前記第1方向において、前記第2導電部から離れ、
前記第2部分領域は、前記第2方向において、前記第4半導体領域と前記第9半導体領域との間に位置した、請求項1〜15のいずれか1つに記載の半導体装置。 - 前記第2半導体領域と電気的に接続された導電領域をさらに備え、
前記半導体部は、前記第2導電形の第9半導体領域をさらに含み、
前記導電領域は、前記第9半導体領域と電気的に接続され、
前記第2部分領域は、前記第2方向において、前記第4半導体領域と前記第9半導体領域との間に位置した、請求項1〜15のいずれか1つに記載の半導体装置。 - 第2電極をさらに備え、
前記第1部分領域は、前記第1方向において、前記第4半導体領域と前記第2電極との間に位置し、
前記第2部分領域は、前記第1方向において、前記第3半導体領域と前記第2電極との間に位置した、請求項1〜17のいずれか1つに記載の半導体装置。 - 前記半導体部は、前記第1導電形または第2導電形の半導体層をさらに含み、
前記半導体層は、前記第1半導体領域と前記第2電極との間に位置した、請求項18記載の半導体装置。
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