JP6700648B2 - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 116
- 238000004519 manufacturing process Methods 0.000 title claims description 79
- 239000012535 impurity Substances 0.000 claims description 155
- 239000000758 substrate Substances 0.000 claims description 106
- 238000005468 ion implantation Methods 0.000 claims description 80
- 229910052698 phosphorus Inorganic materials 0.000 claims description 46
- 239000011574 phosphorus Substances 0.000 claims description 46
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 40
- 238000009792 diffusion process Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 36
- 238000000137 annealing Methods 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims 5
- 239000010410 layer Substances 0.000 description 49
- 238000009826 distribution Methods 0.000 description 26
- 229910052796 boron Inorganic materials 0.000 description 23
- 230000015572 biosynthetic process Effects 0.000 description 21
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 20
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 239000002344 surface layer Substances 0.000 description 15
- -1 boron ion Chemical class 0.000 description 13
- 229910052785 arsenic Inorganic materials 0.000 description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000007429 general method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
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- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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Description
本発明の実施の形態1にかかる半導体装置について、MOS型半導体装置の一つであるパワーMOSFETを例に説明する。図1は、本発明の実施の形態1にかかるMOSFETの表面MOS構造の要部を示す断面図である。n-層2となる半導体基板のおもて面の表面層には、p型ウェル領域3が選択的に設けられている。p型ウェル領域3の内部には、n+型ソース領域4およびp-領域5が選択的に設けられている。n+型ソース領域4は、基板おもて面に露出されている。p-領域5は、n+型ソース領域4とp型ウェル領域3との間に設けられ、n+型ソース領域4の周囲を取り囲む。また、p型ウェル領域3の内部には、p-領域5に接するようにp+コンタクト領域(不図示)が設けられていてもよい。
次に、本発明の実施の形態2にかかる半導体装置の製造方法について、nチャネルMOSFETを製造する場合を例に説明する。図15〜図22は、本発明の実施の形態2にかかるMOSFETの表面MOS構造の製造工程を順に示す半導体基板の要部断面図である。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、p型ウェル領域3およびn+型ソース領域4を形成する前に、ゲート絶縁膜6とポリシリコンからなるゲート電極7とを形成する点である。すなわち、実施の形態2においては、ゲート電極7をマスクにして、チャネルが形成される側のp型ウェル領域3、n+型ソース領域4、およびp-領域5をセルフアライメントで形成する。
次に、本発明の実施の形態3にかかる半導体装置の製造方法について、nチャネルMOSFETを製造する場合を例に説明する。図39〜図42は、本発明の実施の形態3にかかるMOSFETの表面MOS構造の製造工程を順に示す半導体基板の要部断面図である。実施の形態3にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、異なるレジストマスクを用いて、ひ素イオン注入16とリンイオン注入17とを行う点である。具体的には、レジストマスクとフィールド酸化膜11による酸化膜マスクとの間に形成される開口部の幅を、リンイオン注入17のときよりも、ひ素イオン注入16のときに狭くすることで、n+型ソース領域24の幅をp-領域25の幅よりもさらに狭くする。
2 n-層
3,33 p型ウェル領域
4,24,39 n+型ソース領域
5,25 p-領域
6,37 ゲート絶縁膜
7,38 ゲート電極
8 層間絶縁膜
9,36 p+コンタクト領域
10 チャネル形成領域
11 フィールド酸化膜
11a フィールド酸化膜11による酸化膜マスクの開口部
12,32 スクリーン酸化膜
13a,13b,35 ボロンイオン注入
14,15,34a、34b、41,42 レジストマスク
15a,39a,41a,42a フィールド酸化膜またはゲート電極とレジストマスクとの間の開口部
16 ひ素イオン注入
17 リンイオン注入
30 n型シリコン基板
31 絶縁膜
Claims (4)
- 第1導電型ドリフト層となる第1導電型半導体基板の一方の主面に第1絶縁膜を形成し、前記第1絶縁膜に選択的に第1開口部を形成後、前記第1開口部に前記第1絶縁膜より厚さが薄い第2絶縁膜を形成する第1形成工程と、
前記第1導電型半導体基板の一方の主面に前記第1絶縁膜をマスクにして前記第2絶縁膜越しに第2導電型不純物をイオン注入し、熱拡散により第2導電型不純物を拡散させて第2導電型ウェル領域を選択的に形成する第2形成工程と、
前記第1絶縁膜との間に、前記第2導電型ウェル領域を選択的に露出する第2開口部を有する第1レジストマスクを前記第2絶縁膜上に形成する第1マスク形成工程と、
前記第1絶縁膜および前記第1レジストマスクをマスクにして、前記第2開口部から前記第2導電型ウェル領域に、前記第2絶縁膜越しに拡散係数の異なる2種類の第1導電型不純物を順にイオン注入するイオン注入工程と、
前記イオン注入工程の後に、前記第1レジストマスクを除去する第1マスク除去工程と、
前記第1マスク除去工程の後に、アニール処理により、前記拡散係数の異なる2種類の第1導電型不純物を拡散させて第1導電型ソース領域と第2導電型低不純物濃度領域とを形成するアニール工程と、
前記アニール工程の後に、前記第1絶縁膜および前記第2絶縁膜を除去する絶縁膜除去工程と、
前記絶縁膜除去工程の後に、前記第1導電型半導体基板の一方の主面にゲート絶縁膜を形成する第3形成工程と、
前記第1導電型ソース領域、前記第2導電型低不純物濃度領域、前記第2導電型ウェル領域、および前記第1導電型ドリフト層の表面上に前記ゲート絶縁膜を介してゲート電極を形成する第4形成工程と、
を含み、
前記第2形成工程の後、前記第1マスク形成工程の前に、前記第2導電型ウェル領域の内部に、前記第2導電型ウェル領域よりも不純物濃度の高い第2導電型の第1領域を選択的に形成する第5形成工程をさらに含み、
前記第5形成工程は、
前記第1絶縁膜を覆う第2レジストマスクを形成する第2マスク工程と、
前記第2レジストマスクをマスクとして前記第2絶縁膜越しに第2導電型不純物をイオン注入する第2イオン注入工程と、
前記第2イオン注入工程の後に、前記第2レジストマスクを除去する第2マスク除去工程と、
前記第2マスク除去工程の後に、アニール処理により第2導電型不純物を拡散させて前記第1領域を形成する第1領域形成工程と、を含み、
前記第5形成工程では、
前記第2導電型ウェル領域を、前記第1導電型半導体基板の一方の主面側の前記第1領域と、前記第1導電型半導体基板の他方の主面側において前記第1領域に接し、かつ前記第1領域の周囲を取り囲む、前記第1領域よりも不純物濃度の低い第2領域と、を有する領域にし、
前記第1領域は、前記第2導電型低不純物濃度領域に接し、かつ前記第2導電型低不純物濃度領域を介して前記第1導電型ソース領域と対向する位置に形成され、
前記アニール工程では、前記第2導電型低不純物濃度領域の正味のドーピング濃度を、前記第1領域と隣接する部分で前記第1領域に含まれる第2導電型不純物の濃度よりも低くし、前記第2領域と隣接する部分で前記第2領域に含まれる第2導電型不純物の濃度よりも低くすることを特徴とする半導体装置の製造方法。 - 第1導電型ドリフト層となる第1導電型半導体基板の一方の主面に第1絶縁膜を形成し、前記第1絶縁膜に選択的に第1開口部を形成後、前記第1開口部に前記第1絶縁膜より厚さが薄い第2絶縁膜を形成する第1形成工程と、
前記第1導電型半導体基板の一方の主面に前記第1絶縁膜をマスクにして前記第2絶縁膜越しに第2導電型不純物をイオン注入し、熱拡散により第2導電型不純物を拡散させて第2導電型ウェル領域を選択的に形成する第2形成工程と、
前記第2導電型ウェル領域に、前記第2絶縁膜越しに拡散係数の異なる2種類の第1導電型不純物を順にイオン注入するイオン注入工程と、
アニール処理により、前記拡散係数の異なる2種類の第1導電型不純物を拡散させて第1導電型ソース領域と第2導電型低不純物濃度領域とを形成するアニール工程と、
前記アニール工程の後に、前記第1絶縁膜および前記第2絶縁膜を除去する絶縁膜除去工程と、
前記絶縁膜除去工程の後に、前記第1導電型半導体基板の一方の主面にゲート絶縁膜を形成する第3形成工程と、
前記第1導電型ソース領域、前記第2導電型低不純物濃度領域、前記第2導電型ウェル領域、および前記第1導電型ドリフト層の表面上に前記ゲート絶縁膜を介してゲート電極を形成する第4形成工程と、
を含み、
前記イオン注入工程は、
前記第1絶縁膜との間に、前記第2導電型ウェル領域上に形成された前記第2絶縁膜を選択的に露出する第2開口部を有する第1レジストマスクを前記第2絶縁膜上に形成する第1マスク形成工程と、
前記第1絶縁膜および前記第1レジストマスクをマスクにして、前記第2開口部から前記第2絶縁膜越しに前記第2導電型ウェル領域に、前記拡散係数の異なる2種類の第1導電型不純物のうち、拡散係数の大きい第1導電型不純物をイオン注入する第1イオン注入工程と、
前記第1レジストマスクを除去した後、前記第1絶縁膜との間に、前記第2開口部よりも狭い開口幅で前記第2導電型ウェル領域上に形成された前記第2絶縁膜を選択的に露出する第3開口部を有する第2レジストマスクを前記第2絶縁膜上に形成する第2マスク形成工程と、
前記第1絶縁膜および前記第2レジストマスクをマスクにして、前記第3開口部から前記第2絶縁膜越しに前記第2導電型ウェル領域に、前記拡散係数の異なる2種類の第1導電型不純物のうち、拡散係数の小さい第1導電型不純物をイオン注入する第2イオン注入工程と、を含み、
前記第2形成工程の後、前記第1マスク形成工程の前に、前記第2導電型ウェル領域の内部に、前記第2導電型ウェル領域よりも不純物濃度の高い第2導電型の第1領域を選択的に形成する第5形成工程をさらに含み、
前記第5形成工程は、
前記第1絶縁膜を覆う第3レジストマスクを形成する第3マスク工程と、
前記第3レジストマスクをマスクとして前記第2絶縁膜越しに第2導電型不純物をイオン注入する第3イオン注入工程と、
前記第3イオン注入工程の後に、前記第3レジストマスクを除去する第3マスク除去工程と、
前記第3マスク除去工程の後に、アニール処理により第2導電型不純物を拡散させて前記第1領域を形成する第1領域形成工程と、を含み、
前記第5形成工程では、
前記第2導電型ウェル領域を、前記第1導電型半導体基板の一方の主面側の前記第1領域と、前記第1導電型半導体基板の他方の主面側において前記第1領域に接し、かつ前記第1領域の周囲を取り囲む、前記第1領域よりも不純物濃度の低い第2領域と、を有する領域にし、
前記第1領域は、前記第2導電型低不純物濃度領域に接し、かつ前記第2導電型低不純物濃度領域を介して前記第1導電型ソース領域と対向する位置に形成され、
前記アニール工程では、前記第2導電型低不純物濃度領域の正味のドーピング濃度を、前記第1領域と隣接する部分で前記第1領域に含まれる第2導電型不純物の濃度よりも低くし、前記第2領域と隣接する部分で前記第2領域に含まれる第2導電型不純物の濃度よりも低くすることを特徴とする半導体装置の製造方法。 - 前記拡散係数の異なる2種類の第1導電型不純物のうち、拡散係数の大きい第1導電型不純物がリンであることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記拡散係数の大きい第1導電型不純物のイオン注入のドーズ量は、前記第2導電型不純物のイオン注入のドーズ量よりも少ないことを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。
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