JP6375743B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Description
まず、実施の形態1にかかる半導体装置の製造方法により作製(製造)される半導体装置の一例としてトレンチゲート型超接合半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の構造の一例を示す断面図である。図1に示す実施の形態1にかかる半導体装置は、ドリフト層を、不純物濃度を高めたn型領域(第1導電型半導体領域)3とp型領域(第2導電型半導体領域)4とを基板主面に平行な方向(横方向)に交互に繰り返し配置した並列pn層5とした超接合半導体装置である。n+型(またはp+型)の半導体基板(第4半導体層)1と並列pn層5との間には、n型バッファ層(第3半導体層)2が設けられている。n+型の半導体基板1は例えばn+型ドレイン層となり、図1の超接合半導体装置として例えばMOSFETが構成される。p+型の半導体基板1は例えばp+型コレクタ層となり、図1の超接合半導体装置として例えばIGBTが構成される。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。図9,10は、実施の形態2にかかる半導体装置の製造途中の状態を示す断面図である。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、出発基板(出発ウエハ)として、n型バッファ層2と同程度の不純物濃度を有するn型の半導体基板(すなわちエピタキシャル層を積層していない半導体基板)42を用いる点である。
次に、実施の形態3にかかる半導体装置の製造方法について説明する。図11は、実施の形態3にかかる半導体装置の構造の一例を示す断面図である。図12は、実施の形態3にかかる半導体装置の製造途中の状態を示す断面図である。実施の形態3にかかる半導体装置の製造方法が実施の形態2にかかる半導体装置の製造方法と異なる点は、出発基板(出発ウエハ)として、n+型ドレイン層(またはp+型コレクタ層)と同程度の不純物濃度を有するn+型(またはp+型)の半導体基板51を用いて、半導体基板51のおもて面上に並列pn層5を設けた点である。すなわち、図11に示すように、n型バッファ層が設けられておらず、並列pn層5のn型領域3およびp型領域4はともに半導体基板51に接する。
次に、実施の形態4にかかる半導体装置の製造方法について説明する。図13は、実施の形態4にかかる半導体装置の構造の一例を示す断面図である。実施の形態4にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、並列pn層65のp型領域64がn型バッファ層2に達しない深さで設けられている点である。すなわち、並列pn層65のすべてのn型領域63は、n型バッファ層2側でつながっている。
次に、実施の形態5にかかる半導体装置の製造方法について説明する。図14は、実施の形態5にかかる半導体装置の構造の一例を示す断面図である。実施の形態5にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、並列pn層65のp型領域64がn型バッファ層2に達しない深さで設けられている点である()。すなわち、実施の形態5は、実施の形態3に実施の形態4を適用したものである。
次に、n型バッファ層2の不純物濃度について検証した。図15は、実施例1にかかる半導体装置のn型バッファ層の不純物濃度とアバランシェ電圧BVdssおよびオン抵抗との関係を示す特性図である。図15には、横軸に並列pn層5のn型領域3の不純物濃度に対するp型領域4の不純物濃度の割合(=n型不純物濃度/p型不純物濃度。図15にはSJ全体p/nと記載)を示し、縦軸にアバランシェ電圧BVdssおよびオン抵抗RonAを示す。まず、実施の形態1にかかる半導体装置の製造方法にしたがい、n型バッファ層2の不純物濃度が異なる3つの試料を作製した(以下、実施例1とする)。実施例1は、100Vの低耐圧クラスとした(実施例2においても同様)。n型バッファ層2の厚さを1.8μmとした。各実施例1におけるn型バッファ層2の不純物濃度を、それぞれ、2.0×1015/cm3、5.0×1015/cm3および1.0×1016/cm3とした。実施例1の、n型バッファ層2以外の条件は、実施の形態1にかかる半導体装置の製造方法に例示した100V程度の低耐圧クラスの場合の上記諸条件としている。
次に、並列pn層5となるn-型にドープされた複数段のエピタキシャル層20a〜20cの不純物濃度について検証した。図16は、実施例2にかかる半導体装置の並列pn層の不純物濃度とオン抵抗およびゲート入力電荷量との関係を示す特性図である。図17は、実施例2にかかる半導体装置の並列pn層の不純物濃度とアバランシェ電圧BVdssおよびRonA・Qg特性との関係を示す特性図である。図16には、並列pn層5となるエピタキシャル層20a〜20cの不純物濃度と、オン抵抗RonAおよびゲート入力電荷量Qgとの関係を示す。図17には、並列pn層5となるエピタキシャル層20a〜20cの不純物濃度と、アバランシェ電圧BVdssおよびRonA・Qg特性との関係を示す。RonA・Qg特性とは、オン抵抗RonAとゲート入力電荷量Qgとの積であり、オン抵抗RonAとスイッチング特性とを含む性能指数である。実施例2の、エピタキシャル層20a〜20cの不純物濃度以外の条件は、実施の形態1にかかる半導体装置の製造方法に例示した100V程度の低耐圧クラスの場合の上記諸条件としている。
2 n型バッファ層
3,63 n型領域
4,64 p型領域
5,65 並列pn層
6 トレンチ
7 ゲート絶縁膜
8 ゲート電極
9 p型ベース領域
11 層間絶縁膜
12 おもて面電極
13 裏面電極
20a,20b,20c,20d エピタキシャル層
21a,21b,21c p型不純物領域
22a,22b,22c n型不純物領域
23 n-型カウンター領域
31,33,35 レジストマスク
32,34,36 イオン注入
Claims (11)
- 第1導電型半導体領域と第2導電型半導体領域とを交互に繰り返し配置した並列pn層を備えた半導体装置の製造方法であって、
第1導電型の第1半導体層を堆積する第1堆積工程と、前記第1半導体層に第1導電型不純物および第2導電型不純物をそれぞれ選択的に導入して、前記第1半導体層の表面層に第1の第1導電型不純物領域と第2導電型不純物領域とを交互に繰り返し配置する第1導入工程と、を繰り返し行う第1形成工程と、
熱処理により、前記第1の第1導電型不純物領域および前記第2導電型不純物領域を拡散させることによって前記並列pn層を形成する熱処理工程と、
を含み、
前記第1形成工程では、さらに、最上段の前記第1半導体層の、隣り合う前記第2導電型不純物領域の間に挟まれる部分に第1導電型不純物を選択的に導入して、最上段の前記第1半導体層の前記第2導電型不純物領域側部の第1導電型不純物濃度を高くする第2導入工程を行うことを特徴とする半導体装置の製造方法。 - 前記第2導入工程では、最上段の前記第1半導体層の、隣り合う前記第2導電型不純物領域の間に挟まれる部分に、前記第1半導体層よりも不純物濃度が高く、かつ前記熱処理による前記第2導電型不純物領域の、前記第1の第1導電型不純物領域側への拡散を抑制可能な第1導電型不純物濃度を有する第2の第1導電型不純物領域を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 少なくとも最上段の前記第1半導体層に対して行う前記第1導入工程では、前記第1の第1導電型不純物領域と前記第2導電型不純物領域とを離して配置することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第1導入工程では、
イオン注入により前記第1半導体層に前記第2導電型不純物を選択的に導入し、
最上段の前記第1半導体層に前記第2導電型不純物領域を形成する際に、前記第2導電型不純物領域の深さが前記第1半導体層の深さの1/10以上1/2以下となるように前記イオン注入のドーズ量および加速エネルギーを設定することを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。 - 前記第1半導体層の不純物濃度は、5×1015/cm3以上1×1017/cm3以下であることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置の製造方法。
- 前記第1堆積工程では、前記第1導電型半導体領域よりも不純物濃度が高く、かつ5×1015/cm3以上1×1017/cm3以下の不純物濃度を有する第1導電型の第3半導体層の上に前記第1半導体層を堆積し、
前記熱処理工程の後、
前記第3半導体層を、前記第1半導体層側に対して反対側から研削する薄化工程と、
前記第3半導体層の研削後の面側から前記第3半導体層に不純物を導入し、前記第3半導体層よりも不純物濃度が高い第1導電型または第2導電型の第4半導体層を形成する第3形成工程と、を行うことを特徴とする請求項1〜5のいずれか一つに記載の半導体装置の製造方法。 - 前記第4半導体層の不純物濃度は、1×1015/cm3以上1×1018/cm3以下であることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第1堆積工程では、前記第1導電型半導体領域よりも不純物濃度が高く、かつ1×1015/cm3以上1×1018/cm3以下の不純物濃度を有する第1導電型の第4半導体層の上に、前記第1半導体層を堆積し、
前記熱処理工程の後、前記第4半導体層を、前記第1半導体層側に対して反対側から研削する薄化工程を行うことを特徴とする請求項1〜5のいずれか一つに記載の半導体装置の製造方法。 - 前記第1形成工程後、
前記第1半導体層の表面に第1導電型の第2半導体層を堆積する第2堆積工程と、
前記第2半導体層に金属−酸化膜−半導体からなる絶縁ゲート構造を形成する素子構造形成工程と、をさらに含み、
前記熱処理工程は、前記素子構造形成工程に含まれる各工程のうち、チャネルが形成される半導体領域を拡散させる拡散工程と同時に行うことを特徴とする請求項1〜8のいずれか一つに記載の半導体装置の製造方法。 - 前記第1形成工程では、
前記第1堆積工程の前に、
第5半導体層を堆積する第3堆積工程と、前記第5半導体層に前記第1導電型不純物および第2導電型不純物をそれぞれ選択的に導入して、前記第5半導体層の表面層に前記第1の第1導電型不純物領域と第2導電型不純物領域とを交互に繰り返し配置する第3導入工程と、を繰り返し行い、
前記第3導入工程の後に、前記第1堆積工程と前記第1導入工程との繰り返しを少なくとも1回行い、最上段に前記第1半導体層を形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1導入工程では、
イオン注入により前記第1半導体層に前記第2導電型不純物を選択的に導入し、
繰り返して行われる前記第1導入工程の最初の工程における、前記第2導電型不純物の導入は、繰り返して行われる前記第1導入工程の2回目以降の工程における、前記第2導電型不純物の導入より、イオン注入のドーズ量が少ないことを特徴とする請求項1に記載の半導体装置の製造方法。
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