JP6318786B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 58
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000012535 impurity Substances 0.000 claims description 52
- 238000009792 diffusion process Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 6
- 210000000746 body region Anatomy 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- Computer Hardware Design (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
この態様によれば、PチャネルDMOSトランジスターのゲート電極をN型とし、PチャネルMOSトランジスターのゲート電極をP型とするので、DMOSトランジスターのオン抵抗を低減するとともに、MOSトランジスターのリーク電流を低減することができる。また、PチャネルDMOSトランジスターのソース領域に確実にP型不純物が注入された半導体装置を提供することができる。
これによれば、DMOSトランジスターを埋め込みチャネル化し、オン抵抗を低減することができる。
この態様によれば、PチャネルDMOSトランジスターのオン抵抗を低減するとともに、PチャネルDMOSトランジスターのN型ゲート電極の第1方向側の面にN型の不純物を注入するときに、ソース領域にN型の不純物が注入されることを抑制して、ソース領域に確実にP型不純物を注入することができる。
これによれば、N型ゲート電極のN型拡散層と、NチャネルMOSトランジスターのソース領域及びドレイン領域とを同時に形成することができる。
これによれば、PチャネルDMOSトランジスターのソース領域と、PチャネルMOSトランジスターのソース領域及びドレイン領域とを同時に形成することができる。
図1(A)は、本発明の実施形態に係る半導体装置の一例を示す断面図である。
図1(A)に示される半導体装置1は、PチャネルDMOSトランジスターTr1と、PチャネルMOSトランジスターTr2と、NチャネルMOSトランジスターTr3と、を含んでいる。これらのトランジスターは、いずれも、P型の半導体基板10pの第1方向側の面に位置している。第1方向側は、各図における上側に相当する。半導体基板10pは、P型の不純物を含む単結晶シリコンによって構成されている。
PチャネルDMOSトランジスターTr1は、図1(A)に示されるように左右対称の構造を有しているので、右側と左側とで対応する要素には同一の符号を付し、重複する説明を省略する。半導体基板10pにおけるPチャネルDMOSトランジスターTr1の位置には、N型ウェル11nと、N型ボディー領域12nと、P型オフセット領域13pと、P型ソース領域21pと、N型ボディーコンタクト領域22nと、P型ドレイン領域23pと、が位置している。
図1(A)を再び参照し、半導体基板10pにおけるPチャネルMOSトランジスターTr2の位置には、N型ウェル14nと、P型ソース領域24pと、P型ドレイン領域25pと、が位置している。
N型ウェル14nは、N型の不純物を含んでいる。N型ウェル14nは、半導体基板10pの第1方向側の面に接して位置している。
半導体基板10pにおけるNチャネルMOSトランジスターTr3の位置には、P型ウェル15pと、N型ソース領域26nと、N型ドレイン領域27nと、が位置している。
P型ウェル15pは、P型の不純物を含んでいる。P型ウェル15pは、半導体基板10pの第1方向側の面に接して位置している。
図2〜図5は、本発明の実施形態に係る半導体装置の製造方法を示す断面図である。まず、図2(A)に示されるように、P型の半導体基板10pの第1方向側の面に、N型ウェル11nを形成する。
以上の工程により、半導体装置1を製造することができる。
Claims (5)
- N型ゲート電極を備えたPチャネルDMOSトランジスターと、
P型ゲート電極を備えたPチャネルMOSトランジスターと、
N型ゲート電極を備えたNチャネルMOSトランジスターと、
を具備し、前記PチャネルDMOSトランジスターの前記N型ゲート電極は、前記PチャネルDMOSトランジスターのドレイン側の一方の端部に延在して他の部分よりも高い濃度でN型の不純物を含むN型拡散層と、前記PチャネルDMOSトランジスターのソース側の他方の端部に位置するP型拡散層とを有し、前記N型拡散層は、前記N型ゲート電極の厚み方向にゲート絶縁膜から離れて位置し、前記P型拡散層と前記ゲート絶縁膜との間にP型の不純物の濃度がN型の不純物の濃度よりも低い領域を有する半導体装置。 - 前記P型拡散層は、前記N型ゲート電極の厚み方向に前記ゲート絶縁膜から離れて位置する、請求項1記載の半導体装置。
- 半導体基板の第1方向側の面に位置する第1のN型領域の一部及び第1のP型領域の一部に接して位置する絶縁膜の前記第1方向側にN型ゲート電極を形成する工程(a)と、
前記N型ゲート電極の前記第1方向側の面の一部である第1領域と前記第1のN型領域の前記第1方向側の面の一部である第2領域とにまたがってレジストを形成し、前記N型ゲート電極の前記第1方向側の面と前記第1のN型領域の前記第1方向側の面とにN型の不純物を注入することにより、前記N型ゲート電極の厚み方向に前記絶縁膜から離れた位置に、前記N型ゲート電極の一方の端部に延在して他の部分よりも高い濃度でN型の不純物を含むN型拡散層を形成すると共に、前記第1のN型領域のコンタクト領域を形成し、前記レジストを除去する工程(b)と、
前記第1領域及び前記第2領域にP型の不純物を注入することにより、前記第1領域に前記N型ゲート電極の他方の端部に位置するP型拡散層を、前記P型拡散層と前記絶縁膜との間にP型の不純物の濃度がN型の不純物の濃度よりも低い領域を設けるように形成すると共に、前記第2領域にソース領域を形成する工程(c)と、
を具備する半導体装置の製造方法。 - 工程(b)は、NチャネルMOSトランジスターのソース領域及びドレイン領域を形成することをさらに含む、請求項3記載の半導体装置の製造方法。
- 工程(c)は、PチャネルMOSトランジスターのソース領域及びドレイン領域を形成することをさらに含む、請求項3又は請求項4記載の半導体装置の製造方法。
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JP2014077928A JP6318786B2 (ja) | 2014-04-04 | 2014-04-04 | 半導体装置及びその製造方法 |
US14/669,714 US9425197B2 (en) | 2014-04-04 | 2015-03-26 | Semiconductor device and manufacturing method for the same |
TW104110756A TWI644413B (zh) | 2014-04-04 | 2015-04-01 | 半導體裝置及其製造方法 |
CN201510155592.9A CN104979348B (zh) | 2014-04-04 | 2015-04-02 | 半导体装置及其制造方法 |
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JPH03155157A (ja) * | 1989-11-13 | 1991-07-03 | Seiko Epson Corp | 半導体装置の製造方法 |
JPH07221291A (ja) | 1994-02-02 | 1995-08-18 | Seiko Instr Inc | 半導体装置及びその製造方法 |
SE513283C2 (sv) * | 1996-07-26 | 2000-08-14 | Ericsson Telefon Ab L M | MOS-transistorstruktur med utsträckt driftregion |
JPH10200123A (ja) | 1997-01-14 | 1998-07-31 | Hitachi Ltd | 半導体素子およびそれを用いた液晶表示装置 |
JP2000077613A (ja) * | 1998-08-28 | 2000-03-14 | Nec Corp | 半導体装置の製造方法 |
JP3683185B2 (ja) * | 2001-03-12 | 2005-08-17 | 株式会社リコー | 定電圧回路 |
JP2005093456A (ja) | 2003-09-11 | 2005-04-07 | Shindengen Electric Mfg Co Ltd | 横型短チャネルdmos及びその製造方法並びに半導体装置 |
JP2007243117A (ja) | 2006-03-13 | 2007-09-20 | Oki Electric Ind Co Ltd | 高耐圧mosトランジスタの製造方法 |
JP5040387B2 (ja) * | 2007-03-20 | 2012-10-03 | 株式会社デンソー | 半導体装置 |
JP4700043B2 (ja) * | 2007-11-07 | 2011-06-15 | Okiセミコンダクタ株式会社 | 半導体素子の製造方法 |
JP4645861B2 (ja) * | 2008-07-03 | 2011-03-09 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2010045312A (ja) * | 2008-08-18 | 2010-02-25 | Seiko Epson Corp | 半導体装置と、電子部品及び半導体装置の製造方法 |
JP5801713B2 (ja) * | 2011-12-28 | 2015-10-28 | 株式会社ソシオネクスト | 半導体装置とその製造方法、およびcanシステム |
JP2014053414A (ja) * | 2012-09-06 | 2014-03-20 | Denso Corp | 半導体装置の製造方法 |
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