JP6770177B2 - デプレッションモード接合電界効果トランジスタと統合されたデバイスおよび該デバイスを製造するための方法 - Google Patents
デプレッションモード接合電界効果トランジスタと統合されたデバイスおよび該デバイスを製造するための方法 Download PDFInfo
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- JP6770177B2 JP6770177B2 JP2019511877A JP2019511877A JP6770177B2 JP 6770177 B2 JP6770177 B2 JP 6770177B2 JP 2019511877 A JP2019511877 A JP 2019511877A JP 2019511877 A JP2019511877 A JP 2019511877A JP 6770177 B2 JP6770177 B2 JP 6770177B2
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8086—Thin film JFET's
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Description
Claims (15)
- デプレッションモード接合電界効果トランジスタと統合されたデバイスであって、前記デバイスが、接合電界効果トランジスタ(JFET)領域と電源デバイス領域とに分割されており、前記デバイスが、
第1の伝導型ドレインであり、前記ドレインの一部分が前記JFET領域を形成するように構成され、前記ドレインの残りの部分が前記電源デバイス領域を形成するように構成された、第1の伝導型ドレインと、
前記デバイスの前面を向く前記第1の伝導型ドレインの表面に配置された第1の伝導型領域であり、前記第1の伝導型領域の一部分が前記JFET領域を形成するように構成され、前記第1の伝導型領域の残りの部分が前記電源デバイス領域を形成するように構成された、第1の伝導型領域と
を備え、前記JFET領域が、
前記第1の伝導型領域内に形成された少なくとも2つの第2の伝導型ウェル領域であり、前記第1の伝導型が第2の伝導型とは反対である、第2の伝導型ウェル領域と、
第1の伝導型を有する少なくとも2つのJFETソースであり、それぞれ前記少なくとも2つの第2の伝導型ウェル領域内に形成された少なくとも2つのJFETソースと、
前記JFETソース上に形成された前記JFETソースの金属電極であり、前記JFETソースと接触した金属電極と、
隣り合った2つのJFETソース間に形成された、前記第1の伝導型である横方向チャネル領域であり、前記横方向チャネル領域の2つの端部が前記隣り合った2つのJFETソースと接触した、横方向チャネル領域と、
第2の伝導型ウェル領域上に形成されたJFET金属ゲートと、
を備え、
前記第2の伝導型ウェル領域は、複数の第1ウェルと、各第1ウェル内にそれぞれ配置され、各第1ウェルよりイオン濃度が高い複数の第2ウェルと、を含み、
第1ウェルは、前記電源デバイス領域から前記JFET領域を絶縁するために前記JFET領域と前記電源デバイス領域との境界に配置されていることを特徴とするデバイス。 - 請求項1に記載のデバイスであって、前記JFET領域が、少なくとも2つのJFETゲートオーム接点をさらに備え、前記JFETゲートオーム接点がそれぞれ、前記隣り合った2つのJFETソースが配置された第2の伝導型ウェル領域のうちのそれぞれのウェル領域内に形成されており、かつ前記JFETソースの前記横方向チャネル領域から離れた1つの側に配置されており、前記第2の伝導型を有しており、前記JFET金属ゲートが、前記JFETゲートオーム接点上に、前記JFETゲートオーム接点と接触して形成されていることを特徴とするデバイス。
- 請求項1に記載のデバイスであって、前記電源デバイスが、垂直二重拡散金属酸化物半導体電界効果トランジスタ(VDMOS)であることを特徴とするデバイス。
- 請求項3に記載のデバイスであって、前記電源デバイス領域が、
ゲートと、
第2のウェルと、
前記第2のウェル内に配置されたVDMOS第1の伝導型ソースと、
前記第2のウェル内の前記VDMOS第1の伝導型ソースの下に配置された第1の非クランプ誘導性スイッチング領域であり、前記第2の伝導型を有し、かつ前記第2のウェルのイオン濃度よりも高いイオン濃度を有する第1の非クランプ誘導性スイッチング領域と
を備えることを特徴とするデバイス。 - 請求項4に記載のデバイスであって、前記JFETソースの下の第2のウェル内に配置された第2の非クランプ誘導性スイッチング領域をさらに備え、前記第2の非クランプ誘導性スイッチング領域が、前記第2の伝導型を有し、かつ前記第2のウェルのイオン濃度よりも高いイオン濃度を有することを特徴とするデバイス。
- 請求項4に記載のデバイスであって、前記ゲートの下の両側に2つの第2のウェルがそれぞれ配置されており、前記2つの第2のウェル内に前記VDMOS第1の伝導型ソースが形成されており、前記2つの第2のウェルのうちのそれぞれのウェル内で前記VDMOS第1の伝導型ソースが2つのブロックに分割されていることを特徴とするデバイス。
- 請求項6に記載のデバイスであって、前記VDMOS第1の伝導型ソースの前記2つのブロック間に第2の伝導型オーム接点領域が形成されていることを特徴とするデバイス。
- 請求項1に記載のデバイスであって、前記第1の伝導型がN型であり、前記第2の伝導型がP型であり、前記第1の伝導型領域がN型エピタキシャル層であることを特徴とするデバイス。
- デプレッションモード接合電界効果トランジスタと統合されたデバイスを製造するための方法であって、前記デバイスが、接合電界効果トランジスタ(JFET)領域および電源デバイス領域を含み、前記方法が、
その上に第1の伝導型領域が形成された、第1の伝導型の基板を用意するステップであり、前記第1の伝導型が第2の伝導型とは反対であるステップと、
前記第1の伝導型領域に第2の伝導型のイオンを注入し、ドライブインにより前記第1の伝導型領域内に複数の第1のウェルを形成するステップと、
前記第1の伝導型領域の表面にフィールド酸化物層およびゲート酸化物層を順番に成長させ、前記第1の伝導型領域の前記表面にポリシリコン層を形成するステップと、
前記第1の伝導型のイオンを注入して、前記JFET領域内に少なくとも2つのJFETソースを形成し、前記電源デバイス領域内に電源デバイスソースを形成するステップと、
フォトエッチングおよびエッチングを実行して、隣り合った2つのJFETソース間の位置の上方のポリシリコンおよび他の表面介在物を除去してチャネル注入窓を形成し、前記チャネル注入窓に前記第1の伝導型のイオンを注入して横方向チャネル領域を形成するステップと、
コンタクトホールをフォトエッチングおよびエッチングし、金属層を堆積させ、前記コンタクトホールに前記金属層を充填して、前記JFETソースの金属電極、JFET金属ゲートおよび前記電源デバイスソースの金属接点をそれぞれ形成するステップと、
前記第1伝導型領域内に前記複数の第1ウェルを形成する前記ステップは、前記第1ウェルを前記JFET領域と前記電源デバイス領域との境界に形成して、前記電源デバイス領域から前記JFET領域を絶縁し、
前記第1伝導型領域の表面上に前記ポリシリコン層を形成する前記ステップの後に、前記第1伝導型領域に前記第2伝導型のイオンを注入し、ドライブインによって複数の第2ウェルを形成するステップであって、前記第2ウェルは異なる第1ウェル内にそれぞれ形成された前記JFET領域内に配置され、各前記第2ウェルは各前記第1ウェルよりもイオン濃度が高いことを特徴とする方法。 - 請求項9に記載の方法であって、前記JFET領域内に前記JFETソースを形成し、前記電源デバイス領域内に前記電源デバイスソースを形成する前記ステップが、前記第2のウェルに前記第1の伝導型のイオンを注入して、それぞれ前記JFET領域内に前記JFETソースを形成し、前記電源デバイス領域内に前記電源デバイスソースを形成することであることを特徴とする方法。
- 請求項9に記載の方法であって、前記JFET領域内に前記JFETソースを形成し、前記電源デバイス領域内に前記電源デバイスソースを形成する前記ステップの後、フォトエッチングおよびエッチングを実行して、前記隣り合った2つのJFETソース間の前記位置の上方の前記ポリシリコンおよび他の表面介在物を除去して前記チャネル注入窓を形成する前記ステップの前に、前記電源デバイス領域の前記第2のウェルに前記第2の伝導型のイオンを注入して、前記電源デバイスソースおよび前記JFETソースの下の前記第2のウェル内に非クランプ誘導性スイッチング領域を形成するステップをさらに含み、注入エネルギーが、前記第1の伝導型のイオンを注入する前記ステップの注入エネルギーよりも大きいことを特徴とする方法。
- 請求項11に記載の方法であって、前記JFET領域内に前記JFETソースを形成し、前記電源デバイス領域内に前記電源デバイスソースを形成する前記ステップの後、前記電源デバイス領域の前記第2のウェルに前記第2の伝導型のイオンを注入する前記ステップの前に、注入障壁層を形成するステップをさらに含むことを特徴とする方法。
- 請求項9に記載の方法であって、前記第1の伝導型がN型であり、前記第2の伝導型がP型であり、前記第1の伝導型領域がN型エピタキシャル層であり、前記電源デバイスが、垂直二重拡散金属酸化物半導体電界効果トランジスタ(VDMOS)であることを特徴とする方法。
- 請求項9に記載の方法であって、前記チャネル注入窓に前記第1の伝導型のイオンを注入する前記ステップで、注入される前記イオンがヒ素イオンであり、前記注入されたイオンのエネルギーが100keVから180keVであり、前記注入されたイオンのドーズ量が2e12cm−2から7e12cm−2であることを特徴とする方法。
- 請求項11に記載の方法であって、前記チャネル注入窓に前記第1の伝導型のイオンを注入する前記ステップで、注入される前記イオンがリンイオンであり、前記注入されたイオンのエネルギーが60keVから120keVであり、前記注入されたイオンのドーズ量が2e12cm−2から7e12cm−2であることを特徴とする方法。
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