JP5802231B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 102
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Description
図1(a)は、本実施形態に係る半導体装置を例示する平面図であり、(b)は(a)に示すA−A’線による断面図である。
なお、図を見やすくするために、図1(a)においては、ゲート絶縁膜21及びゲート電極22の図示を省略している。
図2(a)〜(c)は、本実施形態に係る半導体装置の製造方法を例示する工程断面図である。
図3は、本実施形態に係る半導体装置の動作を例示する断面図である。
図1(a)及び(b)に示すように、ゲート電極22とソース電極23に同電位、例えば、接地電位が印加されているときは、ドレイン電極24に正電位が印加されても、n−形のドリフト層12とp−形のウェル13との界面を起点として空乏層(図示せず)が拡がり、ソース・ドレイン間に電流が流れない。
上述の如く、本実施形態においては、枠状領域32の幅が縦型MOSFETのゲート長Lとなる。そして、枠状領域32の幅は、図2(c)に示す1回のイオン注入により、決定することができる。このため、ゲート長Lの長さを精度よく制御することができる。この結果、本実施形態に係る半導体装置は、微細化してもゲート長の相対的な変動量が小さく、特性が安定する。例えば、ゲート長が短くなることによりリーク電流が増加したり、ゲート長が長くなることによりオン抵抗が増加したりすることを抑制できる。
図4(a)は、比較例に係る半導体装置を例示する断面図であり、(b)は(a)に示す領域Bを示す一部拡大断面図である。
Claims (6)
- 第1導電形層内に第2導電形の第1領域を形成する工程と、
前記第1導電形層における前記第1領域の直上域の周辺部に不純物を注入することにより、下端が前記第1領域に達し、上端が前記第1導電形層の上面に達し、前記第1導電形層における前記第1領域の直上域の中央部に位置しその形状が上方から見て帯状である第1部分を囲む第2導電形の第2領域を形成する工程と、
前記第1部分の長手方向両側に位置し、前記第1部分及び前記第2領域に接し、前記第1導電形層の前記第1部分を除く第2部分に接しない領域に、その実効的な不純物濃度が前記第1導電形層の実効的な不純物濃度よりも高い第1導電形のコンタクト層を形成する工程と、
前記第2領域上、並びに、その両側に配置された前記第1部分上及び前記第2部分上にゲート絶縁膜を形成する工程と、
前記第2部分に接続される第1電極を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成すると共に、前記第1部分及び前記コンタクト層に接続される第2電極を形成する工程と、
を備えた半導体装置の製造方法。 - 第1電極と、
前記第1電極に接続された第1導電形の第1半導体層と、
前記第1半導体層に接した第2導電形の第2半導体層と、
前記第2半導体層に接し、第1導電形であり、その不純物濃度が前記第2半導体層の不純物濃度よりも低く、前記第2半導体層によって前記第1半導体層から区画された第3半導体層と、
前記第2半導体層、並びに、その両側に配置された前記第1半導体層及び前記第3半導体層を覆うゲート絶縁膜と、
前記ゲート絶縁膜上に設けられたゲート電極と、
前記第3半導体層に接続された第2電極と、
を備えた半導体装置。 - 第1電極と、
前記第1電極に接続された第1導電形の第1半導体層と、
前記第1半導体層に接した第2導電形の第2半導体層と、
前記第2半導体層に接し、第1導電形であり、その不純物濃度が前記第1半導体層の不純物濃度と等しく、前記第2半導体層によって前記第1半導体層から区画された第3半導体層と、
前記第2半導体層上、並びに、その両側に配置された前記第1半導体層上及び前記第3半導体層上に設けられたゲート絶縁膜と、
前記ゲート絶縁膜上に設けられたゲート電極と、
前記第3半導体層に接続された第2電極と、
を備えた半導体装置。 - 前記第2半導体層は、
前記第3半導体層の直下域に配置された第1領域と、
前記第3半導体層を囲む第2領域と、
を有した請求項2または3に記載の半導体装置。 - 第1導電形であり、その実効的な不純物濃度が前記第3半導体層の実効的な不純物濃度よりも高く、前記第3半導体層、前記第2半導体層及び前記第2電極に接し、前記第1半導体層に接していないコンタクト層をさらに備え、
上方から見て、前記第3半導体層の形状は帯状であり、
前記コンタクト層は、前記第3半導体層の長手方向両側に配置されている請求項4記載の半導体装置。 - 前記第1半導体層、前記第2半導体層及び前記第3半導体層は、炭化珪素により形成されている請求項2〜5のいずれか1つに記載の半導体装置。」
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CN201310408423.2A CN104064597A (zh) | 2013-03-22 | 2013-09-10 | 半导体器件和制造该器件的方法 |
US14/023,287 US9142612B2 (en) | 2013-03-22 | 2013-09-10 | Semiconductor device and method of fabricating the same |
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JP3206727B2 (ja) | 1997-02-20 | 2001-09-10 | 富士電機株式会社 | 炭化けい素縦型mosfetおよびその製造方法 |
JP2004319964A (ja) | 2003-03-28 | 2004-11-11 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US7074643B2 (en) * | 2003-04-24 | 2006-07-11 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same |
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