JP5801713B2 - 半導体装置とその製造方法、およびcanシステム - Google Patents
半導体装置とその製造方法、およびcanシステム Download PDFInfo
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- JP5801713B2 JP5801713B2 JP2011288084A JP2011288084A JP5801713B2 JP 5801713 B2 JP5801713 B2 JP 5801713B2 JP 2011288084 A JP2011288084 A JP 2011288084A JP 2011288084 A JP2011288084 A JP 2011288084A JP 5801713 B2 JP5801713 B2 JP 5801713B2
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Description
p型半導体基板と、
前記p型半導体基板の表面から第1の深さで形成された第1のn型ウェルと、
前記p型半導体基板の表面から第1の深さより深い第2の深さで形成された第2のn型ウェルと、
前記第1および第2のn型ウェル内にそれぞれ形成された、第1および第2のp型バックゲート領域と、
前記第1および第2のp型バックゲート領域内にそれぞれ形成された、第1および第2のn型ソース領域と、
前記第1のn型ウェル内の、前記第1のp型バックゲート領域を挟んで、前記第1のn型ソース領域と対向する位置に形成された、第1のn型ドレイン領域と、
前記第2のn型ウェル内の、前記第2のp型バックゲート領域を挟んで、前記第2のn型ソース領域と対向する位置に形成された、第2のn型ドレイン領域と、
前記第1のn型ウェルの表面部の、前記第1のp型バックゲート領域と前記第1のn型ドレイン領域との間、および、前記第2のn型ウェルの表面部の、前記第2のp型バックゲート領域と前記第2のn型ドレイン領域との間、に形成された素子分離膜と、
を有し、前記第1のn型ウェル内に第1トランジスタ、前記第2のn型ウェル内に前記第1トランジスタより逆耐圧の高い第2のトランジスタが形成されている半導体装置
が提供される。
通常NDMOSトランジスタ
閾値電圧Vth: 1.01V (Vd=15V,Psub=PBG=S=0V、Id=2μAの時のVg電圧)
オン電流Ion: 5.79mA (Vd=40V,Psub=PBG=S=0V、Vg=5Vの時のドレイン電流)
BVsd:42V以上 (Vg=0V,Psub=PBG=S=0V、Id=0.1μAの時のVd電圧)
負耐圧:−10V (Vd=0V,Psub=0V,G=S=フローティング、p型バックゲートウェル電流=−0.1μAの時のp型バックゲートウェルの電圧)
負耐圧NDMOSトランジスタ
閾値電圧Vth: 1.0V (Vd=15V,Psub=PBG=S=0V、Id=2μAの時のVg電圧)
オン電流Ion: 5.73mA (Vd=40V,Psub=PBG=S=0V、Vg=5Vの時のドレイン電流)
BVsd:42V以上 (Vg=0V,Psub=PBG=S=0V、Id=0.1μAの時のVd電圧)
負耐圧:−35V (Vd=0V,Psub=0V,G=S=フローティング、p型バックゲートウェルの電流=−0.1μAの時のp型バックゲートウェルの電圧)
通常NDMOSトランジスタ保護用ツェナーダイオード
ツェナー電圧:6.5V
負耐圧:−10V (nウェル=0V,Psub=0V,カソード=フローティング、アノード=0.1μAの時のアノード電圧)
負耐圧NDMOSトランジスタ保護用ツェナーダイオード
ツェナー電圧:6.5V
負耐圧:−35V (nウェル=0V,Psub=0V,カソード=フローティング、アノード=0.1μAの時のアノード電圧)
CANは、共通のバスにより、複数の車載モジュール間の通信を行なう。車載のため、バッテリ電源電圧(12V〜24V)が通常印加される電圧範囲となる。走行上のトラブルにより、LSIのGND電位が浮いてしまっても、CANの信号線のバス電位を変動させないことが要求される。
PBG p型バックゲート領域、
S ソース領域、
D ドレイン領域、
CH チャネル領域、
G ゲート電極、
DMOS ダブルディフューズドMOS、
ZD ツェナーダイオード
STI フィールド酸化膜、素子分離膜、
Claims (10)
- p型半導体基板と、
前記p型半導体基板の表面から第1の深さで形成された第1のn型ウェルと、
前記p型半導体基板の表面から第1の深さより深い第2の深さで形成された第2のn型ウェルと、
前記第1および第2のn型ウェル内にそれぞれ形成された、第1および第2のp型バックゲート領域と、
前記第1および第2のp型バックゲート領域内にそれぞれ形成された、第1および第2のn型ソース領域と、
前記第1のn型ウェル内の、前記第1のp型バックゲート領域を挟んで、前記第1のn型ソース領域と対向する位置に形成された、第1のn型ドレイン領域と、
前記第2のn型ウェル内の、前記第2のp型バックゲート領域を挟んで、前記第2のn型ソース領域と対向する位置に形成された、第2のn型ドレイン領域と、
前記第1のn型ウェルの表面部の、前記第1のp型バックゲート領域と前記第1のn型ドレイン領域との間、および、前記第2のn型ウェルの表面部の、前記第2のp型バックゲート領域と前記第2のn型ドレイン領域との間、に形成された素子分離膜と、
を有し、前記第1のn型ウェル内に第1トランジスタ、前記第2のn型ウェル内に前記第1トランジスタより逆耐圧の高い第2のトランジスタが形成されている半導体装置。 - 前記第1のトランジスタは、前記第2のトランジスタより面内面積が小さい、請求項1記載の半導体装置。
- 前記p型半導体基板に形成された第3のn型ウェルと、前記第3のn型ウェル内に形成された第1p型アノード領域と、前記第1p型アノード領域内に形成された第1n型カソード領域と、を含む第1ツェナーダイオードと、
前記p型半導体基板に形成された第4のn型ウェルと、前記第4のn型ウェル内に形成された第2p型アノード領域と、前記第2p型アノード領域内に形成された第2n型カソード領域と、を含む第2ツェナーダイオードと、をさらに有し、
前記第4のn型ウェルは、前記第3のn型ウェルよりも、前記p型半導体基板の表面から深く形成され、
前記第2ツェナーダイオードは、前記第1ツェナーダイオードよりも逆耐圧が高い請求項1又は2に記載の半導体装置。 - 前記第1ツェナーダイオードは、前記第2ツェナーダイオードよりも面内面積が小さい請求項3に記載の半導体装置。
- p型半導体基板にn型不純物をイオン注入して第1のn型ウェルを形成し、
熱処理することにより、前記n型不純物を拡散させ、深さを拡大した第1の拡大n型ウェルとし、
前記p型半導体基板に素子分離膜を形成し、
前記p型半導体基板にn型不純物をイオン注入して第2のn型ウェルを形成し、
前記第1の拡大n型ウェルおよび前記第2のn型ウェル内にp型不純物をイオン注入し、第1および第2のp型バックゲート領域を形成し、
前記第1および第2のp型バックゲート領域上方から素子分離膜に掛かる第1および第2のゲート電極を形成し、
前記第1および第2のp型バックゲート領域内に、n型不純物をイオン注入して、第1および第2のn型ソース領域を形成し、
前記第1の拡大n型ウェルの、前記素子分離膜を介して、前記第1のバックゲート領域と対向する位置および、前記第2のn型ウェルの、前記素子分離膜を介して前記第2のバックゲート領域と対向する位置にn型不純物をイオン注入して、それぞれ第1および第2のn型ドレイン領域を形成する、
半導体装置の製造方法。 - 前記素子分離膜の形成が、前記p型半導体基板にトレンチを形成し、トレンチ内に絶縁膜を堆積し、不要部を除去することによって形成される請求項5記載の半導体装置の製造方法。
- 第1および第2のバックゲート領域を形成するイオン注入が、注入条件の異なるイオン注入で行なわれる請求項5又は6記載の半導体装置の製造方法。
- 前記第1のn型ウェルを形成する際、同時に第3のn型ウェルを形成し、
前記第1のp型バックゲート領域を形成する際、同時に前記第3のn型ウェル内に第1のp型アノード領域を形成し、
前記第1、第2のn型ソース領域を形成する際、同時に前記第1のp型アノード領域内に第1のn型カソード領域を形成し、
第1のツェナーダイオードを形成する、請求項5〜7のいずれか1項に記載の半導体装置の製造方法。 - 前記第2のn型ウェルを形成する際、同時に第4のn型ウェルを形成し、
前記第2のp型バックゲート領域を形成する際、同時に前記第4のn型ウェル内に第2のp型アノード領域を形成し、
前記第1、第2のn型ソース領域を形成する際、同時に前記第2のp型アノード領域内に第2のn型カソード領域を形成し、
第2のツェナーダイオードを形成する、請求項5〜8のいずれか1項に記載の半導体装置の製造方法。 - 複数の通信モジュールを含むCANシステムであり、
逆流阻止回路として、請求項1〜4のいずれか1項に記載の半導体装置を含むCANシステム。
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