JP5581972B2 - 電子部品、及び電子装置 - Google Patents
電子部品、及び電子装置 Download PDFInfo
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- JP5581972B2 JP5581972B2 JP2010241338A JP2010241338A JP5581972B2 JP 5581972 B2 JP5581972 B2 JP 5581972B2 JP 2010241338 A JP2010241338 A JP 2010241338A JP 2010241338 A JP2010241338 A JP 2010241338A JP 5581972 B2 JP5581972 B2 JP 5581972B2
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- electronic component
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Description
また、複数の電子部品側ランドのうち、面積が最大の電子部品側ランドにはんだ非着領域を設けたので、特にボイドが発生し易い電子部品側ランドと基板側ランドとの間のはんだ接合部におけるボイドの残存を防止し、電子部品と基板との間のはんだによる接合面積を安定して確保することができる。
また、はんだ非着領域として、電子部品側ランドにおける基板側ランドとの対向面にはんだ絶縁層を設けたので、容易にはんだ非着領域を形成することができ、発生したボイド内の気体を、はんだ絶縁層と基板側ランドとの間に形成された空隙を介してはんだ接合部の外部に排出することができる。
また、複数の電子部品側ランドのうち、面積が最大の電子部品側ランドにはんだ非着領域を設けたので、特にボイドが発生し易い電子部品側ランドと基板側ランドとの間のはんだ接合部におけるボイドの残存を防止し、電子部品と基板との間のはんだによる接合面積を安定して確保することができる。
また、複数の電子部品側ランドのうち、面積が最大の電子部品側ランドにはんだ非着領域を設けたので、特にボイドが発生し易い電子部品側ランドと基板側ランドとの間のはんだ接合部におけるボイドの残存を防止し、電子部品と基板との間のはんだによる接合面積を安定して確保することができる。
最初に、実施の形態に係る電子装置の構成について説明する。電子装置は、基板と、当該基板に実装される電子部品とを備えている。図1は電子部品を例示する図であり、図1(a)は電子部品の側面図、図1(b)は電子部品の平面図である。また、図2は基板を例示する図であり、図2(a)は基板の平面図、図2(b)は基板の側面図である。
図1に示すように、電子部品3は、電子部品側ランド30を備えている。この電子部品側ランド30は、基板への実装時に当該基板上の基板側ランドに対向する。この電子部品側ランド30は、電子部品3が基板と対向する面において、例えばエッチングやアディティブ法等の公知の方法により、所望の形状の銅等の金属薄膜として形成されている。図1では、四角形の平面形状を有する電子部品側ランド30が複数設けられている場合を例示している。
電子部品側ランド30は、アース用ランド31、及び入出力用ランド32を備えている。アース用ランド31は、電子部品3を設置させるためのランドであり、電子部品3における基板との対向面の略中央に設けられている。入出力用ランド32は、電子部品3と基板との間での信号の入出力を行うためのランドであり、アース用ランド31の周囲に設けられている。また、入出力用ランド32は、補強用ランド33を備えている。補強用ランド33は、電子部品3と基板との間での信号の入出力を行うと共に、電子部品3と基板との接続を補強するためのランドであり、電子部品3における基板との対向面の外周近傍(本実施の形態では各隅部)に設けられている。この補強用ランド33は、他の入出力用ランド32よりも面積が大きく形成されている。なお、各補強用ランド33の面積は等しく形成されている。このように、他の入出力用ランド32よりも面積が大きい補強用ランド33を電子部品3の各隅部(図1(b)では4隅)に設けることにより、電子部品3と基板との間のはんだ接合部におけるはんだの疲労断線を防止し、接続信頼性を高めることができる。これらの電子部品側ランド30の形状の詳細については後述する。
図2に示すように、基板2は、基板側ランド20を備えている。この基板側ランド20は、基板2が電子部品3と対向する面において、例えばエッチングやアディティブ法等の公知の方法により、所望の形状の銅等の金属薄膜として形成されている。図2では、四角形の平面形状を有する基板側ランド20が複数設けられている場合を例示している。これらの各基板側ランド20と、当該各基板側ランド20に対向する各電子部品側ランド30とは、それぞれの配置位置において、対を成して設置されている。この基板側ランド20の形状の詳細については後述する。
次に、電子部品側ランド30及び基板側ランド20の形状について説明する。補強用ランド33を除く電子部品側ランド30(すなわち、アース用ランド31、及び補強用ランド33以外の入出力用ランド32)の形状は、各電子部品側ランド30に対向する基板側ランド20(すなわち、各電子部品側ランド30と対になる基板側ランド20)の形状と略同一となるように形成されている。
次に、上述のように構成された電子部品3及び電子装置の作用について説明する。図3は電子部品3の基板2への実装状態を示す図であり、図3(a)は各電子部品側ランド30と各基板側ランド20との間にはんだを供給した状態を例示した側断面図、図3(b)は基板2への電子部品3の実装後の状態を例示した側断面図である。なお図3は、図1(b)に例示した電子部品3におけるA−A’断面、及び図2(a)に例示した基板2におけるB−B’断面を示している。
このように本実施の形態によれば、基板側ランド20の形状と、当該基板側ランド20に対向する補強用ランド33の形状とが異なるように、補強用ランド33における基板側ランド20との対向面に溝34を設けたので、発生したボイド内の気体を溝34と基板側ランド20との間に形成された空隙を介してはんだ接合部の外部に排出することができる。これにより、はんだ接合部におけるボイドの残存を防止し、電子部品3と基板2との間のはんだによる接合面積を安定して確保することができる。
以上、本発明に係る実施の形態について説明したが、本発明の具体的な構成及び手段は、特許請求の範囲に記載した各発明の技術的思想の範囲内において、任意に改変及び改良することができる。以下、このような変形例について説明する。
まず、発明が解決しようとする課題や発明の効果は、上述の内容に限定されるものではなく、発明の実施環境や構成の細部に応じて異なる可能性があり、上述した課題の一部のみを解決したり、上述した効果の一部のみを奏することがある。
上述の実施の形態では、補強用ランド33を溝34で分割し、この溝34により分割された補強用ランド33の平面形状が、当該補強用ランド33に対向する位置の基板側ランド20の平面形状と異なるようにした場合を例として説明したが、溝34の位置における補強用ランド33の厚さが、当該溝34に対向する位置の基板側ランド20の厚さと異なるようにしてもよい。図4は変形例における電子部品3の基板2への実装状態を示す図であり、図4(a)は各電子部品側ランド30と各基板側ランド20との間にはんだを供給した状態を例示した側断面図、図4(b)は基板2への電子部品3の実装後の状態を例示した側断面図である。この図4の例では、上述の実施の形態と同様に補強用ランド33が溝34で分割されており、さらに基板側ランド20にも、補強用ランド33の溝34に対向する位置に溝21が設けられている。但し、補強用ランド33の溝34の位置における当該補強用ランド33の厚さが0、すなわち補強用ランド33が溝34で完全に分割されているのに対し、当該溝34に対向する位置(すなわち基板側ランド20の溝21の位置)の基板側ランド20の厚さは、0よりも大きい所定の厚さとなっている。なお、基板側ランド20の溝21は、当該基板側ランド20が補強用ランド33に対向する面に向かって開放されるように設けられている。このように構成した補強用ランド33と基板側ランド20との間にはんだを供給すると、完全に分割されている補強用ランド33の溝34の位置にははんだが流れないものの、完全に分割されていない基板側ランド20の表面には溝21の位置を含めてはんだが流れる。これにより、図4(b)に示したように、補強用ランド33の溝34と基板側ランド20の溝21との間には、V字型の空隙が形成される。従って、補強用ランド33の溝と基板側ランド20の溝との間に矩形断面の空隙が形成された状態と比較して、電子部品3と基板2との間のはんだによる接合面積を十分に確保することができる。
2 基板
3 電子部品
20 基板側ランド
21、34 溝
30 電子部品側ランド
31 アース用ランド
32 入出力用ランド
33 補強用ランド
Claims (7)
- 基板に実装される電子部品であって、
前記基板への実装時に当該基板上の基板側ランドに対向する電子部品側ランドを複数備え、
前記基板側ランドの形状と、当該基板側ランドに対向する前記電子部品側ランドの形状とが異なるように、当該電子部品側ランドにおける前記基板側ランドとの対向面にはんだ非着領域を設け、
複数の前記電子部品側ランドのうち、面積が最大の電子部品側ランドに前記はんだ非着領域を設けた、
電子部品。 - 当該電子部品における前記基板との対向面の外周近傍に前記複数の電子部品側ランドを備え、
当該電子部品における前記基板との対向面の外周近傍に設けられた前記複数の電子部品側ランドのうち、面積が最大の電子部品側ランドに前記はんだ非着領域を設けた、
請求項1に記載の電子部品。 - 基板に実装される電子部品であって、
前記基板への実装時に当該基板上の基板側ランドに対向する電子部品側ランドを備え、
前記基板側ランドの形状と、当該基板側ランドに対向する前記電子部品側ランドの形状とが異なるように、当該電子部品側ランドにおける前記基板側ランドとの対向面にはんだ非着領域を設け、
前記はんだ非着領域として、前記電子部品側ランドにおける前記基板側ランドとの対向面に溝を設け、
前記溝の位置における前記電子部品側ランドの厚さが、当該溝に対向する位置の前記基板側ランドの厚さと異なる、
電子部品。 - 基板に実装される電子部品であって、
前記基板への実装時に当該基板上の基板側ランドに対向する電子部品側ランドを備え、
前記基板側ランドの形状と、当該基板側ランドに対向する前記電子部品側ランドの形状とが異なるように、当該電子部品側ランドにおける前記基板側ランドとの対向面にはんだ非着領域を設け、
前記はんだ非着領域として、前記電子部品側ランドにおける前記基板側ランドとの対向面にはんだ絶縁層を設けた、
電子部品。 - 前記電子部品側ランドを前記はんだ非着領域で分割し、
前記はんだ非着領域により分割された前記電子部品側ランドの平面形状が、当該電子部品側ランドに対向する位置の前記基板側ランドの平面形状と異なる、
請求項1から4のいずれか一項に記載の電子部品。 - 基板に実装される電子部品であって、
前記基板への実装時に当該基板上の基板側ランドに対向する電子部品側ランドを複数備え、
前記電子部品側ランドは、当該電子部品における前記基板との対向面の略中央に設けられたアース用ランドと、前記アース用ランドの周囲に設けられた入出力用ランドと、を有し、
前記入出力用ランドは、当該電子部品における前記基板との対向面の外周近傍に設けられた補強用ランドを有し、
前記補強用ランドは、他の前記入出力用ランドよりも面積が大きく形成され、
前記基板側ランドの形状と、当該基板側ランドに対向する前記補強用ランドの形状とが異なるように、当該補強用ランドにおける前記基板側ランドとの対向面にはんだ非着領域を設け、
複数の前記電子部品側ランドのうち、面積が最大の電子部品側ランドに前記はんだ非着領域を設けた、
電子部品。 - 基板と、当該基板に実装される電子部品と、を備える電子装置であって、
前記基板は、基板側ランドを備え、
前記電子部品は、前記基板への実装時に前記基板側ランドに対向する電子部品側ランドを複数備え、
前記基板側ランドの形状と、当該基板側ランドに対向する前記電子部品側ランドの形状とが異なるように、当該基板側ランドにおける当該電子部品側ランドとの対向面、及び/又は、当該電子部品側ランドにおける当該基板側ランドとの対向面にはんだ非着領域を設け、
複数の前記電子部品側ランドのうち、面積が最大の電子部品側ランドに前記はんだ非着領域を設けた、
電子装置。
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EP11180886.1A EP2447994A3 (en) | 2010-10-27 | 2011-09-12 | Electronic component and electronic device |
US13/235,111 US8787033B2 (en) | 2010-10-27 | 2011-09-16 | Electronic component and electronic device |
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JP2010241338A Expired - Fee Related JP5581972B2 (ja) | 2010-10-27 | 2010-10-27 | 電子部品、及び電子装置 |
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US (1) | US8787033B2 (ja) |
EP (1) | EP2447994A3 (ja) |
JP (1) | JP5581972B2 (ja) |
CN (1) | CN102458048B (ja) |
Families Citing this family (5)
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ITMI20111776A1 (it) * | 2011-09-30 | 2013-03-31 | St Microelectronics Srl | Sistema elettronico per saldatura a rifusione |
DE102012105297A1 (de) * | 2012-06-19 | 2013-12-19 | Endress + Hauser Gmbh + Co. Kg | Verfahren zum Verbinden eines Bauteils mit einem Träger über eine Lötung und Bauteil zum Verbinden mit einem Träger |
JP6504762B2 (ja) | 2014-08-05 | 2019-04-24 | キヤノン株式会社 | モジュールの製造方法 |
US10177107B2 (en) * | 2016-08-01 | 2019-01-08 | Xilinx, Inc. | Heterogeneous ball pattern package |
US11830810B2 (en) * | 2020-05-07 | 2023-11-28 | Wolfspeed, Inc. | Packaged transistor having die attach materials with channels and process of implementing the same |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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US3599326A (en) * | 1969-01-27 | 1971-08-17 | Philco Ford Corp | Method of forming electrical connections with solder resistant surfaces |
JPS607758A (ja) * | 1983-06-27 | 1985-01-16 | Nec Corp | 半導体装置 |
JP2859143B2 (ja) | 1994-11-08 | 1999-02-17 | 松下電器産業株式会社 | モジュール部品 |
US7654432B2 (en) * | 1997-05-27 | 2010-02-02 | Wstp, Llc | Forming solder balls on substrates |
US6169253B1 (en) * | 1998-06-08 | 2001-01-02 | Visteon Global Technologies, Inc. | Solder resist window configurations for solder paste overprinting |
US6267009B1 (en) * | 1998-12-14 | 2001-07-31 | Endress + Hauser Gmbh + Co. | Capacitive pressure sensor cells or differential pressure sensor cells and methods for manufacturing the same |
US7034402B1 (en) * | 2000-06-28 | 2006-04-25 | Intel Corporation | Device with segmented ball limiting metallurgy |
JP2004095867A (ja) * | 2002-08-30 | 2004-03-25 | Casio Comput Co Ltd | 電子部品 |
JP2005223090A (ja) * | 2004-02-04 | 2005-08-18 | Murata Mfg Co Ltd | 実装基板と部品との接続構造 |
JP2006060141A (ja) * | 2004-08-23 | 2006-03-02 | Sharp Corp | 印刷基板及びこれを用いた表面実装型半導体パッケージの実装方法 |
US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
US20080003803A1 (en) * | 2006-06-30 | 2008-01-03 | Pei-Haw Tsao | Semiconductor package substrate for flip chip packaging |
US20080142964A1 (en) * | 2006-12-13 | 2008-06-19 | Haixiao Sun | Tubular-shaped bumps for integrated circuit devices and methods of fabrication |
US20080150101A1 (en) * | 2006-12-20 | 2008-06-26 | Tessera, Inc. | Microelectronic packages having improved input/output connections and methods therefor |
JP2008227271A (ja) * | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | 電子装置および電子部品実装方法 |
US7667335B2 (en) * | 2007-09-20 | 2010-02-23 | Stats Chippac, Ltd. | Semiconductor package with passivation island for reducing stress on solder bumps |
JP4999806B2 (ja) * | 2008-09-18 | 2012-08-15 | アルプス電気株式会社 | 電子モジュール及びその製造方法 |
JP5487691B2 (ja) | 2009-04-08 | 2014-05-07 | 株式会社デンソー | 車両制御装置、車両制御プログラム |
-
2010
- 2010-10-27 JP JP2010241338A patent/JP5581972B2/ja not_active Expired - Fee Related
-
2011
- 2011-09-12 EP EP11180886.1A patent/EP2447994A3/en not_active Withdrawn
- 2011-09-16 US US13/235,111 patent/US8787033B2/en not_active Expired - Fee Related
- 2011-10-18 CN CN201110319259.9A patent/CN102458048B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20120106116A1 (en) | 2012-05-03 |
JP2012094712A (ja) | 2012-05-17 |
US8787033B2 (en) | 2014-07-22 |
EP2447994A2 (en) | 2012-05-02 |
EP2447994A3 (en) | 2018-01-24 |
CN102458048A (zh) | 2012-05-16 |
CN102458048B (zh) | 2015-10-21 |
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