JP5395382B2 - トランジスタの作製方法 - Google Patents
トランジスタの作製方法 Download PDFInfo
- Publication number
- JP5395382B2 JP5395382B2 JP2008202513A JP2008202513A JP5395382B2 JP 5395382 B2 JP5395382 B2 JP 5395382B2 JP 2008202513 A JP2008202513 A JP 2008202513A JP 2008202513 A JP2008202513 A JP 2008202513A JP 5395382 B2 JP5395382 B2 JP 5395382B2
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- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor
- film
- region
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Electroluminescent Light Sources (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本実施の形態では、表示装置に用いられるボトムゲート型の薄膜トランジスタ(TFT)に関して図面を参照して説明する。図1は、画素の一部における薄膜トランジスタと薄膜トランジスタに電気的に接続された画素電極の断面図と上面図であり、図1(A)は、図1(B)におけるA−Bの断面に対応している。
本実施の形態では、上記実施の形態1で示した表示装置に用いられるボトムゲート型の薄膜トランジスタの作製方法に関して図面を参照して説明する。以下の説明では、nチャネル型の薄膜トランジスタについて説明する。
本実施の形態では、上記実施の形態と異なる薄膜トランジスタを有する表示装置に関して図18を参照して説明する。
本実施の形態では、上記実施の形態と異なる薄膜トランジスタを有する表示装置に関して図面を参照して説明する。具体的には、上記実施の形態では、チャネルエッチ型の薄膜トランジスタを示したが、保護層160を設けた構成(チャネル保護型)としてもよい(図15参照)。
本実施の形態では、上記実施の形態で示した薄膜トランジスタを有する表示装置の一形態として液晶表示パネルに関して図11を参照して説明する。図11(A)は、第1の基板4001上に形成された薄膜トランジスタ4010及び液晶素子4013を第2の基板4006との間にシール材4005によって封止したパネルの上面図であり、図11(B)は、図11(A)のC−Dにおける断面を示している。
本実施の形態では、上記実施の形態で示した薄膜トランジスタを有する発光装置の一形態として発光表示パネルに関して図12を参照して説明する。図12(A)は、第1の基板4001上に形成された薄膜トランジスタ4010及び発光素子4011を第2の基板4006との間にシール材4005によって封止したパネルの上面図であり、図12(B)は、図12(A)のE−Fにおける断面を示している。
本発明により得られる表示装置等は、アクティブマトリクス型表示装置モジュールに用いることができる。即ち、それらを表示部に組み込んだ電子機器全てに本発明を実施できる。
101 ゲート電極
102 ゲート絶縁膜
103 半導体層
104 半導体層
105 半導体層
106 導電膜
107 絶縁膜
108 画素電極
109 不純物領域
110 薄膜トランジスタ
121 マスク
122 マスク
140a 半導体層
140b 半導体層
160 保護層
180 処理容器
182 ガス供給部
184 マイクロ波発生装置
200 プラズマ
900 基板
901 ゲート電極
902 ゲート絶縁膜
903 半導体層
904 半導体層
905a ソース領域
905b ドレイン領域
906a ソース電極
906b ドレイン電極
907 不純物領域
921 画素部
922 信号線駆動回路
923 走査線駆動回路
924 チューナ
925 映像信号増幅回路
926 映像信号処理回路
927 コントロール回路
928 信号分割回路
929 音声信号増幅回路
930 音声信号処理回路
931 制御回路
932 入力部
933 スピーカー
105a ソース領域
105b ドレイン領域
106a ソース電極
106b ドレイン電極
1110 ロード室
1115 アンロード室
1120 共通室
1121 搬送手段
1122 ゲートバルブ
1128 カセット
1130 基板
1200 共通室
2001 筐体
2002 表示用パネル
2003 主画面
2004 モデム
2005 受信機
2006 リモコン操作機
2007 表示部
2008 サブ画面
2009 スピーカー部
2301 携帯電話機
2302 表示部
2303 操作部
2401 本体
2402 表示部
2501 照明部
2502 傘
2503 可変アーム
2504 支柱
2505 台
2506 電源
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4007 充填材
4008 液晶
4009 薄膜トランジスタ
4010 薄膜トランジスタ
4011 発光素子
4012 透明導電膜
4013 液晶素子
4014 配線
4016 接続端子
4017 画素電極
4018 FPC
4019 異方性導電膜
4030 画素電極
4031 対向電極
4035 スペーサ
4041 薄膜トランジスタ
Claims (3)
- 基板上にゲート電極を形成し、
前記ゲート電極上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に、微結晶半導体を有する第1の半導体層と、非晶質半導体を有する第2の半導体層と、一導電型を付与する不純物が添加された第3の半導体層とを順に積層させて形成し、
前記第3の半導体層上に導電膜を形成し、
前記導電膜上にマスクを選択的に形成し、
前記マスクを用いて、前記導電膜と前記第3の半導体層をエッチングすることによって、ソース電極及びドレイン電極とソース領域及びドレイン領域とを形成し、
前記ソース電極及びドレイン電極の端部を選択的にエッチングすることによって、前記ソース領域及び前記ドレイン領域の端部の表面を露出させ、
前記ソース電極及び前記ドレイン電極をマスクとして、前記ソース領域及び前記ドレイン領域と異なる導電型の不純物元素を導入することによって、前記ソース領域と前記ドレイン領域との間の前記第2の半導体層に不純物領域を形成することを特徴とするトランジスタの作製方法。 - 請求項1において、
前記第1の半導体層を前記第2の半導体層より薄く形成することを特徴とするトランジスタの作製方法。 - 請求項1または請求項2において、
前記非晶質半導体をn型で形成し、
前記不純物元素としてp型の不純物元素を用いることを特徴とするトランジスタの作製方法。
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-
2008
- 2008-08-06 US US12/222,256 patent/US7968885B2/en not_active Expired - Fee Related
- 2008-08-06 JP JP2008202513A patent/JP5395382B2/ja not_active Expired - Fee Related
-
2011
- 2011-03-30 US US13/075,436 patent/US8633485B2/en not_active Expired - Fee Related
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2013
- 2013-10-18 JP JP2013216941A patent/JP5728064B2/ja not_active Expired - Fee Related
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US20090039351A1 (en) | 2009-02-12 |
JP2009060096A (ja) | 2009-03-19 |
JP2014057080A (ja) | 2014-03-27 |
US20110175091A1 (en) | 2011-07-21 |
US7968885B2 (en) | 2011-06-28 |
JP5728064B2 (ja) | 2015-06-03 |
US8633485B2 (en) | 2014-01-21 |
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