JP5357510B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP5357510B2 JP5357510B2 JP2008281711A JP2008281711A JP5357510B2 JP 5357510 B2 JP5357510 B2 JP 5357510B2 JP 2008281711 A JP2008281711 A JP 2008281711A JP 2008281711 A JP2008281711 A JP 2008281711A JP 5357510 B2 JP5357510 B2 JP 5357510B2
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Description
図1は、本発明の実施の形態1による半導体集積回路装置において、その外形の一例を示す断面図である。図1に示す半導体集積回路装置SIPは、パッケージ基板PKBD上に複数((n+1)個)の半導体チップCHIP0〜CHIPnが順次積層搭載されたシステムインパッケージの構造となっている。CHIP0〜CHIPnは、それぞれ、トランジスタ形成面TR0〜TRnが下向きに配置される。CHIP0のトランジスタ形成面TR0には、端子(バンプ)BP0が形成され、これがPKBD上面の端子に接続される。PKBD上面の端子は、内部に形成された配線層を介して下面に形成された端子(ボール)BLに接続され、このBLが図示しないマザーボード等に接続される。
前述した実施の形態1では、各半導体チップの内部コア回路で用いる電源電圧の中から最も低い電源電圧をデータ通信用の電源電圧として用いたが、本実施の形態2では、この最も低い電源電圧よりも更に低い電圧でデータ通信を行う例を示す。
BF_DO データ送信回路
BL ボール
BP バンプ
BUS バス
CHIP 半導体チップ
CK クロック信号
CSI 受信選択信号
CSO 送信選択信号
DI 受信データ信号
DO 送信データ信号
GND 接地電圧
IV インバータ回路
LGC 内部コア回路
ML 配線層
MN NMISトランジスタ
MP PMISトランジスタ
ND ナンド回路
NR ノア回路
P_DIO データ送受信端子
P_VDD,P_VDDH,P_VDDL 電源電圧端子
PKBD パッケージ基板
REF リファレンス電圧
SA センスアンプ回路
SAEN センスアンプ活性化信号
SIP 半導体集積回路装置
TR トランジスタ形成面
TSV 貫通ビア
VDD,VDDL,VDDH 電源電圧
Claims (3)
- 所定の処理機能を実現し第1電源電圧で動作する第1内部コア回路と、外部との間のインタフェースを担う第1データ送受信回路とを備えた第1半導体チップと、
所定の処理機能を実現し第2電源電圧で動作する第2内部コア回路と、外部との間のインタフェースを担う第2データ送受信回路とを備えた第2半導体チップと、
所定の処理機能を実現し第3電源電圧で動作する第3内部コア回路と、外部との間のインタフェースを担う第3データ送受信回路とを備えた第3半導体チップとを備え、
前記第1半導体チップと前記第2半導体チップと前記第3半導体チップは、互いに積層搭載され、
前記第1データ送受信回路と前記第2データ送受信回路と前記第3データ送受信回路は、第1貫通ビアで接続され、前記第1電源電圧かつ前記第2電源電圧かつ前記第3電源電圧よりも低い第4電源電圧を用いて、前記第1貫通ビアを介して高電位側となる論理レベルのデータ送受信を行うことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1半導体チップは、第1電源電圧端子を備え、
前記第2半導体チップは、第2電源電圧端子を備え、
前記第3半導体チップは、第3電源電圧端子を備え、
前記第1電源電圧端子と前記第2電源電圧端子と前記第3電源電圧端子は、第2貫通ビアで接続され、
前記第2貫通ビアには、前記第4電源電圧が供給されることを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記第1内部コア回路で使用されるMISトランジスタのゲート絶縁膜の厚さは、前記第1データ送受信回路で使用されるMISトランジスタのゲート絶縁膜の厚さと同じであり、
前記第2内部コア回路で使用されるMISトランジスタのゲート絶縁膜の厚さは、前記第2データ送受信回路で使用されるMISトランジスタのゲート絶縁膜の厚さと同じであり、
前記第3内部コア回路で使用されるMISトランジスタのゲート絶縁膜の厚さは、前記第3データ送受信回路で使用されるMISトランジスタのゲート絶縁膜の厚さと同じであることを特徴とする半導体集積回路装置。
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JP2008281711A JP5357510B2 (ja) | 2008-10-31 | 2008-10-31 | 半導体集積回路装置 |
US12/606,812 US8253227B2 (en) | 2008-10-31 | 2009-10-27 | Semiconductor integrated circuit device |
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JP2008281711A JP5357510B2 (ja) | 2008-10-31 | 2008-10-31 | 半導体集積回路装置 |
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JP5357510B2 true JP5357510B2 (ja) | 2013-12-04 |
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US8339474B2 (en) * | 2008-08-20 | 2012-12-25 | Freescale Semiconductor, Inc. | Gain controlled threshold in denoising filter for image signal processing |
CN102044522A (zh) * | 2010-07-15 | 2011-05-04 | 黄婷婷 | 多晶片堆迭结构 |
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KR101190682B1 (ko) | 2010-09-30 | 2012-10-12 | 에스케이하이닉스 주식회사 | 3차원 적층 반도체 집적회로 |
US8427833B2 (en) | 2010-10-28 | 2013-04-23 | International Business Machines Corporation | Thermal power plane for integrated circuits |
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KR101278270B1 (ko) * | 2011-08-26 | 2013-06-24 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US8987066B2 (en) | 2012-01-03 | 2015-03-24 | Honeywell International Inc. | Processing unit comprising integrated circuits including a common configuration of electrical interconnects |
US9082764B2 (en) | 2012-03-05 | 2015-07-14 | Corning Incorporated | Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same |
JP6207228B2 (ja) | 2013-05-10 | 2017-10-04 | キヤノン株式会社 | 集積回路装置およびその構成方法 |
KR102034155B1 (ko) * | 2013-08-09 | 2019-10-18 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 이용하는 반도체 시스템 |
US9177831B2 (en) * | 2013-09-30 | 2015-11-03 | Intel Corporation | Die assembly on thin dielectric sheet |
US8929169B1 (en) * | 2014-05-13 | 2015-01-06 | Sandisk Technologies Inc. | Power management for nonvolatile memory array |
KR102422456B1 (ko) * | 2017-12-22 | 2022-07-19 | 삼성전자주식회사 | 데이터 송수신 장치, 이를 포함하는 반도체 패키지 및 데이터 송수신 방법 |
KR20210063496A (ko) * | 2019-11-22 | 2021-06-02 | 삼성전자주식회사 | 프로세싱 회로를 포함하는 메모리 장치, 그리고 시스템 온 칩과 메모리 장치를 포함하는 전자 장치 |
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JP3249871B2 (ja) * | 1993-12-22 | 2002-01-21 | 三菱電機株式会社 | 半導体記憶装置 |
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JP2008159736A (ja) * | 2006-12-22 | 2008-07-10 | Elpida Memory Inc | 半導体装置及びその電源供給方法 |
JP2009070967A (ja) * | 2007-09-12 | 2009-04-02 | Kawasaki Microelectronics Kk | 半導体集積回路 |
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2008
- 2008-10-31 JP JP2008281711A patent/JP5357510B2/ja not_active Expired - Fee Related
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US20100109096A1 (en) | 2010-05-06 |
JP2010109264A (ja) | 2010-05-13 |
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