JP4729881B2 - 薄膜半導体装置の製造方法および薄膜半導体装置 - Google Patents
薄膜半導体装置の製造方法および薄膜半導体装置 Download PDFInfo
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- JP4729881B2 JP4729881B2 JP2004227470A JP2004227470A JP4729881B2 JP 4729881 B2 JP4729881 B2 JP 4729881B2 JP 2004227470 A JP2004227470 A JP 2004227470A JP 2004227470 A JP2004227470 A JP 2004227470A JP 4729881 B2 JP4729881 B2 JP 4729881B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
Description
有することを特徴としている。先ず第1工程では、基板上に半導体薄膜を設け、半導体薄
膜上にゲート絶縁膜を設け、ゲート絶縁膜上にゲート電極を設け、ゲート絶縁膜をゲート
電極をマスクにパターニングして薄膜トランジスタを形成する。次に第2工程では、薄膜
トランジスタを覆う状態で、少なくとも最下層を構成する膜中に水酸基(−OH基)が含
有されない層間絶縁膜をマグネトロンスパッタ法により基板上に形成する。その後第3工
程では、水分雰囲気中において熱処理を行うことにより半導体薄膜のダングリングボンド
に酸素を結合させると共に、前記層間絶縁膜を緻密化する。
縁膜と、ゲート絶縁膜上のゲート電極とを有する薄膜トランジスタと、この薄膜トランジ
スタを覆う状態でマグネトロンスパッタ法により基板上に設けられ、少なくとも最下層を
構成する膜中に水酸基が含有されない層間絶縁膜とを備えている。ゲート絶縁膜は、ゲー
ト電極をマスクにパターニングされている。水分雰囲気中における熱処理によって半導体
薄膜のダングリングボンドに酸素または水素を結合させると共に、層間絶縁膜は緻密化さ
れる。
図3は、下記実施形態において使用される処理装置の一例を示す構成図である。この図に示す処理装置1は、気密にシールされた圧力容器2と、圧力容器2内で気密にシールされた処理室3と、処理室3を加熱するヒータ4と、圧力容器2に接続された昇圧ライン5および減圧ライン6と、処理室3に接続されたガス供給ライン7及び排気ライン8とから構成されている。
図4〜図6の断面工程図は、第1実施形態の薄膜半導体装置の製造方法を説明するための図である。ここでは、これらの図を用いて薄膜トランジスタとしてトップゲート型のTFTを有する表示用駆動パネル(薄膜半導体装置)の製造方法を説明する。
次に、図7の断面工程図を用いて第2実施形態の半導体薄膜の製造方法を説明する。
次に、図8の断面工程図を用いて第3実施形態の半導体薄膜の製造方法を説明する。この図に示す第3実施形態の製造方法が、図7を用いて説明した第2実施形態の製造方法とことなるところは、層間絶縁膜44”の構成にある、
次に、図9,10の断面工程図を用いて第4実施形態の半導体薄膜の製造方法を説明する。ここでは、これらの図を用いて薄膜トランジスタとしてボトムゲート型のTFTの製造方法を説明し、さらにはこれを用いた表示用駆動パネル(薄膜半導体装置)の製造方法を説明する。
Claims (6)
- 基板上に半導体薄膜を設け、前記半導体薄膜上にゲート絶縁膜を設け、前記ゲート絶縁 膜上にゲート電極を設け、前記ゲート絶縁膜を前記ゲート電極をマスクにパターニングして薄膜トランジスタを形成する第1工程と、
前記薄膜トランジスタを覆う状態で、少なくとも最下層を構成する膜中に水酸基が含有
されない層間絶縁膜をマグネトロンスパッタ法により前記基板上に形成する第2工程と、
前記層間絶縁膜を形成した後、水分雰囲気中での熱処理により前記半導体薄膜のダング
リングボンドに酸素または水素を結合させると共に、前記層間絶縁膜を緻密化する第3工
程とを行う薄膜半導体装置の製造方法。 - 前記第2工程では、窒化シリコンからなる前記層間絶縁膜を形成する
請求項1記載の薄膜半導体装置の製造方法。 - 前記第2工程では、窒化シリコン膜と酸化シリコン膜との積層構造からなる前記層間絶
縁膜を形成する
請求項1記載の薄膜半導体装置の製造方法。 - 前記第3工程の熱処理は加圧雰囲気で行われる
請求項1記載の薄膜半導体装置の製造方法。 - 前記第1工程では、前記薄膜トランジスタのゲート絶縁膜として膜中に水酸基が含有されない絶縁膜を形成する
請求項1記載の薄膜半導体装置の製造方法。 - 基板上の半導体薄膜と、前記半導体薄膜上のゲート絶縁膜と、前記ゲート絶縁膜上のゲート電極とを有する薄膜トランジスタと、
前記薄膜トランジスタを覆う状態でマグネトロンスパッタ法により前記基板上に設けら
れ、少なくとも最下層を構成する膜中に水酸基が含有されない層間絶縁膜とを備え、
前記ゲート絶縁膜は、前記ゲート電極をマスクにパターニングされており、
水分雰囲気中における熱処理によって、前記半導体薄膜のダングリングボンドに酸素ま
たは水素を結合させると共に、前記層間絶縁膜は緻密化されている
薄膜半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004227470A JP4729881B2 (ja) | 2004-08-04 | 2004-08-04 | 薄膜半導体装置の製造方法および薄膜半導体装置 |
TW094126431A TW200618305A (en) | 2004-08-04 | 2005-08-03 | Method of manufacturing thin film semiconductor device and thin film semiconductor device |
US11/196,109 US20060051903A1 (en) | 2004-08-04 | 2005-08-03 | Method of manufacturing thin film semiconductor device, and thin film semiconductor device |
KR1020050071211A KR20060049275A (ko) | 2004-08-04 | 2005-08-04 | 박막 반도체 장치의 제조 방법 및 박막 반도체 장치 |
US12/327,939 US20090142912A1 (en) | 2004-08-04 | 2008-12-04 | Method of Manufacturing Thin Film Semiconductor Device and Thin Film Semiconductor Device |
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JP2004227470A JP4729881B2 (ja) | 2004-08-04 | 2004-08-04 | 薄膜半導体装置の製造方法および薄膜半導体装置 |
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JP2006049535A JP2006049535A (ja) | 2006-02-16 |
JP4729881B2 true JP4729881B2 (ja) | 2011-07-20 |
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JP2004227470A Expired - Fee Related JP4729881B2 (ja) | 2004-08-04 | 2004-08-04 | 薄膜半導体装置の製造方法および薄膜半導体装置 |
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US (2) | US20060051903A1 (ja) |
JP (1) | JP4729881B2 (ja) |
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Families Citing this family (11)
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JP3917698B2 (ja) * | 1996-12-12 | 2007-05-23 | 株式会社半導体エネルギー研究所 | レーザーアニール方法およびレーザーアニール装置 |
JP2008078166A (ja) * | 2006-09-19 | 2008-04-03 | Sony Corp | 薄膜半導体装置の製造方法および薄膜半導体装置 |
KR100810639B1 (ko) * | 2006-12-06 | 2008-03-07 | 삼성에스디아이 주식회사 | 박막트랜지스터와 그 제조방법 및 이를 구비한유기전계발광표시장치 |
KR100810638B1 (ko) * | 2006-12-06 | 2008-03-07 | 삼성에스디아이 주식회사 | 박막트랜지스터와 그 제조방법 및 이를 구비한유기전계발광표시장치 |
TWI345836B (en) | 2007-06-12 | 2011-07-21 | Au Optronics Corp | Dielectric layer and thin film transistor,display planel,and electro-optical apparatus |
KR101015847B1 (ko) * | 2008-01-18 | 2011-02-23 | 삼성모바일디스플레이주식회사 | 박막트랜지스터와 그 제조방법 및 이를 구비한유기전계발광표시장치 |
KR101340098B1 (ko) * | 2009-09-17 | 2014-01-02 | 가부시끼가이샤 도시바 | 반도체 장치의 제조 방법 |
JP6489942B2 (ja) * | 2015-05-29 | 2019-03-27 | 東芝メモリ株式会社 | 半導体デバイスの製造方法 |
US9627484B1 (en) * | 2015-10-12 | 2017-04-18 | International Business Machines Corporation | Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer |
CN108630605B (zh) * | 2017-03-22 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
CN109523912B (zh) * | 2018-12-13 | 2021-03-16 | 厦门天马微电子有限公司 | 显示面板和显示装置 |
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JPH0714849A (ja) * | 1993-06-18 | 1995-01-17 | Fujitsu Ltd | 薄膜トランジスタの製造方法 |
JPH0855858A (ja) * | 1994-08-15 | 1996-02-27 | Sony Corp | 半導体装置の製法 |
JP2001006090A (ja) * | 1999-06-21 | 2001-01-12 | Matsushita Electric Ind Co Ltd | 交通流量管理方法 |
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JP2814009B2 (ja) * | 1990-06-05 | 1998-10-22 | 三菱電機株式会社 | 半導体装置の製造方法 |
US6136728A (en) * | 1996-01-05 | 2000-10-24 | Yale University | Water vapor annealing process |
US5815226A (en) * | 1996-02-29 | 1998-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of fabricating same |
TW333671B (en) * | 1996-03-25 | 1998-06-11 | Sanyo Electric Co | The semiconductor device and its producing method |
TW332320B (en) * | 1997-01-03 | 1998-05-21 | Nat Science Council | A low temperature deposited hydrogenated amorphous silicon nitride and amorphous silicon hydrogen composite passivation layer, the deposition method and the semiconductor |
US6274887B1 (en) * | 1998-11-02 | 2001-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
US6346730B1 (en) * | 1999-04-06 | 2002-02-12 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device having a pixel TFT formed in a display region and a drive circuit formed in the periphery of the display region on the same substrate |
JP3437843B2 (ja) * | 2001-07-06 | 2003-08-18 | 沖電気工業株式会社 | 絶縁膜の形成方法及び集積回路の製造方法 |
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- 2005-08-03 US US11/196,109 patent/US20060051903A1/en not_active Abandoned
- 2005-08-03 TW TW094126431A patent/TW200618305A/zh not_active IP Right Cessation
- 2005-08-04 KR KR1020050071211A patent/KR20060049275A/ko not_active Application Discontinuation
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Patent Citations (3)
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JPH0714849A (ja) * | 1993-06-18 | 1995-01-17 | Fujitsu Ltd | 薄膜トランジスタの製造方法 |
JPH0855858A (ja) * | 1994-08-15 | 1996-02-27 | Sony Corp | 半導体装置の製法 |
JP2001006090A (ja) * | 1999-06-21 | 2001-01-12 | Matsushita Electric Ind Co Ltd | 交通流量管理方法 |
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US20090142912A1 (en) | 2009-06-04 |
TWI312577B (ja) | 2009-07-21 |
US20060051903A1 (en) | 2006-03-09 |
JP2006049535A (ja) | 2006-02-16 |
KR20060049275A (ko) | 2006-05-18 |
TW200618305A (en) | 2006-06-01 |
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