JP4504397B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP4504397B2 JP4504397B2 JP2007141538A JP2007141538A JP4504397B2 JP 4504397 B2 JP4504397 B2 JP 4504397B2 JP 2007141538 A JP2007141538 A JP 2007141538A JP 2007141538 A JP2007141538 A JP 2007141538A JP 4504397 B2 JP4504397 B2 JP 4504397B2
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- memory cell
- bit line
- sense amplifier
- voltage
- clamp voltage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Description
図1は、本発明の第1の実施の形態に係るNAND型フラッシュメモリの要部の回路図である。
図4は、本発明の第2の実施の形態に係るNAND型フラッシュメモリの要部の回路図である。
Claims (5)
- 複数の平行に配置されたビット線及びこれらビット線と直交する複数のワード線に沿ってマトリクス状に配置され前記ビット線にデータが読み出される複数のメモリセルからなるメモリセルアレイと、
前記ビット線の電流を検出して前記各メモリセルからの読み出しデータを判定するセンスアンプと、
前記センスアンプと前記ビット線との間に接続されてゲートに印加されるクランプ電圧によって前記ビット線の充電時の電圧を決定するクランプ用トランジスタと、
前記クランプ電圧を、前記センスアンプから選択される前記メモリセルまでの距離が長いほど大きくなるように生成するクランプ電圧生成回路と、
を備えたことを特徴とする半導体記憶装置。 - 前記メモリセルアレイは、前記ビット線の延びる方向に複数のブロックに分割され、
前記クランプ電圧生成回路は、前記選択されるメモリセルが属するブロックのアドレスに基づいて前記クランプ電圧を決定するものである
ことを特徴とする請求項1記載の半導体記憶装置。 - 前記センスアンプ及び前記クランプ用トランジスタは、前記メモリセルアレイの前記ビット線の延びる方向の両側に半数ずつ分散配置され、
前記クランプ電圧生成回路は、前記メモリセルアレイの一方の側のクランプ用トランジスタに第1のクランプ電圧を供給し、前記メモリセルアレイの他方の側のクランプ用トランジスタに第2のクランプ電圧を供給するものである
ことを特徴とする請求項1又は2記載の半導体記憶装置。 - ビット線に沿って複数のメモリセルを直列接続してなるメモリセル列の一端が第1の選択ゲートトランジスタを介して前記ビット線に接続され前記メモリセル列の他端が第2の選択ゲートトランジスタを介してソース線に接続されてなるNANDストリングを前記ビット線及びこれと直交するワード線に沿ってマトリクス状に配置してなるメモリセルアレイと、
選択された前記メモリセルに前記ビット線を介して流れる電流の大小によって前記選択されたメモリセルからの読み出しデータを判定するセンスアンプと、
前記センスアンプと前記ビット線との間に接続されてゲートに印加されるクランプ電圧によって前記ビット線の充電時の電圧を決定するクランプ用トランジスタと、
前記クランプ電圧を、前記センスアンプから選択されたNANDストリングまでの距離が長いほど大きくなるように生成するクランプ電圧生成回路と、
を備えたことを特徴とする半導体記憶装置。 - 前記クランプ電圧生成回路は、読み出しアドレスの少なくとも一部を入力し、前記入力された値に応じた大きさの前記クランプ電圧を生成するものであることを特徴とする請求項4記載の半導体記憶装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2007141538A JP4504397B2 (ja) | 2007-05-29 | 2007-05-29 | 半導体記憶装置 |
US12/128,324 US7924632B2 (en) | 2007-05-29 | 2008-05-28 | Semiconductor memory device |
KR1020080049539A KR100912149B1 (ko) | 2007-05-29 | 2008-05-28 | 반도체 기억 장치 |
US13/044,657 US8194472B2 (en) | 2007-05-29 | 2011-03-10 | Semiconductor memory device |
US13/447,491 US8472264B2 (en) | 2007-05-29 | 2012-04-16 | Semiconductor memory device |
Applications Claiming Priority (1)
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JP2007141538A JP4504397B2 (ja) | 2007-05-29 | 2007-05-29 | 半導体記憶装置 |
Publications (2)
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JP2008299891A JP2008299891A (ja) | 2008-12-11 |
JP4504397B2 true JP4504397B2 (ja) | 2010-07-14 |
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JP2007141538A Active JP4504397B2 (ja) | 2007-05-29 | 2007-05-29 | 半導体記憶装置 |
Country Status (3)
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US (3) | US7924632B2 (ja) |
JP (1) | JP4504397B2 (ja) |
KR (1) | KR100912149B1 (ja) |
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2008
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US20110158006A1 (en) | 2011-06-30 |
KR100912149B1 (ko) | 2009-08-14 |
JP2008299891A (ja) | 2008-12-11 |
US20090201738A1 (en) | 2009-08-13 |
US20120236645A1 (en) | 2012-09-20 |
US8472264B2 (en) | 2013-06-25 |
KR20080104989A (ko) | 2008-12-03 |
US8194472B2 (en) | 2012-06-05 |
US7924632B2 (en) | 2011-04-12 |
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