JP4024681B2 - プラスチック半導体パッケージ - Google Patents
プラスチック半導体パッケージ Download PDFInfo
- Publication number
- JP4024681B2 JP4024681B2 JP2002568424A JP2002568424A JP4024681B2 JP 4024681 B2 JP4024681 B2 JP 4024681B2 JP 2002568424 A JP2002568424 A JP 2002568424A JP 2002568424 A JP2002568424 A JP 2002568424A JP 4024681 B2 JP4024681 B2 JP 4024681B2
- Authority
- JP
- Japan
- Prior art keywords
- die
- paddle
- package
- attachment
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000004033 plastic Substances 0.000 title description 6
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 238000000034 method Methods 0.000 description 21
- 239000000463 material Substances 0.000 description 17
- 239000003822 epoxy resin Substances 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 230000032798 delamination Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
図2は、従来技術による、ダウンボンドを備えたノンリード型パッケージを示す断面模式図
図3Aは、ダイをリードフレームの凹部形態部分に取付けると共に、ダウンボンドを、リードフレームのパドルの非凹部形態部分におけるダウンボンドアタッチメント部位に付着した、本発明のパッケージの実施形態を示す断面模式図、
図3Bは、図3Aに示した本発明の実施形態のダイパドルを示す平面模式図
図3Cは、図3BのC-C線に沿って切欠したダイパドルの断面模式図
図4Aは、ダイ付着領域と、ダウンボンドアタッチメント部位との間に溝を挿入した、本発明の別の実施形態であるパッケージを示す断面模式図
図4Bは、図4Aに示した本発明の実施形態のダイパドルを示す平面模式図
図4Cは、図4BのC-C線に沿って切欠したダイパドルの断面模式図
図5Aは、ダイパドル上部エッジの略周辺部に形成した溝を有する(この溝の形成により、応力を低下させると共に、ダイパドルと封入成形体材料との相互結合が得られる。)、本発明の別の実施形態であるダイパドルを示す平面模式図
図5Bは、図5AのB-B線に沿って切欠したダイパドルの断面模式図
図5Cは、図5AのC-C線に沿って切欠したダイパドルの断面模式図
図5Dは、図5A〜図5Cに示したような溝を、ダイ付着領域の周辺部付近に向かって内方に延在させた、本発明の別の実施形態であるダイパドルを示す断面模式図
図5Eは、図5DのE-E線に沿って切欠したダイパドルの断面模式図,および
図5Fは、図5DのF-F線に沿って切欠したダイパドルの断面模式図である。
図6Bは、図6AのB-B線に沿って切欠したダイパドルの断面模式図
図7Aは、ダウンボンド部位付近において別々の構成の分離溝を有する、本発明の別の実施形態であるダイパドルを示す平面模式図
図7Bは、図7AのB-B線に沿って切欠したダイパドルの断面模式図
図7Cは、図7AのC-C線に沿って切欠したダイパドルの断面模式図
図8は、図4Aに示すようにダイアタッチメント領域とダウンボンドアタッチメント部位との間のダイパドルエッジに対し略平行に走行する溝を有し、さらに、リード上面において凹部を有する、本発明の別の実施形態であるパッケージを示す平面模式図
図9は、図3Aに示すようにパドル上において凹部形態ダイ付着領域を有し、さらに、リードフレームのリード部分上面において溝を有する、本発明の別の実施形態であるパッケージを示す断面模式図
図10は、ダイアタッチメント領域と、ダウンボンドアタッチメント部位との間において、ダイパドルエッジに対し略平行に走行するダイパドル通過スロットを有する、本発明の別の実施形態であるパッケージを示す断面模式図
図11は、本発明の別の実施形態である、積重ね型パッケージを示す断面模式図、および
図12は、本発明の別の実施形態である、積重ね型パッケージを示す断面模式図である。
他の実施形態は、請求の範囲に記載されている。
Claims (4)
- ダイ付着パドルとリードとを備える、表面実装半導体チップパッケージ用のリードフレームであって、
前記ダイ付着パドルは、ダウンボンドアタッチメント部位を、前記パドルの上面であって前記パドルの周辺縁部付近において有すると共に、ダイ付着中央領域を前記パドル上面において有し、かつ、前記パドル上面の一部は、凹部形態であり、
前記パドル上面の凹部形態部分は、前記ダイ付着パドルの前記周辺縁部付近から前記ダイ付着領域に向かって内方に延在する複数の凹部を含み、
前記縁部付近から延在する前記凹部は、前記表面の非凹部形態部分と交互に配置され、前記非凹部形態部分の各々は、その上面において、1またはそれ以上の前記ダウンボンドアタッチメント部位を備え、
前記表面の非凹部形態部分は、前記パドルの基礎縁部を越えて外方に延在し、これにより、片持ちばり部分を形成しており、
前記ダウンボンドアタッチメント部位は、片持ちばり部分上に存在することを特徴とするリードフレーム。 - 請求項1記載のリードフレームを備えることを特徴とするリードフレーム表面実装パッケージ。
- 請求項 1 に記載のリードフレームの前記ダイ付着中央領域上に付着した第1ダイと、前記第1ダイを覆うように積重ねた第2ダイとを備えることを特徴とする、ノンリード型成形パッケージ。
- 前記第1ダイと、前記第2ダイとの間に挿入したスペーサーを有する請求項 3 記載のパッケージ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US27223901P | 2001-02-27 | 2001-02-27 | |
US10/081,490 US6661083B2 (en) | 2001-02-27 | 2002-02-22 | Plastic semiconductor package |
PCT/US2002/005695 WO2002069400A1 (en) | 2001-02-27 | 2002-02-25 | Plastic semiconductor package |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2004522297A JP2004522297A (ja) | 2004-07-22 |
JP2004522297A5 JP2004522297A5 (ja) | 2005-12-22 |
JP4024681B2 true JP4024681B2 (ja) | 2007-12-19 |
Family
ID=26765631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002568424A Expired - Lifetime JP4024681B2 (ja) | 2001-02-27 | 2002-02-25 | プラスチック半導体パッケージ |
Country Status (6)
Country | Link |
---|---|
US (1) | US6661083B2 (ja) |
EP (1) | EP1378007A4 (ja) |
JP (1) | JP4024681B2 (ja) |
KR (1) | KR20040030514A (ja) |
TW (1) | TW550716B (ja) |
WO (1) | WO2002069400A1 (ja) |
Families Citing this family (163)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6639308B1 (en) | 1999-12-16 | 2003-10-28 | Amkor Technology, Inc. | Near chip size semiconductor package |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP5183583B2 (ja) * | 2000-12-28 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR100369393B1 (ko) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
US6838751B2 (en) * | 2002-03-06 | 2005-01-04 | Freescale Semiconductor Inc. | Multi-row leadframe |
US6818973B1 (en) * | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
US6667543B1 (en) * | 2002-10-29 | 2003-12-23 | Motorola, Inc. | Optical sensor package |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
SG157957A1 (en) * | 2003-01-29 | 2010-01-29 | Interplex Qlp Inc | Package for integrated circuit die |
US7217599B2 (en) * | 2003-06-12 | 2007-05-15 | St Assembly Test Services Ltd. | Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor |
TWI257693B (en) * | 2003-08-25 | 2006-07-01 | Advanced Semiconductor Eng | Leadless package |
WO2005055320A1 (en) * | 2003-12-03 | 2005-06-16 | Koninklijke Philips Electronics N.V. | Integrated circuit package and leadframe |
US7122406B1 (en) * | 2004-01-02 | 2006-10-17 | Gem Services, Inc. | Semiconductor device package diepad having features formed by electroplating |
US6894382B1 (en) * | 2004-01-08 | 2005-05-17 | International Business Machines Corporation | Optimized electronic package |
US7009286B1 (en) * | 2004-01-15 | 2006-03-07 | Asat Ltd. | Thin leadless plastic chip carrier |
US20050242425A1 (en) * | 2004-04-30 | 2005-11-03 | Leal George R | Semiconductor device with a protected active die region and method therefor |
US8536688B2 (en) * | 2004-05-25 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit leadframe and fabrication method therefor |
US7091581B1 (en) * | 2004-06-14 | 2006-08-15 | Asat Limited | Integrated circuit package and process for fabricating the same |
JP4722415B2 (ja) * | 2004-06-14 | 2011-07-13 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US7411289B1 (en) | 2004-06-14 | 2008-08-12 | Asat Ltd. | Integrated circuit package with partially exposed contact pads and process for fabricating the same |
US20060006510A1 (en) * | 2004-07-06 | 2006-01-12 | Koduri Sreenivasan K | Plastic encapsulated semiconductor device with reliable down bonds |
CN100424864C (zh) * | 2004-07-16 | 2008-10-08 | 矽品精密工业股份有限公司 | 提高封装可靠性的导线架及其封装结构 |
CN100349288C (zh) * | 2004-09-22 | 2007-11-14 | 日月光半导体制造股份有限公司 | 无外引脚封装结构 |
US7119448B1 (en) * | 2004-10-18 | 2006-10-10 | National Semiconductor Corporation | Main power inductance based on bond wires for a switching power converter |
US7358617B2 (en) * | 2004-11-29 | 2008-04-15 | Texas Instruments Incorporated | Bond pad for ball grid array package |
US20060131708A1 (en) * | 2004-12-16 | 2006-06-22 | Ng Kee Y | Packaged electronic devices, and method for making same |
US7554179B2 (en) * | 2005-02-08 | 2009-06-30 | Stats Chippac Ltd. | Multi-leadframe semiconductor package and method of manufacture |
US20060181861A1 (en) * | 2005-02-17 | 2006-08-17 | Walker Harold Y Jr | Etched leadframe for reducing metal gaps |
JP2006294998A (ja) * | 2005-04-13 | 2006-10-26 | Rohm Co Ltd | 半導体装置及びリードフレーム |
US7994619B2 (en) * | 2005-11-01 | 2011-08-09 | Stats Chippac Ltd. | Bridge stack integrated circuit package system |
US8399968B2 (en) * | 2005-11-18 | 2013-03-19 | Stats Chippac Ltd. | Non-leaded integrated circuit package system |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7768083B2 (en) | 2006-01-20 | 2010-08-03 | Allegro Microsystems, Inc. | Arrangements for an integrated sensor |
US8698294B2 (en) * | 2006-01-24 | 2014-04-15 | Stats Chippac Ltd. | Integrated circuit package system including wide flange leadframe |
US8003443B2 (en) * | 2006-03-10 | 2011-08-23 | Stats Chippac Ltd. | Non-leaded integrated circuit package system with multiple ground sites |
JP4705881B2 (ja) * | 2006-05-09 | 2011-06-22 | パナソニック株式会社 | リードフレーム及びそれを用いた半導体装置 |
TW200744183A (en) * | 2006-05-16 | 2007-12-01 | Chipmos Technologies Inc | Integrated circuit package and multi-layer leadframe utilized |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US8062934B2 (en) * | 2006-06-22 | 2011-11-22 | Stats Chippac Ltd. | Integrated circuit package system with ground bonds |
US20080029855A1 (en) * | 2006-08-04 | 2008-02-07 | Yi-Ling Chang | Lead Frame and Fabrication Method thereof |
US8093693B2 (en) | 2006-09-15 | 2012-01-10 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US8067271B2 (en) * | 2006-09-15 | 2011-11-29 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US20080067639A1 (en) * | 2006-09-15 | 2008-03-20 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
JP2008085002A (ja) * | 2006-09-27 | 2008-04-10 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US8422243B2 (en) * | 2006-12-13 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit package system employing a support structure with a recess |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
JP5122172B2 (ja) * | 2007-03-30 | 2013-01-16 | ローム株式会社 | 半導体発光装置 |
TWI337387B (en) * | 2007-04-20 | 2011-02-11 | Chipmos Technologies Inc | Leadframe for leadless package, package structure and manufacturing method using the same |
TW200849521A (en) * | 2007-06-06 | 2008-12-16 | Advanced Semiconductor Eng | Leadframe with die pad and leads corresponding there to |
US8678271B2 (en) * | 2007-06-26 | 2014-03-25 | Globalfoundries Inc. | Method for preventing void formation in a solder joint |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
EP2183778A2 (en) | 2007-07-23 | 2010-05-12 | Nxp B.V. | A leadframe structure for electronic packages |
US7919848B2 (en) * | 2007-08-03 | 2011-04-05 | Stats Chippac Ltd. | Integrated circuit package system with multiple devices |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7595226B2 (en) * | 2007-08-29 | 2009-09-29 | Freescale Semiconductor, Inc. | Method of packaging an integrated circuit die |
US8067825B2 (en) * | 2007-09-28 | 2011-11-29 | Stats Chippac Ltd. | Integrated circuit package system with multiple die |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
US7829379B2 (en) * | 2007-10-17 | 2010-11-09 | Analog Devices, Inc. | Wafer level stacked die packaging |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7808089B2 (en) * | 2007-12-18 | 2010-10-05 | National Semiconductor Corporation | Leadframe having die attach pad with delamination and crack-arresting features |
US20090152683A1 (en) * | 2007-12-18 | 2009-06-18 | National Semiconductor Corporation | Rounded die configuration for stress minimization and enhanced thermo-mechanical reliability |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US7781899B2 (en) * | 2008-02-27 | 2010-08-24 | Infineon Technologies Ag | Leadframe having mold lock vent |
TWI364820B (en) * | 2008-03-07 | 2012-05-21 | Chipmos Technoligies Inc | Chip structure |
US8120152B2 (en) | 2008-03-14 | 2012-02-21 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof |
US7834431B2 (en) * | 2008-04-08 | 2010-11-16 | Freescale Semiconductor, Inc. | Leadframe for packaged electronic device with enhanced mold locking capability |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
JP2009302209A (ja) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法 |
KR101438826B1 (ko) * | 2008-06-23 | 2014-09-05 | 엘지이노텍 주식회사 | 발광장치 |
US8455988B2 (en) * | 2008-07-07 | 2013-06-04 | Stats Chippac Ltd. | Integrated circuit package system with bumped lead and nonbumped lead |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
JP2010087129A (ja) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8664038B2 (en) * | 2008-12-04 | 2014-03-04 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked paddle and method of manufacture thereof |
US8487420B1 (en) | 2008-12-08 | 2013-07-16 | Amkor Technology, Inc. | Package in package semiconductor device with film over wire |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8093707B2 (en) * | 2009-10-19 | 2012-01-10 | National Semiconductor Corporation | Leadframe packages having enhanced ground-bond reliability |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8492884B2 (en) | 2010-06-07 | 2013-07-23 | Linear Technology Corporation | Stacked interposer leadframes |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8404524B2 (en) | 2010-09-16 | 2013-03-26 | Stats Chippac Ltd. | Integrated circuit packaging system with paddle molding and method of manufacture thereof |
US8519518B2 (en) * | 2010-09-24 | 2013-08-27 | Stats Chippac Ltd. | Integrated circuit packaging system with lead encapsulation and method of manufacture thereof |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
TWI557183B (zh) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
DE102011016566A1 (de) * | 2011-03-07 | 2012-09-13 | Osram Opto Semiconductors Gmbh | Leiterrahmen für optoelektronische Bauelemente und Verfahren zur Herstellung optoelektronischer Bauelemente |
US9142426B2 (en) * | 2011-06-20 | 2015-09-22 | Cyntec Co., Ltd. | Stack frame for electrical connections and the method to fabricate thereof |
TWI443785B (zh) * | 2011-07-27 | 2014-07-01 | 矽品精密工業股份有限公司 | 半導體晶圓、晶片、具有該晶片之半導體封裝件及其製法 |
JP5935578B2 (ja) * | 2011-08-23 | 2016-06-15 | 大日本印刷株式会社 | 光半導体装置用リードフレーム、樹脂付き光半導体装置用リードフレーム、および光半導体装置 |
US8497165B2 (en) * | 2011-10-20 | 2013-07-30 | Intersil Americas Inc. | Systems and methods for lead frame locking design features |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
DE102012101970A1 (de) * | 2012-03-08 | 2013-09-12 | Osram Opto Semiconductors Gmbh | Leiterrahmeneinheit, Leiterrahmenverbund und elektronisches Bauelement mit Leiterrahmeneinheit |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
TWI480988B (zh) * | 2012-06-12 | 2015-04-11 | 矽品精密工業股份有限公司 | 封裝基板板片結構、封裝基板、半導體封裝件及其製法 |
JP2014007363A (ja) * | 2012-06-27 | 2014-01-16 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
US20140118978A1 (en) * | 2012-10-25 | 2014-05-01 | Po-Chun Lin | Package substrate and chip package using the same |
JP2014099534A (ja) * | 2012-11-15 | 2014-05-29 | Dainippon Printing Co Ltd | リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法 |
CN103972195A (zh) * | 2013-01-28 | 2014-08-06 | 飞思卡尔半导体公司 | 半导体装置及其装配方法 |
KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
US9496214B2 (en) * | 2013-05-22 | 2016-11-15 | Toyota Motor Engineering & Manufacturing North American, Inc. | Power electronics devices having thermal stress reduction elements |
US20150001697A1 (en) * | 2013-06-28 | 2015-01-01 | Stmicroelectronics Sdn Bhd | Selective treatment of leadframe with anti-wetting agent |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
JP2015233114A (ja) * | 2014-05-13 | 2015-12-24 | 株式会社デンソー | 半導体装置 |
DE102014108916B4 (de) * | 2014-06-25 | 2019-12-05 | Heraeus Deutschland GmbH & Co. KG | Bandförmiges Substrat zur Herstellung von Chipträgern, elektronisches Modul mit einem solchen Chipträger, elektronische Einrichtung mit einem solchen Modul und Verfahren zur Herstellung eines Substrates |
EP3172452B1 (en) * | 2014-07-25 | 2021-09-01 | Teledyne Digital Imaging, Inc. | Bonding method with peripheral trench |
JP6493952B2 (ja) * | 2014-08-26 | 2019-04-03 | 大口マテリアル株式会社 | リードフレーム及びその製造方法 |
JP2016058612A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社デンソー | 半導体装置 |
US9728510B2 (en) | 2015-04-10 | 2017-08-08 | Analog Devices, Inc. | Cavity package with composite substrate |
US10083888B2 (en) * | 2015-11-19 | 2018-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
JP6842236B2 (ja) * | 2015-12-28 | 2021-03-17 | ローム株式会社 | 磁気センサモジュール |
DE102016105781A1 (de) * | 2016-03-30 | 2017-10-19 | Infineon Technologies Ag | Ein Leadframe, eine Elektronikkomponente und ein Verfahren zum Ausbilden der Elektronikkomponente |
JP2018117049A (ja) * | 2017-01-18 | 2018-07-26 | 株式会社ディスコ | パッケージデバイスの製造方法 |
JP6757274B2 (ja) | 2017-02-17 | 2020-09-16 | 新光電気工業株式会社 | リードフレーム及びその製造方法 |
US11430722B2 (en) * | 2017-04-12 | 2022-08-30 | Texas Instruments Incorporated | Integration of a passive component in a cavity of an integrated circuit package |
US10622274B2 (en) | 2017-10-06 | 2020-04-14 | Industrial Technology Research Institute | Chip package |
US10607925B2 (en) * | 2017-10-06 | 2020-03-31 | Allegro Microsystems, Llc | Integrated circuit package having a raised lead edge |
JP6652117B2 (ja) | 2017-11-29 | 2020-02-19 | 日亜化学工業株式会社 | 樹脂パッケージおよび発光装置 |
US20190221502A1 (en) * | 2018-01-17 | 2019-07-18 | Microchip Technology Incorporated | Down Bond in Semiconductor Devices |
US10935612B2 (en) | 2018-08-20 | 2021-03-02 | Allegro Microsystems, Llc | Current sensor having multiple sensitivity ranges |
US11302611B2 (en) * | 2018-11-28 | 2022-04-12 | Texas Instruments Incorporated | Semiconductor package with top circuit and an IC with a gap over the IC |
US10770377B2 (en) * | 2018-12-31 | 2020-09-08 | Texas Instruments Incorporated | Leadframe die pad with partially-etched groove between through-hole slots |
TWI728318B (zh) | 2019-02-27 | 2021-05-21 | 力成科技股份有限公司 | 系統級封裝結構 |
JP2019161238A (ja) * | 2019-06-17 | 2019-09-19 | マクセルホールディングス株式会社 | 半導体装置用基板およびその製造方法、半導体装置 |
US11133241B2 (en) * | 2019-06-28 | 2021-09-28 | Stmicroelectronics, Inc. | Semiconductor package with a cavity in a die pad for reducing voids in the solder |
JP7051921B2 (ja) * | 2020-03-13 | 2022-04-11 | ローム株式会社 | 半導体装置 |
JP7499114B2 (ja) | 2020-08-21 | 2024-06-13 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US11567108B2 (en) | 2021-03-31 | 2023-01-31 | Allegro Microsystems, Llc | Multi-gain channels for multi-range sensor |
CN117832096A (zh) * | 2022-09-29 | 2024-04-05 | 恩智浦美国有限公司 | 具有树脂渗出控制结构的半导体装置及其方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5479563A (en) * | 1977-12-07 | 1979-06-25 | Kyushu Nippon Electric | Lead frame for semiconductor |
JPH02130864A (ja) * | 1988-11-10 | 1990-05-18 | Seiko Epson Corp | リードフレームのダイパッド構造 |
JP2849100B2 (ja) * | 1988-12-23 | 1999-01-20 | 旭化成工業株式会社 | 磁電変換素子およびその製造方法 |
JPH0536882A (ja) | 1991-07-31 | 1993-02-12 | Mitsubishi Electric Corp | 半導体用フレーム |
KR100552353B1 (ko) | 1992-03-27 | 2006-06-20 | 가부시키가이샤 히타치초엘에스아이시스템즈 | 리이드프레임및그것을사용한반도체집적회로장치와그제조방법 |
JPH0621317A (ja) | 1992-07-02 | 1994-01-28 | Seiko Epson Corp | 半導体パッケージの製造方法 |
US5278446A (en) * | 1992-07-06 | 1994-01-11 | Motorola, Inc. | Reduced stress plastic package |
US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
US5594234A (en) | 1994-11-14 | 1997-01-14 | Texas Instruments Incorporated | Downset exposed die mount pad leadframe and package |
US5894108A (en) | 1997-02-11 | 1999-04-13 | National Semiconductor Corporation | Plastic package with exposed die |
US5818103A (en) * | 1997-03-28 | 1998-10-06 | Nec Corporation | Semiconductor device mounted on a grooved head frame |
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
JP3062691B1 (ja) * | 1999-02-26 | 2000-07-12 | 株式会社三井ハイテック | 半導体装置 |
KR100335480B1 (ko) * | 1999-08-24 | 2002-05-04 | 김덕중 | 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지 |
JP2001127246A (ja) * | 1999-10-29 | 2001-05-11 | Fujitsu Ltd | 半導体装置 |
US6198171B1 (en) * | 1999-12-30 | 2001-03-06 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced quad flat non-lead package of semiconductor |
JP3420153B2 (ja) * | 2000-01-24 | 2003-06-23 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2002076228A (ja) * | 2000-09-04 | 2002-03-15 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
-
2002
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- 2002-02-25 KR KR10-2003-7011170A patent/KR20040030514A/ko not_active Application Discontinuation
- 2002-02-25 EP EP02713685A patent/EP1378007A4/en not_active Ceased
- 2002-02-25 WO PCT/US2002/005695 patent/WO2002069400A1/en active Application Filing
- 2002-02-25 JP JP2002568424A patent/JP4024681B2/ja not_active Expired - Lifetime
- 2002-02-27 TW TW091103594A patent/TW550716B/zh not_active IP Right Cessation
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EP1378007A4 (en) | 2010-03-17 |
US20020163015A1 (en) | 2002-11-07 |
US6661083B2 (en) | 2003-12-09 |
WO2002069400A1 (en) | 2002-09-06 |
JP2004522297A (ja) | 2004-07-22 |
KR20040030514A (ko) | 2004-04-09 |
EP1378007A1 (en) | 2004-01-07 |
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