JPH0621317A - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法

Info

Publication number
JPH0621317A
JPH0621317A JP4175367A JP17536792A JPH0621317A JP H0621317 A JPH0621317 A JP H0621317A JP 4175367 A JP4175367 A JP 4175367A JP 17536792 A JP17536792 A JP 17536792A JP H0621317 A JPH0621317 A JP H0621317A
Authority
JP
Japan
Prior art keywords
chip
die pad
groove
integrated circuit
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4175367A
Other languages
English (en)
Inventor
Satoru Matsuya
悟 松舎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4175367A priority Critical patent/JPH0621317A/ja
Publication of JPH0621317A publication Critical patent/JPH0621317A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【構成】ダイパッド１のＩＣ搭載側のＩＣチップ内周部
に溝２，外周部に溝３を設け、ダイパッドにＩＣチップ
を接着させるＤＢ剤のダイパッド外部へのはみ出し時の
ストッパーとすると同時に、内周の溝には貫通穴を設け
る。 【効果】ＤＢ剤のはみ出しを防止する。またモールド封
止時のダイパッドとモールド剤の機械的密着強度を向上
させることによって、ＩＲリフローに代表される様なパ
ッケージ実装時の全体加熱方式によるパッケージクラッ
クの発生を防ぐ。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体の組立工程にお
ける半導体パッケージの製造方法に関する。
【０００２】
【従来の技術】従来の技術としては、図２に示す半導体
パッケージの製造方法が知られていた。これは主に図２
（ａ），図２（ｂ）及び図２（ｃ）に代表される３タイ
プに分けられる。図２（ａ）はダイパッド１だけの何も
工夫のないタイプであり、図２（ｂ）は、ダイパッド１
の裏面にディンプル９と呼ばれる半球状の窪みを多数設
ける構造のものである。また、図２（ｃ）はダイパッド
１にスリット１０と呼ばれる貫通穴を開ける構造のもの
であった。
【０００３】
【発明が解決しようとする課題】しかし、前述の従来の
技術では、ダイパッドにＩＣチップを接着させるＤＢ剤
のダイパッド外部へのはみ出しや、ＩＲリフローに代表
される様な表面実装技術によって、半導体パッケージ全
体が加熱された場合にパッケージクラックの発生及びＡ
ｕワイヤの切断、しいては耐熱性の劣化を引き起こす危
険性があった。
【０００４】そこで本発明の目的とするところは、ダイ
パッドのＩＣ搭載側のＩＣチップの内外周に溝を設ける
ことによってＤＢ剤のはみ出しに対するストッパーとす
ると共に、内周部の溝には貫通穴を設けることによっ
て、ダイパッドとモールド樹脂の機械的な密着強度を高
めることによって、パッケージ実装時の全体加熱方式に
よるパッケージクラックの発生を防ぐものである。
【０００５】
【課題を解決するための手段】本発明の半導体パッケー
ジの製造方法は、半導体の組立工程の中で、金属から成
るダイパッドにＩＣチップを接着させるものにおいて、
ダイパッドのＩＣチップ搭載側のＩＣチップの内外周部
に溝を付け、更に内周部には貫通穴を設けることを特徴
とする。
【０００６】
【作用】本発明の上記構造によれば、ＤＢ剤のはみ出し
と表面実装技術によるパッケージ全体加熱時に発生する
パッケージクラック等の不具合を回避することが出来
る。
【０００７】
【実施例】以下に本発明の実施例を図面に基づいて説明
する。図１（ａ）は、本発明の半導体パッケージの製造
方法の平面図であり、金属から成るダイパッド１のＩＣ
搭載側のＩＣチップの内周２及び外周３に溝を設けた状
態を示している。この際の溝の深さは、リードフレーム
設計上許すことの出来る限り深い方が望ましい。また内
部の溝の広さとしては、ＩＣチップの大きさよりＸ，Ｙ
方向各1.5mm〜2.0mm程度小さいものが望ましいと思われ
る。外周の溝の位置と大きさはＩＣチップの大きさから
1.0mm程度広い所から幅0.5mm程度のものが望ましい。更
に内周の溝２にはダイパッドを貫通する穴４を設ける。
この穴の数は、モールド樹脂の注入圧力及び後述するＤ
Ｂ剤のはみ出しに対するストッパーとしての役目を考え
て、1〜3個程度開けるのが望ましい。また、図１（ｂ）
は本発明の半導体パッケージの製造方法の縦断面図であ
り、組立工程との関係を示している。前述のダイパッド
１上には、ＩＣチップ５がＤＢ剤６を用いて接着される
が、この際にはみ出したＤＢ剤はＩＣ内周及び外周部の
溝に流れ出し、信頼性及び製造装置の関係上問題となる
ＤＢ剤のはみ出し過多を防ぐことが出来る。このＩＣチ
ップを接着させる際には、ＩＣチップ能動面へのキズ防
止及び前述のＩＣチップ内周部の溝を考慮して、ＩＣチ
ップ表面に力が加わることを避ける必要があり、角錘型
のコレットを使用することが望ましい。その後ＩＣチッ
プ上に形成されたＡｌ電極とリードフレームをＡｕワイ
ヤ７により接着し、最後にモールド剤８を用いて封止す
るものである。最終製品形態で考えた場合、図中２に示
すＩＣチップの内周の溝には、リードフレームを介して
モールド剤が注入される為に、リードフレームとモール
ド剤の機械的な密着性が向上することになる。ＩＲリフ
ローに代表される様な表面実装方法では、リードフレー
ムとモールド剤の密着性が耐パッケージクラック性を左
右する為に、前述の機械的密着強度の向上の意味は大き
いと言える。
【０００８】
【発明の効果】以上述べたように本発明によれば、金属
から成るダイパッドにＩＣチップを接着させるものにお
いて、ダイパッドのＩＣ搭載側のＩＣチップの内外周に
溝を付け、更に内周部には貫通穴を設けることによっ
て、ＤＢ剤のはみ出しと、表面実装技術によるパッケー
ジ全体加熱時に発生するパッケージクラックを回避する
ことが出来る。
【図面の簡単な説明】
【図１】本発明の半導体パッケージの製造方法の平面図
および縦断面図である。
【図２】従来の半導体パッケージの製造方法の平面図で
ある。
【符号の説明】
１…ダイパッド ２…内周の溝 ３…外周の溝 ４…貫通穴 ５…ＩＣチップ ６…ＤＢ剤 ７…Ａｕワイヤ ８…モールド剤 ９…ディンプル 10…スリット

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】半導体の組立工程の中で、金属から成るダ
    イパッドにＩＣチップを接着させるものにおいて、ダイ
    パッドのＩＣ搭載側のＩＣチップの内外周に溝を付け、
    更に内周部には貫通穴を設けることを特徴とする半導体
    パッケージの製造方法。
JP4175367A 1992-07-02 1992-07-02 半導体パッケージの製造方法 Pending JPH0621317A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4175367A JPH0621317A (ja) 1992-07-02 1992-07-02 半導体パッケージの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4175367A JPH0621317A (ja) 1992-07-02 1992-07-02 半導体パッケージの製造方法

Publications (1)

Publication Number Publication Date
JPH0621317A true JPH0621317A (ja) 1994-01-28

Family

ID=15994855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4175367A Pending JPH0621317A (ja) 1992-07-02 1992-07-02 半導体パッケージの製造方法

Country Status (1)

Country Link
JP (1) JPH0621317A (ja)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655782A3 (en) * 1993-11-29 1995-10-18 Toshiba Kk Semiconductor device sealed with a resin and method of manufacturing it.
WO1997012387A2 (de) * 1995-09-29 1997-04-03 Siemens Aktiengesellschaft Leiterrahmen für integrierte schaltungen
DE19639181A1 (de) * 1996-09-24 1998-04-02 Siemens Ag Zuleitungsrahmen für ein mikroelektronisches Bauelement
US6383014B1 (en) 1999-10-29 2002-05-07 Yazaki Corporation Wire holding structure of an electric wire protector
WO2002069400A1 (en) * 2001-02-27 2002-09-06 Chippac, Inc. Plastic semiconductor package
EP1302983A1 (en) * 2001-10-15 2003-04-16 Siliconix (Taiwan) Ltd. Leadframe having slots in a die pad
WO2004016368A1 (ja) * 2002-08-06 2004-02-26 Kabushiki Kaisha Kobe Seiko Sho リードフレーム加工用コイニングポンチ、そのコイニングポンチの製造方法、及びリードフレーム
EP1510825A1 (en) * 2002-05-31 2005-03-02 Matsushita Electric Works, Ltd. Sensor package
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
KR100526837B1 (ko) * 2000-04-27 2005-11-08 앰코 테크놀로지 코리아 주식회사 반도체패키지
US7560311B2 (en) 2002-04-16 2009-07-14 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US7705469B2 (en) * 2007-05-31 2010-04-27 Oki Semiconductor Co., Ltd. Lead frame, semiconductor device using same and manufacturing method thereof
US7719096B2 (en) * 2006-08-11 2010-05-18 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
US7812432B2 (en) * 2008-03-07 2010-10-12 Chipmos Technologies Inc. Chip package with a dam structure on a die pad
US8018072B1 (en) 2008-12-23 2011-09-13 Amkor Technology, Inc. Semiconductor package having a heat spreader with an exposed exterion surface and a top mold gate
DE102011016566A1 (de) * 2011-03-07 2012-09-13 Osram Opto Semiconductors Gmbh Leiterrahmen für optoelektronische Bauelemente und Verfahren zur Herstellung optoelektronischer Bauelemente

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655782A3 (en) * 1993-11-29 1995-10-18 Toshiba Kk Semiconductor device sealed with a resin and method of manufacturing it.
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