JP2014078768A - 異なるサイズを有する複数の半導体チップが積層された半導体素子とそれを備えたマルチチップパッケージ - Google Patents
異なるサイズを有する複数の半導体チップが積層された半導体素子とそれを備えたマルチチップパッケージ Download PDFInfo
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- JP2014078768A JP2014078768A JP2014021330A JP2014021330A JP2014078768A JP 2014078768 A JP2014078768 A JP 2014078768A JP 2014021330 A JP2014021330 A JP 2014021330A JP 2014021330 A JP2014021330 A JP 2014021330A JP 2014078768 A JP2014078768 A JP 2014078768A
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Abstract
【解決手段】本発明の半導体素子は、第1チップと、第1チップ上に積層され、第1チップと異なるサイズを有する少なくとも1つのチップと、を含み、第1チップは、中央に配された複数の第1パッドを備え、少なくとも1つのチップは、中央に配された複数の第2パッドを備え、第1チップと少なくとも1つのチップは、垂直に配された第1パッドを用いて電気的に連結され、第1パッドと第2パッドは、第1チップと少なくとも1つのチップに同じ配列順序で配される。
【選択図】 図1
Description
また、第1チップ及び少なくとも1つのチップのうち、少なくとも1つは、エッジ部に追加パッドを含む。
また、同じ座標に位置する第1パッド及び第2パッドは、同一信号を伝達することを特徴とする。
図1を参照すれば、本発明のマルチチップパッケージは、実装基板100、例えば、印刷回路基板の上部に積層されている複数の半導体チップ110,120,130を含む。複数の半導体チップ110,120,130は、異なるサイズを有し、異なる機能を行える。半導体チップ110,120及び130のそれぞれは、DRAM、SRAM、フラッシュメモリ、プロセッサのうち何れか一つでありうる。一部の実施形態で、半導体チップ110,120及び130は、サイズが減少する順序で積層されうる。しかし、このような整列に制限されるものではない。
半導体チップ110,120及び130は、パッド群112,122及び132が相互対向するように積層される。パッド群112,122及び132は、各半導体チップ110,120及び130の同じ領域(例えば、中心領域あるいはエッジ領域)に配列される。各半導体チップ110,120及び130の同じ領域にパッドグループ112,122及び132を配列することは、電気的な観点で本質的なものではないが、前記半導体パッケージの面積を縮少させうる。
半導体チップ110,120及び130を積層することによって、相互対向するパッド112a,122a及び132aは、連結部材、例えば、バンプ140によって電気的に連結される。複数の半導体チップ110,120及び130のうち一つの半導体チップが実装基板100と電気的に連結される。本実施形態では、実装基板100と半導体チップ110とがバンプ140によって連結される。
102は、実装基板100に電気的経路を提供できるスタッドを示す。スタッド102は、導電性ボール104と電気的に連結される。
すなわち、図10に示したように、パッド群112,122,132は、半導体チップ110,120,130の一側エッジにそれぞれ配列されてもよく、図11に示したように、半導体チップ110,120,130のエッジに沿って“L”字状に配列されてもよい。
図16Aを参照すれば、複数のスタッド102を備える実装基板100が提供される。実装基板100の選択されたスタッド102上にバンプ140−1を形成した後、パッド112の備える第1半導体チップ110を実装基板100上に積層する。第1半導体チップ110は、貫通型パッド112と第1バンプ140とがコンタクトされるように積層される。以後に、第1半導体チップ110の露出されたパッド112上に第2バンプ140−2が形成される。
図17Aを参照すれば、複数のスタッド102を有する実装基板100上に接着層145を形成した後、接着層145上に第1半導体チップ110が付着される。第1半導体チップ110で、パッド領域は、導電性材料が充填されずにホール状態に維持されている。また接着層145は、ホールhが位置する部分には存在しないように形成される。以後、ホールhの部位を除外した第1半導体チップ110上に再び接着層145を形成した後、第2半導体チップ120が第1半導体チップ110上に付着される。このとき第2半導体チップ120も同様に、パッド領域が導電性材料で充填されていないホール状態を維持しており、第2半導体チップ120のホールと第1チップ110のホールとが相互対応するように配置される。第2半導体チップ120の上部にホールh領域が露出されるように接着層145を再び形成した後、第2半導体チップ120上に第3半導体チップ130が付着される。第3半導体チップ130もパッド領域がホール状態に存在し、第2半導体チップ120のホールと第3半導体チップ130のホールとが対向するように配置される。
前述した実施形態で開示されたパッドは、2列または1列に整列されるが、本発明の実施形態は、これに限定されず、パッドは、多様な形態に配列される。
また、本発明の実施形態で、半導体チップが実装される基板についての例として印刷回路基板を説明したが、セラミック、リードフレーム、回路テープまたは回路フィルムのような実装部材が使われる。また、外部との電気的接続手段として導電ボールを使用したが、バンプなど、その他の接続手段を何れも使用しうる。
102 スタッド
104 導電性ボール
110,120,130 半導体チップ
112,122,132 パッド群
112a,122a,132a パッド
140 バンプ
145 接着剤
150 封止材
160 ワイヤ
Claims (17)
- 第1チップと、
前記第1チップ上に積層され、前記第1チップと異なるサイズを有する少なくとも1つのチップと、を含み、
前記第1チップは、中央に配された複数の第1パッドを備え、前記少なくとも1つのチップは、中央に配された複数の第2パッドを備え、前記第1チップと前記少なくとも1つのチップは、垂直に配された前記第1パッドを用いて電気的に連結され、
前記第1パッドと前記第2パッドは、前記第1チップと前記少なくとも1つのチップに同じ配列順序で配されたことを特徴とする半導体素子。 - 前記第1パッドは、貫通ビアコンタクトで形成されたことを特徴とする請求項1に記載の半導体素子。
- 前記少なくとも1つのチップは、複数のチップを含み、互いに異なるサイズを有することを特徴とする請求項1に記載の半導体素子。
- 前記第1チップと前記少なくとも1つのチップは、前記第1パッド上のバンプを通じて電気的に連結されたことを特徴とする請求項1に記載の半導体素子。
- 前記第1チップ及び前記少なくとも1つのチップのうち、少なくとも1つは、エッジ部に追加パッドを含むことを特徴とする請求項1に記載の半導体素子。
- 前記第1チップと前記少なくとも1つのチップは、中央に基準領域を備え、前記第1パッド及び第2パッドは、対応する基準領域に対して同じ座標に位置することを特徴とする請求項1に記載の半導体素子。
- 前記同じ座標に位置する前記第1パッド及び第2パッドは、同一信号を伝達することを特徴とする請求項6に記載の半導体素子。
- 前記第1チップと前記少なくとも1つのチップは、互いに異なる機能を有することを特徴とする請求項1に記載の半導体素子。
- 前記第1チップは、ロジックチップまたはCPUチップであり、前記少なくとも1つのチップは、メモリチップであることを特徴とする請求項8に記載の半導体素子。
- 基板と、
前記基板上に積層された第1チップと、
前記第1チップ上に積層され、前記第1チップと異なるサイズを有する少なくとも1つのチップと、
前記第1チップと前記少なくとも1つのチップとを密封する密封材と、
前記基板の下部面に配された導電性ボールと、を含み、
前記第1チップは、中央に配された複数の第1パッドを備え、前記少なくとも1つのチップは、中央に配置された複数の第2パッドを備え、前記第1チップと前記少なくとも1つのチップは、垂直に配された前記第1パッドを用いて電気的に連結され、
前記第1パッドと前記第2パッドは、前記第1チップと前記少なくとも1つのチップに同じ配列順序で配されたことを特徴とするマルチチップパッケージ。 - 前記第1パッドは、貫通ビアコンタクトで形成されたことを特徴とする請求項10に記載のマルチチップパッケージ。
- 前記基板は、前記第1チップ及び前記少なくとも1つの半導体チップに電気的に連結されたことを特徴とする請求項10に記載のマルチチップパッケージ。
- 前記第1パッドは、貫通ビアコンタクトで形成され、前記少なくとも1つのチップは、前記第1パッドを通じて前記基板に電気的に連結されたことを特徴とする請求項10に記載のマルチチップパッケージ。
- 前記少なくとも1つのチップは、複数のチップを含み、互いに異なるサイズを有することを特徴とする請求項10に記載のマルチチップパッケージ。
- 前記第1チップと前記少なくとも1つのチップは、中央に基準領域を備え、前記第1パッド及び第2パッドは、対応する基準領域に対して同じ座標に位置することを特徴とする請求項10に記載のマルチチップパッケージ。
- 前記同じ座標に位置する前記第1パッド及び第2パッドは、同一信号を伝達することを特徴とする請求項15に記載のマルチチップパッケージ。
- 前記第1チップは、ロジックチップまたはCPUチップであり、前記少なくとも1つのチップは、メモリチップであることを特徴とする請求項10に記載のマルチチップパッケージ。
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US9397034B2 (en) | 2016-07-19 |
US8395259B2 (en) | 2013-03-12 |
US20130147044A1 (en) | 2013-06-13 |
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US9761563B2 (en) | 2017-09-12 |
US20160300819A1 (en) | 2016-10-13 |
JP6336766B2 (ja) | 2018-06-06 |
US20080036082A1 (en) | 2008-02-14 |
JP5475222B2 (ja) | 2014-04-16 |
KR20080013305A (ko) | 2008-02-13 |
KR100809696B1 (ko) | 2008-03-06 |
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