JP2011187853A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】半導体装置は、第1導電型のドリフト拡散領域10と、第2導電型のボディ拡散領域2と、第1導電型のソース拡散領域6と、ドリフト拡散領域10の上部に形成されたトレンチ内に埋め込まれ、ボディ拡散領域2とは離間した位置に形成された絶縁膜14と、ドリフト拡散領域10の上部に形成され、絶縁膜14から見てソース拡散領域6と逆の方向に隣接する第1導電型のドレイン拡散領域7と、ボディ拡散領域2上からドリフト拡散領域10上を越えて絶縁膜14上にまで形成されたゲート電極5とを備えている。また、ドリフト拡散領域10は、基板内部領域11と、基板内部領域11よりも高濃度の第1導電型不純物を含む表面領域12とを有している。
【選択図】図1
Description
図1は、本発明の実施形態に係るLDMOSトランジスタ(半導体装置)の断面図である。同図に示すように、本実施形態に係るLDMOSトランジスタは、p型(第2導電型)の半導体基板1と、半導体基板1の上部に形成されたn型(第1導電型)のドリフト拡散領域10と、ドリフト拡散領域10の上部(すなわち半導体基板1の上部)に形成されたp型のボディ拡散領域2と、ボディ拡散領域2の上部に形成され、互いに接するp型のバックゲート拡散領域8及びn型のソース拡散領域6と、ドリフト拡散領域10の上部に形成されたn型のドレイン拡散領域7と、ソース拡散領域6とドレイン拡散領域7との間に形成され、ソース拡散領域6及びボディ拡散領域2と離間して配置された酸化膜(絶縁膜)14とを備えている。酸化膜14は、ドリフト拡散領域10の上部に形成されたトレンチ13内に埋め込まれている。
図6は、本発明の実施形態に係るLDMOSトランジスタの第1の変形例を示す断面図である。本変形例に係るLDMOSトランジスタは、酸化膜14の直下に位置する領域に、基板内部領域11よりも高濃度のn型不純物を含むドリフト拡散部15が形成されている点が、図1に示すLDMOSトランジスタと異なっている。
図10は、本発明の実施形態に係るLDMOSトランジスタの第2の変形例を示す断面図である。本変形例に係るLDMOSトランジスタは、トレンチ13のコーナー部が丸められていることを除いては、図1に示すLDMOSトランジスタと同様の構成を有している。
図14は、本発明の実施形態に係るLDMOSトランジスタの第3の変形例を示す断面図である。同図に示すように、本変形例に係るLDMOSトランジスタでは、半導体基板1の上部に形成されたn型のドリフト拡散領域210がソース拡散領域6の下方には形成されておらず、p型のボディ拡散領域2とも離れた位置に形成されている点が図1に示すLDMOSトランジスタと異なっている。
2 ボディ拡散領域
4 ゲート絶縁膜
5 ゲート電極
6 ソース拡散領域
7、207 ドレイン拡散領域
8 バックゲート拡散領域
10、210 ドリフト拡散領域
11、211 基板内部領域
12、212 表面領域
13 トレンチ
14 酸化膜
15 ドリフト拡散部
16 ソース電極
17 ドレイン電極
19 酸化膜
20 窒化膜
21 レジスト
23 層間絶縁膜
24 酸化膜
25 空乏層
26 キャリアの経路
50 レジスト
Claims (10)
- 半導体基板の上部に形成された第1導電型のドリフト拡散領域と、
前記半導体基板の上部に形成された第2導電型のボディ拡散領域と、
前記ボディ拡散領域の上部に形成された第1導電型のソース拡散領域と、
前記ドリフト拡散領域の上部に形成されたトレンチ内に埋め込まれ、前記ボディ拡散領域とは離間した位置に形成された絶縁膜と、
前記ドリフト拡散領域の上部に形成され、前記絶縁膜から見て前記ソース拡散領域と逆の方向に隣接する第1導電型のドレイン拡散領域と、
ゲート絶縁膜を間に挟んだ状態で、前記ボディ拡散領域上から前記ドリフト拡散領域上を越えて前記絶縁膜上にまで形成されたゲート電極とを備え、
前記ドリフト拡散領域は、基板内部領域と、前記基板内部領域上で且つ前記ゲート電極の下に形成され、前記基板内部領域よりも高濃度の第1導電型不純物を含む表面領域とを有している半導体装置。 - 請求項1に記載の半導体装置において、
前記ドリフト拡散領域のうち前記トレンチの底部に位置する部分は、同じ深さに位置する前記基板内部領域よりも高濃度の第1導電型不純物を含んでいる半導体装置。 - 請求項1または2に記載の半導体装置において、
前記トレンチの上端部及び前記トレンチ底部のコーナー部は丸められている半導体装置。 - 請求項1〜3のうちいずれか1つに記載の半導体装置において、
前記ボディ拡散領域は前記ドリフト拡散領域の上部に形成されており、
前記ボディ拡散領域と前記表面領域とは接している半導体装置。 - 請求項1〜3のうちいずれか1つに記載の半導体装置において、
前記ボディ拡散領域と前記ドリフト拡散領域とは互いに離間して形成されており、
前記半導体基板のうち前記ボディ拡散領域と前記ドリフト拡散領域との間に位置する部分は第2導電型を示す半導体装置。 - 請求項1〜5のうちいずれか1つに記載の半導体装置において、
前記ドリフト拡散領域に含まれる第1導電型不純物の濃度は、前記ソース拡散領域及び前記ドレイン拡散領域に含まれる第1導電型不純物の濃度よりも低い半導体装置。 - 第1のイオン注入によって第1導電型の不純物イオンを半導体基板に注入し、第1導電型の基板内部領域を形成するとともに、前記第1のイオン注入よりも低い注入エネルギー、大きいドーズ量の第2のイオン注入によって第1導電型の不純物イオンを前記半導体基板に注入し、前記基板内部領域よりも浅い位置に第1導電型の表面領域を形成することで、前記基板内部領域及び前記表面領域を含むドリフト拡散領域を形成する工程(a)と、
前記ドリフト拡散領域の所定の領域にトレンチを形成する工程(b)と、
前記トレンチを埋める絶縁膜を形成する工程(c)と、
前記半導体基板との間にゲート絶縁膜を挟んで、前記半導体基板上及び前記絶縁膜上にゲート電極を形成する工程(d)と、
前記半導体基板の上部であって、前記ゲート電極のゲート長方向の端部下に位置する領域に、前記トレンチとは離間した第2導電型のボディ拡散領域を形成する工程(e)と、
前記ボディ拡散領域の上部に第1導電型のソース拡散領域を形成するとともに、前記ドリフト拡散領域の上部であって、前記絶縁膜から見て前記ソース拡散領域と逆の方向に隣接する領域に第1導電型のドレイン拡散領域を形成する工程(f)とを備えている半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記工程(b)は前記工程(a)の後に行われ、
前記工程(b)では前記所定の領域に開口が形成された第1のマスクを用いて前記ドリフト拡散領域をエッチングすることで前記トレンチを形成し、
前記工程(b)の後、前記工程(c)の前に、前記第1のマスクを用いて前記ドリフト拡散領域のうち前記トレンチの底部に位置する領域に第1導電型の不純物イオンを注入し、前記基板内部領域よりも高濃度の第1導電型の不純物を含むドリフト拡散部を形成する工程をさらに備えている半導体装置の製造方法。 - 請求項7または8に記載の半導体装置の製造方法において、
前記工程(b)は、
前記ドリフト拡散領域の前記所定の領域を選択的に酸化することにより、前記所定の領域上に酸化膜を形成する工程(b1)と、
前記酸化膜を除去することで、前記所定の領域に、底部のコーナー部が丸められた前記トレンチを形成する工程(b1)とを含んでいる半導体装置の製造方法。 - 請求項7〜9のうちいずれか1つに記載の半導体装置の製造方法において、
前記工程(a)では、前記半導体基板の一部を覆う第2のマスクを用いたイオン注入によって前記基板内部領域及び前記表面領域を形成し、
前記工程(e)では、前記ドリフト拡散領域から離れた位置に前記ボディ拡散領域を形成する半導体装置の製造方法。
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