JP2010258226A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2010258226A JP2010258226A JP2009106767A JP2009106767A JP2010258226A JP 2010258226 A JP2010258226 A JP 2010258226A JP 2009106767 A JP2009106767 A JP 2009106767A JP 2009106767 A JP2009106767 A JP 2009106767A JP 2010258226 A JP2010258226 A JP 2010258226A
- Authority
- JP
- Japan
- Prior art keywords
- region
- groove
- trench
- semiconductor substrate
- wall portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 238000000034 method Methods 0.000 claims description 32
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000006731 degradation reaction Methods 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 description 58
- 230000000052 comparative effect Effects 0.000 description 55
- 238000010586 diagram Methods 0.000 description 24
- 102100027417 Cytochrome P450 1B1 Human genes 0.000 description 20
- 101000725164 Homo sapiens Cytochrome P450 1B1 Proteins 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 230000005684 electric field Effects 0.000 description 16
- 230000006866 deterioration Effects 0.000 description 13
- 238000012360 testing method Methods 0.000 description 12
- 238000010893 electron trap Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 239000000969 carrier Substances 0.000 description 6
- 238000004380 ashing Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000001154 acute effect Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】半導体基板SUBは、主表面を有し、かつその主表面に溝TRを有している。埋め込み絶縁膜BIは溝TR内を埋め込んでいる。溝TRは、互いに対向する一方壁面FSと他方壁面SSとを有している。ゲート電極層GEは少なくとも埋め込み絶縁膜BI上に位置している。溝TRは、一方壁面FSおよび他方壁面SSの少なくともいずれかの壁面の主表面と溝TRの底部BTとの間に位置する角部CP1A、CP2Aを有している。
【選択図】図2
Description
(実施の形態1)
まず実施の形態1における半導体装置の構成について図1および図2を用いて説明する。
図3を参照して、溝TRの一方壁部FSの上側部分UP1から底部BTまでの深さ方向(厚み方向)の寸法をS1とし、割合(%)をX2、Y2としたとき、角部CP1Aは溝TRの底部BTからS1×Y2だけ浅い位置(半導体基板SUBの主表面に近い位置)に位置している。また一方壁部FSと底部BTとの接合部(エッジ部)ED1は、半導体基板SUBの主表面からS1の深さで、かつ溝TRの上側部分UP1から横方向(半導体基板SUBの主表面に沿う方向)にS1×X2だけドレイン側(他方壁部SS側)に位置している。
なお図4〜図13においては図1に示したアナログ・デジタル混載チップにおけるスタックゲート型の不揮発性メモリNVMおよびCMOSトランジスタとともに、図2に示すLDMOSトランジスタ(以下、「SS−LDMOSトランジスタ」と称する)が示されている。
次に、本実施の形態の半導体装置の作用効果について図14に示す比較例と対比して説明する。
次に、実施の形態2の半導体装置の構成について図21を用いて説明する。
図3を参照して、溝TRの上側部分UP2から底部BTまでの深さ方向の寸法をS2とし、割合(%)をX1、Y1としたとき、他方壁部SSの角部CP1Bは溝TRの底部BTからS2×Y1だけ浅い位置(半導体基板SUBの主表面に近い位置)に位置している。また他方壁部SSと底部BTとの接合部(エッジ部)ED2は、半導体基板SUBの主表面からS2の深さで、かつ溝TRの上側部分UP2から横方向(半導体基板SUBの主表面に沿う方向)にS2×X1だけソース側(一方壁部FS側)に位置している。
次に、実施の形態3の半導体装置の構成について図27を用いて説明する。
上記の実施の形態1〜3においては、SS−LDMOSトランジスタがRESURF型の場合について説明したが、SS−LDMOSトランジスタは非RESURF型であってもよい。以下、その構成について図33を用いて説明する。
上記の実施の形態1〜4においては、角部を有する溝をLDMOSトランジスタに適用した場合について説明したが、角部を有する溝は、その溝の下側に位置する半導体基板内に電流を流す素子に適用することもできる。以下、その構成について図34を用いて説明する。
本発明者は、図2に示す実施の形態1における溝TRの一方壁部FSの階段形状について好ましい形状を検討した。その検討内容および検討結果を図35〜図37を用いて説明する。
本実施の形態においては、角部の平面レイアウトについて図42〜図44を用いて説明する。
上記の実施の形態1〜7においては、溝TRの一方壁部FSおよび他方壁部SSが断面視において階段形状となるように角部を形成した場合について説明したが、角部は溝TRの一方壁部FSおよび他方壁部SSの各々に断面視において傾斜部を形成するように設けられてもよい。以下、溝TRの一方壁部FSおよび他方壁部SSの各々に傾斜部を形成するような角部を有する構成について図45〜49を用いて説明する。
本発明者は、図45および図46の各々に示す構成について、デバイス・シミュレーションによってOLT試験のストレス状態を再現し、図14に示す比較例との素子内部状態の比較を行った。その比較検討の内容および検討結果を図50〜56を用いて説明する。
実施の形態1〜7においては溝TRの一方壁部FS、他方壁部SSの階段形状は段部が1段の場合について説明したが、図57に示すように2段以上の複数の段部を有していてもよい。複数の段部を有する場合には、一方壁部FSおよび他方壁部SSの各々には、凸状の角部CP1と凹状の角部CP2との組が複数組形成されることなる。
Claims (11)
- 主表面を有し、かつ前記主表面に溝を有する半導体基板と、
前記溝内を埋め込む埋め込み絶縁膜と、
少なくとも前記埋め込み絶縁膜上に位置するゲート電極層とを備え、
前記溝は、互いに対向する一方壁部と他方壁部とを有し、かつ前記一方壁部および前記他方壁部の少なくともいずれかの壁部の前記主表面と前記溝の底部との間に角部を有している、半導体装置。 - 前記角部は、前記溝の前記一方壁部および前記他方壁部の少なくともいずれかの壁部が断面において階段形状となるように形成されている、請求項1に記載の半導体装置。
- 前記角部から前記溝の前記底部までの下側部分が前記角部から前記主表面までの上側部分に対して断面において傾斜している、請求項1に記載の半導体装置。
- 前記溝の前記一方壁部側の前記半導体基板の前記主表面に形成された第1導電型の第1領域と、
前記溝の前記他方壁部側の前記半導体基板の前記主表面に形成された第2領域とをさらに備え、
前記第1領域の下に位置し、かつ前記第1領域と前記溝との間に挟まれる前記半導体基板の前記主表面に位置するように形成された第2導電型の第3領域と、
前記第2領域および前記溝の下に位置するように前記半導体基板に形成された第1導電型の第4領域とをさらに備え、
前記ゲート電極層は、前記半導体基板の前記主表面に位置する前記第3領域上に位置し、かつ前記埋め込み絶縁膜を介して前記第4領域と対向している、請求項1〜3のいずれかに記載の半導体装置。 - 前記第3領域よりも低い不純物濃度を有し、かつ前記第4領域とpn接合を構成するように前記第3および第4領域の下に形成された第2導電型の第5領域をさらに備えた、請求項4に記載の半導体装置。
- 前記第4領域が前記第3領域の下側に回りこむように形成されており、かつ
前記第3領域よりも低い不純物濃度を有し、かつ前記第4領域の下に形成された第2導電型の第5領域と、
前記第4領域と前記第5領域との間に形成され、かつ前記第4領域よりも高い不純物濃度を有する第1導電型の第6領域をさらに備えた、請求項4に記載の半導体装置。 - 平面視において前記第1領域と前記第2領域との間に位置するように、前記角部は前記溝の一部に形成されている、請求項4〜6のいずれかに記載の半導体装置。
- 平面視において前記第1領域と前記第2領域との間に位置するように、前記角部は前記溝の全体に形成されている、請求項4〜6のいずれかに記載の半導体装置。
- 主表面を有し、かつ互いに対向する一方壁部と他方壁部とを有する溝を前記主表面に有する半導体基板と、
前記溝内を埋め込む埋め込み絶縁膜と、
前記溝の前記一方壁部側の前記半導体基板の前記主表面に形成された第1領域と、
前記溝の前記他方壁部側の前記半導体基板の前記主表面に形成され、かつ前記第1領域との間で前記溝の下の前記半導体基板の領域を通して電流を流すための第2領域とをさらに備え、
前記溝は、前記一方壁部および前記他方壁部の少なくともいずれかの壁部を階段形状とするような角部を有している、半導体装置。 - 半導体基板の主表面に、互いに対向する1対の側壁を有する第1の溝を形成する工程と、
前記第1の溝の前記1対の側壁の少なくともいずれかを覆い、かつ前記1対の側壁の間の中央部を開口するようにマスクパターンを形成する工程と、
前記マスクパターンをマスクに用いて前記半導体基板をエッチングして前記第1の溝の少なくとも前記中央部に第2の溝を形成することにより、前記第1および第2の溝からなる溝の互いに対向する一方壁部および他方壁部の少なくともいずれかに階段形状をなす角部を形成する工程とを備えた、半導体装置の製造方法。 - 前記半導体基板は第1素子領域と第2素子領域と第3素子領域とを有し、
前記第1の溝は前記第1素子領域に形成され、かつ前記第1の溝と同じ工程で前記第2素子領域に第3の溝が形成され、かつ前記第3素子領域に第4の溝が形成され、
前記マスクパターンは、前記第3の溝を開口し、かつ前記第4の溝を覆うように形成され、
前記マスクパターンをマスクに用いて前記半導体基板をエッチングすることにより、前記第2の溝の形成と同時に前記第3の溝の深さが深くされる、請求項10に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009106767A JP5769915B2 (ja) | 2009-04-24 | 2009-04-24 | 半導体装置 |
EP10250552.6A EP2244300A3 (en) | 2009-04-24 | 2010-03-23 | Semiconductor device having a buried insulating layer and method of manufacturing the same |
US12/754,238 US8692325B2 (en) | 2009-04-24 | 2010-04-05 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009106767A JP5769915B2 (ja) | 2009-04-24 | 2009-04-24 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010258226A true JP2010258226A (ja) | 2010-11-11 |
JP2010258226A5 JP2010258226A5 (ja) | 2012-04-12 |
JP5769915B2 JP5769915B2 (ja) | 2015-08-26 |
Family
ID=42315688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009106767A Active JP5769915B2 (ja) | 2009-04-24 | 2009-04-24 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8692325B2 (ja) |
EP (1) | EP2244300A3 (ja) |
JP (1) | JP5769915B2 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011204924A (ja) * | 2010-03-25 | 2011-10-13 | Toshiba Corp | 半導体装置 |
WO2014037995A1 (ja) * | 2012-09-04 | 2014-03-13 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
JP2015018937A (ja) * | 2013-07-11 | 2015-01-29 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
JP2015162581A (ja) * | 2014-02-27 | 2015-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2016015373A (ja) * | 2014-07-01 | 2016-01-28 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
JP2017183544A (ja) * | 2016-03-30 | 2017-10-05 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
JP2018517279A (ja) * | 2015-04-08 | 2018-06-28 | 無錫華潤上華科技有限公司 | 横方向拡散金属酸化物半導体電界効果トランジスタ及びその製造方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5404550B2 (ja) * | 2010-07-29 | 2014-02-05 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
US9343538B2 (en) * | 2011-05-13 | 2016-05-17 | Richtek Technology Corporation | High voltage device with additional isolation region under gate and manufacturing method thereof |
US8686505B2 (en) * | 2012-07-27 | 2014-04-01 | Infineon Technologies Dresden Gmbh | Lateral semiconductor device and manufacturing method therefor |
CN104465379B (zh) * | 2013-09-18 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及形成方法 |
CN104979404A (zh) * | 2015-05-22 | 2015-10-14 | 西安电子科技大学 | 一种具有阶梯场氧的横向双扩散金属氧化物半导体场效应管 |
US9985019B2 (en) * | 2015-09-16 | 2018-05-29 | Vanguard International Semiconductor Corporation | Semiconductor structure with high-voltage and low-voltage CMOS devices and method for manufacturing the same |
JP6837384B2 (ja) * | 2017-05-23 | 2021-03-03 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
DE102017130213B4 (de) * | 2017-12-15 | 2021-10-21 | Infineon Technologies Ag | Planarer feldeffekttransistor |
JP7114290B2 (ja) | 2018-03-16 | 2022-08-08 | 株式会社東芝 | 半導体装置 |
US11132469B2 (en) * | 2019-04-17 | 2021-09-28 | Micron Technology, Inc. | Suspicious activity monitoring memory system |
CN111244178B (zh) * | 2020-01-15 | 2020-10-16 | 合肥晶合集成电路有限公司 | 扩散型场效应晶体管的形成方法 |
CN111276532A (zh) * | 2020-03-17 | 2020-06-12 | 合肥晶合集成电路有限公司 | 一种半导体器件及其制备方法 |
KR20220168360A (ko) * | 2021-06-16 | 2022-12-23 | 삼성전자주식회사 | 반도체 장치 |
US20230049610A1 (en) * | 2021-08-12 | 2023-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method for manufacturing the same |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07161806A (ja) * | 1993-12-02 | 1995-06-23 | Nec Corp | 半導体装置の製造方法 |
JPH0897411A (ja) * | 1994-09-21 | 1996-04-12 | Fuji Electric Co Ltd | 横型高耐圧トレンチmosfetおよびその製造方法 |
JPH10189964A (ja) * | 1996-12-27 | 1998-07-21 | Sanyo Electric Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP2000505956A (ja) * | 1996-12-23 | 2000-05-16 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 高電圧ldmosトランジスタ装置 |
JP2000150634A (ja) * | 1998-11-13 | 2000-05-30 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002141501A (ja) * | 2000-11-01 | 2002-05-17 | Fuji Electric Co Ltd | トレンチ型半導体装置の製造方法 |
JP2002329862A (ja) * | 2001-04-28 | 2002-11-15 | Hynix Semiconductor Inc | 高電圧素子及びその製造方法 |
JP2003031804A (ja) * | 2001-05-11 | 2003-01-31 | Fuji Electric Co Ltd | 半導体装置 |
JP2003078002A (ja) * | 2001-08-30 | 2003-03-14 | Hynix Semiconductor Inc | 半導体メモリ素子の製造方法 |
JP2005057146A (ja) * | 2003-08-07 | 2005-03-03 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US6864152B1 (en) * | 2003-05-20 | 2005-03-08 | Lsi Logic Corporation | Fabrication of trenches with multiple depths on the same substrate |
JP2005129654A (ja) * | 2003-10-22 | 2005-05-19 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2006060224A (ja) * | 2004-08-18 | 2006-03-02 | Agere Systems Inc | 強化された遮蔽構造を備えた金属酸化膜半導体デバイス |
WO2007072292A1 (en) * | 2005-12-19 | 2007-06-28 | Nxp B.V. | Asymmetrical field-effect semiconductor device with sti region |
JP2007294872A (ja) * | 2006-03-29 | 2007-11-08 | Fuji Electric Device Technology Co Ltd | 高耐圧横型mosfet |
US20080265363A1 (en) * | 2007-04-30 | 2008-10-30 | Jeffrey Peter Gambino | High power device isolation and integration |
JP2008288510A (ja) * | 2007-05-21 | 2008-11-27 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
JP2009506535A (ja) * | 2005-08-25 | 2009-02-12 | フリースケール セミコンダクター インコーポレイテッド | ポリ充填トレンチを用いる半導体装置 |
JP2009521131A (ja) * | 2005-10-31 | 2009-05-28 | フリースケール セミコンダクター インコーポレイテッド | 半導体装置とその形成方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6346451B1 (en) * | 1997-12-24 | 2002-02-12 | Philips Electronics North America Corporation | Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode |
JP2002237591A (ja) * | 2000-12-31 | 2002-08-23 | Texas Instruments Inc | Dmosトランジスタ・ソース構造とその製法 |
US7148540B2 (en) * | 2004-06-28 | 2006-12-12 | Agere Systems Inc. | Graded conductive structure for use in a metal-oxide-semiconductor device |
US7262471B2 (en) * | 2005-01-31 | 2007-08-28 | Texas Instruments Incorporated | Drain extended PMOS transistor with increased breakdown voltage |
KR100702775B1 (ko) * | 2005-05-03 | 2007-04-03 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
US7944000B2 (en) * | 2006-06-12 | 2011-05-17 | Ricoh Company, Ltd. | Semiconductor resistor, method of manufacturing the same, and current generating device using the same |
US20080237702A1 (en) * | 2007-03-26 | 2008-10-02 | Chih-Hua Lee | Ldmos transistor and method of making the same |
KR20090072013A (ko) * | 2007-12-28 | 2009-07-02 | 주식회사 동부하이텍 | 수평형 디모스 트랜지스터 |
-
2009
- 2009-04-24 JP JP2009106767A patent/JP5769915B2/ja active Active
-
2010
- 2010-03-23 EP EP10250552.6A patent/EP2244300A3/en not_active Withdrawn
- 2010-04-05 US US12/754,238 patent/US8692325B2/en active Active
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07161806A (ja) * | 1993-12-02 | 1995-06-23 | Nec Corp | 半導体装置の製造方法 |
JPH0897411A (ja) * | 1994-09-21 | 1996-04-12 | Fuji Electric Co Ltd | 横型高耐圧トレンチmosfetおよびその製造方法 |
JP2000505956A (ja) * | 1996-12-23 | 2000-05-16 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 高電圧ldmosトランジスタ装置 |
JPH10189964A (ja) * | 1996-12-27 | 1998-07-21 | Sanyo Electric Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP2000150634A (ja) * | 1998-11-13 | 2000-05-30 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002141501A (ja) * | 2000-11-01 | 2002-05-17 | Fuji Electric Co Ltd | トレンチ型半導体装置の製造方法 |
JP2002329862A (ja) * | 2001-04-28 | 2002-11-15 | Hynix Semiconductor Inc | 高電圧素子及びその製造方法 |
JP2003031804A (ja) * | 2001-05-11 | 2003-01-31 | Fuji Electric Co Ltd | 半導体装置 |
JP2003078002A (ja) * | 2001-08-30 | 2003-03-14 | Hynix Semiconductor Inc | 半導体メモリ素子の製造方法 |
US6864152B1 (en) * | 2003-05-20 | 2005-03-08 | Lsi Logic Corporation | Fabrication of trenches with multiple depths on the same substrate |
JP2005057146A (ja) * | 2003-08-07 | 2005-03-03 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2005129654A (ja) * | 2003-10-22 | 2005-05-19 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2006060224A (ja) * | 2004-08-18 | 2006-03-02 | Agere Systems Inc | 強化された遮蔽構造を備えた金属酸化膜半導体デバイス |
JP2009506535A (ja) * | 2005-08-25 | 2009-02-12 | フリースケール セミコンダクター インコーポレイテッド | ポリ充填トレンチを用いる半導体装置 |
JP2009521131A (ja) * | 2005-10-31 | 2009-05-28 | フリースケール セミコンダクター インコーポレイテッド | 半導体装置とその形成方法 |
WO2007072292A1 (en) * | 2005-12-19 | 2007-06-28 | Nxp B.V. | Asymmetrical field-effect semiconductor device with sti region |
JP2007294872A (ja) * | 2006-03-29 | 2007-11-08 | Fuji Electric Device Technology Co Ltd | 高耐圧横型mosfet |
US20080265363A1 (en) * | 2007-04-30 | 2008-10-30 | Jeffrey Peter Gambino | High power device isolation and integration |
JP2008288510A (ja) * | 2007-05-21 | 2008-11-27 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
Non-Patent Citations (1)
Title |
---|
JPN6014014532; Il-Yong Park et al.: 'BD180 - a new 0.18 mum BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V' Power Semiconductor Devices and IC's , 20080518, pp.64-pp.67 * |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011204924A (ja) * | 2010-03-25 | 2011-10-13 | Toshiba Corp | 半導体装置 |
US8637928B2 (en) | 2010-03-25 | 2014-01-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
US8847309B2 (en) | 2010-03-25 | 2014-09-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
WO2014037995A1 (ja) * | 2012-09-04 | 2014-03-13 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
JP2015018937A (ja) * | 2013-07-11 | 2015-01-29 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
JP2015162581A (ja) * | 2014-02-27 | 2015-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9356138B2 (en) | 2014-02-27 | 2016-05-31 | Renesas Electronics Corporation | Semiconductor device |
US9755069B2 (en) | 2014-02-27 | 2017-09-05 | Renesas Electronics Corporation | Semiconductor device |
JP2016015373A (ja) * | 2014-07-01 | 2016-01-28 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
JP2018517279A (ja) * | 2015-04-08 | 2018-06-28 | 無錫華潤上華科技有限公司 | 横方向拡散金属酸化物半導体電界効果トランジスタ及びその製造方法 |
JP2017183544A (ja) * | 2016-03-30 | 2017-10-05 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20100270616A1 (en) | 2010-10-28 |
JP5769915B2 (ja) | 2015-08-26 |
EP2244300A2 (en) | 2010-10-27 |
US8692325B2 (en) | 2014-04-08 |
EP2244300A3 (en) | 2013-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5769915B2 (ja) | 半導体装置 | |
TWI605596B (zh) | 絕緣閘切換裝置及其製造方法 | |
US7981783B2 (en) | Semiconductor device and method for fabricating the same | |
KR101883010B1 (ko) | 반도체 소자 및 그 소자의 제조 방법 | |
US8125023B2 (en) | Vertical type power semiconductor device having a super junction structure | |
US8373227B2 (en) | Semiconductor device and method having trenches in a drain extension region | |
US20170062608A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP6078390B2 (ja) | 半導体装置 | |
JP6710627B2 (ja) | 半導体装置およびその製造方法 | |
KR101531882B1 (ko) | 반도체 소자 및 그 제조 방법 | |
CN106992173B (zh) | 包括场效应晶体管的半导体器件 | |
CN111108593A (zh) | 窄深沟槽的沉降物至掩埋层连接区域 | |
US20110220991A1 (en) | Semiconductor device | |
JP2008084995A (ja) | 高耐圧トレンチmosトランジスタ及びその製造方法 | |
JP6571467B2 (ja) | 絶縁ゲート型スイッチング素子とその製造方法 | |
US20160149029A1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP2009239096A (ja) | 半導体装置 | |
US9324800B1 (en) | Bidirectional MOSFET with suppressed bipolar snapback and method of manufacture | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
KR20130007474A (ko) | 반도체 장치 | |
TWI601295B (zh) | 斷閘極金氧半場效電晶體 | |
JP2014022487A (ja) | 半導体装置 | |
TW201916104A (zh) | 具有多閘極結構之ldmos finfet結構 | |
US10418479B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
KR20100072405A (ko) | 반도체 소자, 이의 제조방법 및 플래시 메모리 소자 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120224 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120224 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130530 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130604 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130801 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140408 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140609 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20150120 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150413 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20150420 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150623 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150624 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5769915 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |