JP2015162581A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2015162581A JP2015162581A JP2014036944A JP2014036944A JP2015162581A JP 2015162581 A JP2015162581 A JP 2015162581A JP 2014036944 A JP2014036944 A JP 2014036944A JP 2014036944 A JP2014036944 A JP 2014036944A JP 2015162581 A JP2015162581 A JP 2015162581A
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Abstract
【解決手段】LDMOSトランジスタPD1の分離絶縁膜SISの上面に溝HLを形成することにより、ゲート電極GEの一部を溝HL内に埋め込む。これにより、分離絶縁膜SISのソース側の端部近傍の半導体基板SB内において電界が集中することを防ぐ。
【選択図】図2
Description
以下に、図1および図2を用いて、本実施の形態の半導体装置の構造について説明する。図1は、本実施の形態の半導体装置であるLDMOSトランジスタの構造を示す平面図である。図2は、図1のA−A線における断面図である。図1および図2に示すLDMOSトランジスタPD1は、Pチャネル型MOS型のFET(Field Effect Transistor:電界効果トランジスタ)である。
本実施の形態では、LDMOSトランジスタの分離絶縁膜の上面に設ける溝の幅を、前記実施の形態に比べて小さくし、そのような溝を分離絶縁膜の上面に複数設けることについて、図26〜図28を用いて説明する。図26は、本実施の形態の半導体装置であるLDMOSトランジスタPD2aを示す平面図であり、図27は、本実施の形態の半導体装置の変形例であるLDMOSトランジスタPD2bを示す平面図である。また、図28は本実施の形態の半導体装置であるLDMOSトランジスタPD2aを示す断面図であり、図28は図26のD−D線における断面図である。なお、図27のE−E線における断面図は、図28に示す断面図と同様の構造となる。
本実施の形態では、LDMOSトランジスタの分離絶縁膜の底部にライナー絶縁膜を形成する場合について説明する。
図33に、本実施の形態の半導体装置であるLDMOSトランジスタPD4の断面図を示す。LDMOSトランジスタPD4は、前記実施の形態1のLDMOSトランジスタPD1(図2参照)をNチャネル型に変更したものである。本実施の形態においても、溝HLに埋め込まれたゲート電極GEにより高いフィールドプレート効果が得られる。このため、図34のシミュレーション結果に示すように、LDMOSトランジスタPD4では、第1比較例のNチャネル型のLDMOSトランジスタCD1(図37参照)に比べて、電界が低減されることで、インパクトイオン化発生レート(IIGR)の大きさが反映されるウェル電流Iwが約1桁低減する。したがって、本実施の形態の半導体装置では、ホットキャリアストレス中のオン抵抗Rspの変動を抑制することができるため、半導体装置の信頼性を向上させることができる。
BVon オン耐圧
CD1〜CD4 LDMOSトランジスタ
CN1〜CN3 コンタクトプラグ
DC ドレイン領域
DFT ドリフト領域
GE ゲート電極
GIS ゲート絶縁膜
HL 溝
HM ハードマスク
HWL ウェル領域
Ig ゲート電流
INC 配線
IS 層間絶縁膜
Iw ウェル電流
LIS ライナー絶縁膜
Lt 溝HLの幅
Ls 分離絶縁膜SISのソース側端と溝HLとの距離
Lov ゲート電極GEの分離絶縁膜SISに対する被り量である長さ
Ld 分離絶縁膜SISの直下のドレイン領域の長さ
Lx 溝HLの深さ
Ly 分離絶縁膜SISの厚さ
PD1〜PD4 LDMOSトランジスタ
SB 半導体基板
SC ソース領域
SIS 分離絶縁膜
TNC 溝
WC ウェル領域
WL ウェル領域
Claims (5)
- 半導体基板と、
前記半導体基板の主面に形成された、一対の第1導電型のソース領域および前記第1導電型のドレイン領域と、
前記ソース領域と前記ドレイン領域との間において、前記半導体基板の主面に形成された分離溝内に埋め込まれた分離絶縁膜と、
前記分離絶縁膜と前記ソース領域との間の前記半導体基板上に形成されたゲート絶縁膜と、
前記ソース領域と前記ドレイン領域との間において、前記ゲート絶縁膜の直上および前記分離絶縁膜の直上に亘って形成されたゲート電極と、
前記分離絶縁膜の下の前記半導体基板内に形成され、その一方の端部が前記ゲート絶縁膜の直下に位置している前記第1導電型のドリフト領域と、
前記分離絶縁膜の上面に形成され、内側に前記ゲート電極の一部が埋め込まれた溝と、
を有し、
前記ゲート電極と前記ドレイン領域との間隔は、前記ゲート電極と前記ソース領域との間隔よりも大きく、
前記溝は、前記分離絶縁膜の前記ソース領域側の端から離間し、かつ前記ゲート電極の前記ドレイン領域側の端からソース側に離間して配置されており、
前記溝の底面は、前記分離絶縁膜の途中深さに位置している、半導体装置。 - 請求項1記載の半導体装置において、
前記溝の深さは、前記分離絶縁膜の厚さの1/3以上であり、
前記溝の底と前記溝の直下の半導体基板との間の距離は、前記ゲート絶縁膜の厚さより大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記溝と、前記分離絶縁膜の前記ソース領域側の端との間の距離は、前記ゲート絶縁膜の厚さより大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記溝が前記分離絶縁膜の上面に複数設けられている、半導体装置。 - 請求項1記載の半導体装置において、
前記分離絶縁膜は、複数の絶縁膜を積層した構成を有し、
前記溝は、前記複数の絶縁膜のうち、最下層の絶縁膜に達している、半導体装置。
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US20160240664A1 (en) | 2016-08-18 |
US9755069B2 (en) | 2017-09-05 |
US9356138B2 (en) | 2016-05-31 |
TW201539750A (zh) | 2015-10-16 |
JP6279346B2 (ja) | 2018-02-14 |
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