JP2006245618A - 受動素子内蔵半導体装置 - Google Patents
受動素子内蔵半導体装置 Download PDFInfo
- Publication number
- JP2006245618A JP2006245618A JP2006164565A JP2006164565A JP2006245618A JP 2006245618 A JP2006245618 A JP 2006245618A JP 2006164565 A JP2006164565 A JP 2006164565A JP 2006164565 A JP2006164565 A JP 2006164565A JP 2006245618 A JP2006245618 A JP 2006245618A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- passive element
- metal wire
- stage
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】インナリード6とステージ4とを有するリードフレーム2のステージ4に半導体素子1が搭載される。ステージ4上に形成された凹部内に、絶縁部材7を介して受動素子8が搭載される。半導体素子1とインナリード6の間を第1の金属ワイヤ5で電気的に接続する。受動素子8の電極とインナリード6の間を第2の金属ワイヤ5で電気的に接続する。リードフレーム6、半導体素子1、受動素子8、第1の金属ワイヤ5及び第2の金属ワイヤ5を封止樹脂3により封止する。
【選択図】図5
Description
本発明の第4実施例による半導体装置では、上述の第3実施例と同様にステージを4分割し、半導体素子1を搭載する側の面にチップコンデンサを搭載したものである。すなわち、チップコンデンサ8は半導体素子1の周囲の分割ステージ4−1〜4−4上に搭載される。この場合、固定用絶縁体12は分割ステージ4−1〜4−4の裏側に貼り付けられ、分割ステージ4−1〜4−4は固定用絶縁体12により互いに固定される。
2 リードフレーム
3 封止樹脂
4 ステージ
4a 凹部
5 金属ワイヤ
6 インナリード
6−1 電源電位リード
6−2 GND電位リード
7 絶縁テープ
8 チップコンデンサ
9 チップインダクタ
11 サポートバー
11a 傾斜部
12 固定用絶縁体
13 導電性接合材料
14 接続バー
Claims (3)
- インナリードとステージとを有するリードフレームと、
該リードフレームの該ステージに搭載された半導体素子と、
前記ステージ上に形成された凹部と、
該凹部内に絶縁部材を介して搭載された受動素子と、
前記半導体素子と前記インナリードの間を電気的に接続する第1の金属ワイヤと、
前記受動素子の電極と前記インナリードの間を電気的に接続する第2の金属ワイヤと、
前記リードフレーム、前記半導体素子、前記受動素子、前記第1の金属ワイヤ及び前記第2の金属ワイヤを封止する封止樹脂と
を有することを特徴とする受動素子内蔵半導体装置。 - 請求項1記載の受動素子内蔵半導体装置であって、
前記凹部内に絶縁部材を介して複数の受動素子が搭載され、該複数の受動素子の電極どうしを電気的に接続する第3の金属ワイヤを有することを特徴とする受動素子内蔵半導体装置。 - 請求項1又は2記載の受動素子内蔵半導体装置であって、
前記半導体素子と前記受動素子の電極とを電気的に接続する第4の金属ワイヤを更に有することを特徴とする受動素子内蔵半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006164565A JP2006245618A (ja) | 2006-06-14 | 2006-06-14 | 受動素子内蔵半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006164565A JP2006245618A (ja) | 2006-06-14 | 2006-06-14 | 受動素子内蔵半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002204560A Division JP2004047811A (ja) | 2002-07-12 | 2002-07-12 | 受動素子内蔵半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006245618A true JP2006245618A (ja) | 2006-09-14 |
Family
ID=37051610
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006164565A Pending JP2006245618A (ja) | 2006-06-14 | 2006-06-14 | 受動素子内蔵半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2006245618A (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100109136A1 (en) * | 2008-10-30 | 2010-05-06 | Denso Corporation | Semiconductor device including semiconductor chip mounted on lead frame |
JP2012227229A (ja) * | 2011-04-15 | 2012-11-15 | Denso Corp | 半導体装置 |
EP2618371A2 (en) | 2012-01-19 | 2013-07-24 | Semiconductor Components Industries, LLC | Semiconductor device |
US8546940B2 (en) | 2008-09-29 | 2013-10-01 | Toppan Printing Co., Ltd. | Manufacturing method of lead frame substrate and semiconductor apparatus |
JP2013232622A (ja) * | 2013-01-21 | 2013-11-14 | Lapis Semiconductor Co Ltd | 半導体装置及び計測機器 |
US8921987B2 (en) | 2012-04-27 | 2014-12-30 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device having an oscillator |
US9230890B2 (en) | 2012-04-27 | 2016-01-05 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
JP2019021944A (ja) * | 2018-11-07 | 2019-02-07 | ラピスセミコンダクタ株式会社 | 半導体装置および計測装置 |
-
2006
- 2006-06-14 JP JP2006164565A patent/JP2006245618A/ja active Pending
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160021304A (ko) | 2008-09-29 | 2016-02-24 | 도판 인사츠 가부시키가이샤 | 리드 프레임 기판의 제조 방법 |
US8546940B2 (en) | 2008-09-29 | 2013-10-01 | Toppan Printing Co., Ltd. | Manufacturing method of lead frame substrate and semiconductor apparatus |
US8703598B2 (en) | 2008-09-29 | 2014-04-22 | Toppan Printing Co., Ltd. | Manufacturing method of lead frame substrate |
JP2010135737A (ja) * | 2008-10-30 | 2010-06-17 | Denso Corp | 半導体装置 |
CN103199074A (zh) * | 2008-10-30 | 2013-07-10 | 株式会社电装 | 包含安装在引线框上的半导体芯片的半导体装置 |
US20100109136A1 (en) * | 2008-10-30 | 2010-05-06 | Denso Corporation | Semiconductor device including semiconductor chip mounted on lead frame |
US8624367B2 (en) | 2008-10-30 | 2014-01-07 | Denso Corporation | Semiconductor device including semiconductor chip mounted on lead frame |
US9029993B2 (en) | 2008-10-30 | 2015-05-12 | Denso Corporation | Semiconductor device including semiconductor chip mounted on lead frame |
JP2012227229A (ja) * | 2011-04-15 | 2012-11-15 | Denso Corp | 半導体装置 |
EP2618371A2 (en) | 2012-01-19 | 2013-07-24 | Semiconductor Components Industries, LLC | Semiconductor device |
US8759955B2 (en) | 2012-01-19 | 2014-06-24 | Semiconductor Components Industries, Llc | Semiconductor device with chips on isolated mount regions |
DE202013012738U1 (de) | 2012-01-19 | 2019-01-08 | Semiconductor Components Industries, Llc | Halbleitervorrichtung |
US10243515B2 (en) | 2012-04-27 | 2019-03-26 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US9257377B2 (en) | 2012-04-27 | 2016-02-09 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device having an oscillator |
US9230890B2 (en) | 2012-04-27 | 2016-01-05 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US9787250B2 (en) | 2012-04-27 | 2017-10-10 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US8921987B2 (en) | 2012-04-27 | 2014-12-30 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device having an oscillator |
US10615108B2 (en) | 2012-04-27 | 2020-04-07 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US10622944B2 (en) | 2012-04-27 | 2020-04-14 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US20200235046A1 (en) * | 2012-04-27 | 2020-07-23 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US11309234B2 (en) | 2012-04-27 | 2022-04-19 | Lapis Semiconductor Co., Ltd. | Semiconductor device having an oscillator and an associated integrated circuit |
US11854952B2 (en) | 2012-04-27 | 2023-12-26 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
JP2013232622A (ja) * | 2013-01-21 | 2013-11-14 | Lapis Semiconductor Co Ltd | 半導体装置及び計測機器 |
JP2019021944A (ja) * | 2018-11-07 | 2019-02-07 | ラピスセミコンダクタ株式会社 | 半導体装置および計測装置 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5169353B2 (ja) | パワーモジュール | |
JP2006245618A (ja) | 受動素子内蔵半導体装置 | |
US7391106B2 (en) | Stack type package | |
CN105814687A (zh) | 半导体封装及其安装结构 | |
JP2004047811A (ja) | 受動素子内蔵半導体装置 | |
EP2398302A1 (en) | Semiconductor module and semiconductor device | |
JP2008130694A (ja) | 電子部品モジュール | |
JP2012104633A (ja) | 半導体装置 | |
JP2005045237A (ja) | 等級分け可能な構造技術によるパワー半導体モジュール | |
JP4908091B2 (ja) | 半導体装置 | |
JP6365772B2 (ja) | パワーモジュール | |
JP2010183100A (ja) | 半導体増幅器 | |
JP4622646B2 (ja) | 半導体装置 | |
CN100401510C (zh) | 半导体装置、半导体主体及其制造方法 | |
US20050178582A1 (en) | Circuit board with mounting pads for reducing parasitic effect | |
JP2006114533A (ja) | 半導体装置 | |
JP6584333B2 (ja) | パワーモジュール | |
JP4215530B2 (ja) | 回路装置 | |
JP4745205B2 (ja) | 半導体装置 | |
JP4545537B2 (ja) | 半導体装置及び半導体装置ユニット | |
JP2004031432A (ja) | 半導体装置 | |
JP2005340535A (ja) | 電子部品実装基板 | |
JP2007103391A (ja) | 半導体増幅器 | |
JPH11195729A (ja) | 半導体装置 | |
JP6136061B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060614 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080704 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080708 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20081111 |