JP4908091B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4908091B2 JP4908091B2 JP2006201540A JP2006201540A JP4908091B2 JP 4908091 B2 JP4908091 B2 JP 4908091B2 JP 2006201540 A JP2006201540 A JP 2006201540A JP 2006201540 A JP2006201540 A JP 2006201540A JP 4908091 B2 JP4908091 B2 JP 4908091B2
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- 239000004065 semiconductor Substances 0.000 title claims description 77
- 239000003990 capacitor Substances 0.000 claims description 80
- 239000000758 substrate Substances 0.000 claims description 51
- 239000004020 conductor Substances 0.000 description 19
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000009499 grossing Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000005283 ground state Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Dc-Dc Converters (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
この態様によれば、リードフレームパッケージにおいて、キャパシタをパッケージ内部に好適に内蔵することができる。
この態様によれば、複数の第2電極を、キャパシタを設けたい位置に形成することにより、半導体基板上に形成された集積回路においてシャントキャパシタが必要な箇所の直近に、それを適切に配置することができる。
また、パッドは、電源回路により生成された電圧が出力される出力端子であって、キャパシタは、電源回路の出力端子に設けられたデカップリングキャパシタであってもよい。電源回路は、リニアレギュレータであってもよい。
言うまでもなく、以上の考察は、シャントキャパシタC2についても同様に成り立つ。
Claims (9)
- 上面に第1、第2電極が形成され、前記第1電極が接地される基体と、
前記基体の第1電極上に実装され、接地電位が前記基体の前記第1電極から供給される半導体基板と、
外部接続用に設けられた前記半導体基板のパッドと、前記基体の前記第2電極とを接続するボンディングワイヤと、
を備え、
前記基体は誘電体で形成され、その内部には複数の電極が誘電体層を挟んで積層されており、前記第1電極と前記第2電極が、積層された電極にそれぞれ接続されることにより、キャパシタを構成することを特徴とする半導体装置。 - 外部接続端子として設けられたリードをさらに備え、
前記第2電極は、前記基体の下面にも前記リードの一端と接続可能な形状で形成され、前記リードの一端と前記第2電極が接続されたことを特徴とする請求項1に記載の半導体装置。 - 前記基体の下面に形成された前記第2電極の形状は、前記リードの一端と略同一形状であることを特徴とする請求項2に記載の半導体装置。
- 接地用の外部接続端子として設けられたアイランドをさらに備え、
前記第1電極は、前記基体の下面にも形成されており、前記アイランドと前記基体の下面に形成された前記第1電極とが接続されたことを特徴とする請求項1から3のいずれかに記載の半導体装置。 - 接地用の外部接続端子として設けられたアイランドと、
外部接続端子として設けられたリードと、
をさらに備え、
前記第1電極は、前記基体の下面にも形成されており、
前記第2電極は、前記基体の下面にも前記リードの一端と接続可能な形状で形成されており、
前記アイランドと前記リードとは、リードフレームとして一体に形成され、それぞれが前記第1電極、前記第2電極に接続された後、切断されることを特徴とする請求項1に記載の半導体装置。 - 前記基体の上面には、互いに絶縁された複数の第2電極が形成されており、
前記ボンディングワイヤは前記第2電極ごとに設けられ、それぞれの前記第2電極を対応するパッドと接続し、
前記複数の第2電極は、前記第1電極を共通の接地端子として並列に設けられた複数のキャパシタとして機能することを特徴とする請求項1または2に記載の半導体装置。 - 前記半導体基板は、電源回路を含み、
前記パッドは、前記電源回路に電源電圧を供給する入力端子であって、
前記キャパシタは、前記電源回路の入力端子に設けられたデカップリングキャパシタであることを特徴とする請求項1から3のいずれかに記載の半導体装置。 - 前記半導体基板は、電源回路を含み、
前記パッドは、前記電源回路により生成された電圧が出力される出力端子であって、
前記キャパシタは、前記電源回路の出力端子に設けられたデカップリングキャパシタであることを特徴とする請求項1から3のいずれかに記載の半導体装置。 - 前記電源回路は、リニアレギュレータであることを特徴とする請求項7または8に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006201540A JP4908091B2 (ja) | 2006-07-25 | 2006-07-25 | 半導体装置 |
US11/880,669 US7948078B2 (en) | 2006-07-25 | 2007-07-24 | Semiconductor device |
CN 200710137374 CN101114640B (zh) | 2006-07-25 | 2007-07-25 | 半导体装置 |
US13/083,951 US8089149B2 (en) | 2006-07-25 | 2011-04-11 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006201540A JP4908091B2 (ja) | 2006-07-25 | 2006-07-25 | 半導体装置 |
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JP2008028282A JP2008028282A (ja) | 2008-02-07 |
JP4908091B2 true JP4908091B2 (ja) | 2012-04-04 |
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JP2006201540A Active JP4908091B2 (ja) | 2006-07-25 | 2006-07-25 | 半導体装置 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US8897046B2 (en) * | 2009-12-25 | 2014-11-25 | Rohm Co., Ltd. | DC voltage conversion module, semiconductor module, and method of making semiconductor module |
JP5784304B2 (ja) * | 2009-12-25 | 2015-09-24 | ローム株式会社 | 直流電圧変換モジュール |
KR20130038582A (ko) * | 2011-10-10 | 2013-04-18 | 삼성전자주식회사 | 파워 노이즈가 줄어든 전압 발생회로를 구비한 반도체 칩 패키지 |
US9401601B2 (en) * | 2013-12-03 | 2016-07-26 | Sensata Technologies, Inc. | Circuit designs for induced transient immunity |
Family Cites Families (5)
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JP2822825B2 (ja) * | 1992-12-26 | 1998-11-11 | 株式会社村田製作所 | 複合電子部品 |
JPH08181274A (ja) * | 1994-12-27 | 1996-07-12 | Sony Corp | ハイブリッドic |
JP3233196B2 (ja) * | 1996-09-11 | 2001-11-26 | 沖電気工業株式会社 | 半導体デバイスパッケージングシステム |
JP2006032507A (ja) * | 2004-07-14 | 2006-02-02 | Matsushita Electric Ind Co Ltd | 基板内蔵コンデンサと基板 |
JP4885635B2 (ja) * | 2006-07-25 | 2012-02-29 | ローム株式会社 | 半導体装置 |
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