JP4745205B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4745205B2 JP4745205B2 JP2006324474A JP2006324474A JP4745205B2 JP 4745205 B2 JP4745205 B2 JP 4745205B2 JP 2006324474 A JP2006324474 A JP 2006324474A JP 2006324474 A JP2006324474 A JP 2006324474A JP 4745205 B2 JP4745205 B2 JP 4745205B2
- Authority
- JP
- Japan
- Prior art keywords
- ground
- semiconductor chip
- lead
- wiring
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
本発明の例は、リードフレームを用いて形成されるパッケージ装置に関する。
次に、最良と思われるいくつかの実施の形態について説明する。
図1及び図2は、本発明の例に用いられるリードフレームのインナーリードの基本構造を示す平面図である。
よって、図2に示すH型構造のように、グラウンド用インナーリード1が、4方向に延びる吊りピンとして機能し、半導体チップ5を支持する構造となることが望ましい。
以下に、上述のリードフレームを用いたパッケージ装置の実施例について説明を行う。
(1) 第1の変形例
図5は、本変形例の半導体チップ側の平面図である。
図6は、本変形例の半導体チップ側の平面図である。
本発明の例によれば、半導体チップの内部配線抵抗に起因する性能低下を抑制し、且つ、半導体チップが搭載されるリードフレームのリード配線の引き回しを簡素化できる。
Claims (5)
- リードフレーム内に設けられるグラウンド用或いは電源電圧用の第1のインナーリードと、前記リードフレーム上に搭載され、第1の辺に沿って設けられるグラウンド用或いは電源電圧用となる第1のパッドを有する半導体チップとを具備し、前記第1のインナーリードは、前記第1の辺と平行となる方向に延在し、前記第1の辺と交差する方向に隣り合い、吊りピンとして機能する2つの第1の配線部と、前記第1の辺と交差する方向に延在し、前記2つの第1の配線部間に配置され、前記2つの第1の配線部に接続される第2の配線部とから形成されるH型構造を有し、前記第1の辺は、前記2つの第1の配線部のうち一方と上下に重なるように配置され、前記第1のパッドは、前記2つの第1の配線部のうち前記一方と接続されることを特徴とする半導体装置。
- 前記第1のパッドは、前記第1の辺に沿って、2個以上設けられることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップは、さらに、前記第1の辺と対向する第2の辺に沿って設けられる第2のパッドを有し、前記第2のパッドは、前記2つの第1の配線部のうち他方と接続されることを特徴とする請求項1に記載の半導体装置。
- 前記リードフレームは、さらに、信号配線用の複数の第2のインナーリードを有し、前記半導体チップは、さらに、前記第2の辺に沿って複数の第3のパッドを有し、前記複数の第3のパッドと接続される前記複数の第2のインナーリードは、前記半導体チップの下面を経由して、その一端が、前記第2の辺に沿って設けられることを特徴とする請求項3に記載の半導体装置。
- 前記半導体チップは、前記第1及び第2のインナーリード上に絶縁層を介して搭載され、前記リードフレームは、前記半導体チップを搭載するためのタブを有しないことを特徴とする請求項4に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006324474A JP4745205B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体装置 |
US11/947,030 US20080128877A1 (en) | 2006-11-30 | 2007-11-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006324474A JP4745205B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008140914A JP2008140914A (ja) | 2008-06-19 |
JP4745205B2 true JP4745205B2 (ja) | 2011-08-10 |
Family
ID=39474759
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006324474A Expired - Fee Related JP4745205B2 (ja) | 2006-11-30 | 2006-11-30 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080128877A1 (ja) |
JP (1) | JP4745205B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5361426B2 (ja) * | 2009-02-05 | 2013-12-04 | 株式会社東芝 | 半導体デバイス |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH029157A (ja) * | 1988-06-28 | 1990-01-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH0286157A (ja) * | 1988-09-22 | 1990-03-27 | Hitachi Ltd | 半導体装置 |
JPH05251622A (ja) * | 1991-04-17 | 1993-09-28 | Hitachi Ltd | 樹脂封止型半導体装置 |
JPH06224362A (ja) * | 1992-10-28 | 1994-08-12 | Internatl Business Mach Corp <Ibm> | 電子素子用リードフレーム・パッケージ |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5198833A (en) * | 1987-11-04 | 1993-03-30 | Sharp Kabushiki Kaisha | Variable density ink-jet dot printer |
JPH0760838B2 (ja) * | 1990-11-13 | 1995-06-28 | 株式会社東芝 | 半導体装置 |
JPH05175409A (ja) * | 1991-12-24 | 1993-07-13 | Sony Corp | 樹脂封止型半導体装置 |
KR970010678B1 (ko) * | 1994-03-30 | 1997-06-30 | 엘지반도체 주식회사 | 리드 프레임 및 이를 이용한 반도체 패키지 |
US5834831A (en) * | 1994-08-16 | 1998-11-10 | Fujitsu Limited | Semiconductor device with improved heat dissipation efficiency |
US5907769A (en) * | 1996-12-30 | 1999-05-25 | Micron Technology, Inc. | Leads under chip in conventional IC package |
-
2006
- 2006-11-30 JP JP2006324474A patent/JP4745205B2/ja not_active Expired - Fee Related
-
2007
- 2007-11-29 US US11/947,030 patent/US20080128877A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH029157A (ja) * | 1988-06-28 | 1990-01-12 | Mitsubishi Electric Corp | 半導体装置 |
JPH0286157A (ja) * | 1988-09-22 | 1990-03-27 | Hitachi Ltd | 半導体装置 |
JPH05251622A (ja) * | 1991-04-17 | 1993-09-28 | Hitachi Ltd | 樹脂封止型半導体装置 |
JPH06224362A (ja) * | 1992-10-28 | 1994-08-12 | Internatl Business Mach Corp <Ibm> | 電子素子用リードフレーム・パッケージ |
Also Published As
Publication number | Publication date |
---|---|
JP2008140914A (ja) | 2008-06-19 |
US20080128877A1 (en) | 2008-06-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102693967B (zh) | 半导体存储卡 | |
JP4372022B2 (ja) | 半導体装置 | |
US7342309B2 (en) | Semiconductor device and fabrication method thereof | |
US20050156323A1 (en) | Semiconductor apparatus | |
JP3415509B2 (ja) | 半導体装置 | |
JP2006245618A (ja) | 受動素子内蔵半導体装置 | |
JPH1131717A (ja) | 半導体チップ及びそれを備えた表示装置 | |
JPH0936297A (ja) | 半導体装置及び半導体装置ユニット及び半導体装置用リードフレーム | |
JP5164490B2 (ja) | 半導体装置及びその製造方法 | |
JP4745205B2 (ja) | 半導体装置 | |
JP2008078354A (ja) | 半導体装置 | |
JP2008124072A (ja) | 半導体装置 | |
JP4435074B2 (ja) | 半導体装置およびその製造方法 | |
JP2014175665A (ja) | ボンドワイヤのためのブレース | |
JP2007294884A (ja) | 半導体装置 | |
JP2007281509A (ja) | 半導体装置 | |
US20110115063A1 (en) | Integrated Circuit Packaging with Split Paddle | |
JP5048627B2 (ja) | リードフレーム及び半導体装置 | |
JP2006186053A (ja) | 積層型半導体装置 | |
JP4545537B2 (ja) | 半導体装置及び半導体装置ユニット | |
JP5593156B2 (ja) | 半導体装置及びその製造方法 | |
JP4384143B2 (ja) | Icチップ積層構造を有する電子機器用モジュール | |
US20120025898A1 (en) | Circuit Device | |
US20070215989A1 (en) | Semiconductor chip assembly | |
JP4271096B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090318 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101027 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101102 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101220 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110125 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110325 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110412 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110511 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140520 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140520 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |