JP2005150478A - マルチチップモジュール - Google Patents
マルチチップモジュール Download PDFInfo
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- JP2005150478A JP2005150478A JP2003387188A JP2003387188A JP2005150478A JP 2005150478 A JP2005150478 A JP 2005150478A JP 2003387188 A JP2003387188 A JP 2003387188A JP 2003387188 A JP2003387188 A JP 2003387188A JP 2005150478 A JP2005150478 A JP 2005150478A
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Abstract
【解決手段】 搭載基板の表面上に面付けされた第1半導体チップ上に背中合わせにチップ表面の周辺部にボンディングパッドが設けられた第2半導体チップを搭載し、上記第2半導体チップ表面の上記ボンディングパッドが形成される部分を含む所定エリアを除いた部分にスペーサを設けてその上に上記第2半導体チップと同じ回路機能を有し、同じ向きに第3半導体チップを搭載し、上記第2半導体チップ及び第3半導体チップのボンディングパッドを上記搭載基板上に形成された対応する電極に対してボンディングワイヤで接続し、上記搭載基板上の上記第1、第2、第3半導体チップ及びボンディングワイヤを封止体で封止する。
【選択図】 図1
Description
CPU…中央処理装置、DSP…データシグナルプロセッサDSP、XYMEM…メモリ、XYCNT…メモリコントローラ、CACHE…キュッシュメモリ、CCN…キャッシュメモリコントローラ、MMU…メモリマネージメントコントローラ、TLB…トランスレーションルックアサイドバッファ、INTC…割り込みコントローラ、CPG/WDT…クロック発振器/ウォッチドッグタイマ、VIO…ビデオI/Oモジュール、UBC…ユーザーブレークコントローラ、AUD…アドバンストユーザーデバッガ、TMU…タイマユニット、CMT…コンペアマッチタイマ、SIOF0…シリアルI/O(FIFO付き)、SCIF1…FIFO内蔵シリアルコミュニケーションインターフェイス、I2 C…I2 Cコントローラ、MFI…多機能インターフェイス、FLCTL…NAND/ANDフラッシュインターフェイス、H−UDI…ユーザーデバックインターフェイス、ASERAM…ASEメモリ、PFC…メモリピンファンクションコントローラ、RWDT…RCLK動作ウォッチドッグタイマ、BSC…バスステートコントローラ、DMAC…ダイレクトメモリアクセスコントローラ。
Claims (10)
- 搭載基板の表面上に面付けされた第1半導体チップと、
上記第1半導体チップ上に背中合わせで搭載され、チップ表面の周辺部にボンディングパッドが設けられた第2半導体チップと、
上記第2半導体チップ表面の上記ボンディングパッドが形成される部分を含む所定エリアを除いた部分に搭載されたスペーサと、
上記スペーサ上に搭載され、上記第2半導体チップと同じ回路機能を有し、同じ向きに搭載された第3半導体チップと、
上記第2半導体チップ及び第3半導体チップのボンディングパッドを上記搭載基板上に形成された対応する電極に対してそれぞれ共通に接続するボンディングワイヤと、
上記搭載基板上の上記第1、第2、第3半導体チップ及びボンディングワイヤを封止する封止体とを備えてなることを特徴とするマルチチップモジュール。 - 請求項1において、
上記第3半導体チップの裏面は、電気絶縁性を有するものであることを特徴とするマルチチップモジュール。 - 請求項2において、
上記第3半導体チップ裏面の電気絶縁性は、第3半導体チップを上記スペーサの表面に固着するダイボンドフィルムにより構成されることを特徴とするマルチチップモジュール。 - 請求項3において、
スペーサは、多結晶シリコンを含むものあることを特徴とするマルチチップモジュール。 - 請求項4において、
上記第2半導体チップは、上記第1半導体チップの表面にダイボンドフィルムにより固着されるものであることを特徴とするマルチチップモジュール。 - 請求項1において、
上記第1半導体チップは、上記第2及び第3半導体チップよりも小さなサイズに形成されるものであることを特徴とするマルチチップモジュール。 - 請求項1において、
上記第3半導体チップの表面には、上記第3半導体チップ表面の上記ボンディングパッドが形成される部分を含む所定エリアを除いた部分に搭載され、チップ表面の周辺部にボンディングパッドが設けられた第4半導体チップを更に有し、
上記第4半導体チップのボンディングパッドは、上記搭載基板上に形成された対応する電極に対してボンディングワイヤにより接続されてなることを特徴とするマルチチップモジュール。 - 請求項7において、
上記第1半導体チップは、電気的に消去が可能とされ、不揮発性メモリセルに記憶情報を記録するメモリチップであり、
上記第2及び第3半導体チップは、ダイナミック型メモリセルに記憶情報を記憶するメモリチップであり、
上記第4チップは、マイクロプロセッサを含む半導体チップであることを特徴とするマルチチップモジュール。 - 請求項7において、
上記第1半導体チップは、上記第4半導体チップよりも多い数の接続電極を有することを特徴とするマルチチップモジュール。 - 請求項9において、
上記第1チップは、マイクロプロセッサを含む半導体チップであり、
上記第2及び第3チップは、ダイナミック型メモリセルに記憶情報を記憶するメモリチップであり、
上記第4チップは、電気的に消去が可能とされ、不揮発性メモリセルに記憶情報を記録するメモリチップであることを特徴とするマルチチップモジュール。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP2008539588A (ja) * | 2005-04-27 | 2008-11-13 | スパンジョン・リミテッド・ライアビリティ・カンパニー | マルチチップモジュールおよび製造方法 |
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US12002788B2 (en) | 2019-04-15 | 2024-06-04 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100401020B1 (ko) * | 2001-03-09 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지 |
US7518223B2 (en) * | 2001-08-24 | 2009-04-14 | Micron Technology, Inc. | Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer |
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US7301242B2 (en) | 2004-11-04 | 2007-11-27 | Tabula, Inc. | Programmable system in package |
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US8201124B1 (en) | 2005-03-15 | 2012-06-12 | Tabula, Inc. | System in package and method of creating system in package |
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US8198713B2 (en) * | 2007-07-13 | 2012-06-12 | Infineon Technologies Ag | Semiconductor wafer structure |
US20090199277A1 (en) * | 2008-01-31 | 2009-08-06 | Norman James M | Credential arrangement in single-sign-on environment |
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US10002653B2 (en) | 2014-10-28 | 2018-06-19 | Nxp Usa, Inc. | Die stack address bus having a programmable width |
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Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5614766A (en) * | 1991-09-30 | 1997-03-25 | Rohm Co., Ltd. | Semiconductor device with stacked alternate-facing chips |
JPH06224360A (ja) | 1993-01-26 | 1994-08-12 | Hitachi Constr Mach Co Ltd | 半導体装置及びその製造方法 |
US5323060A (en) * | 1993-06-02 | 1994-06-21 | Micron Semiconductor, Inc. | Multichip module having a stacked chip arrangement |
JPH0730051A (ja) * | 1993-07-09 | 1995-01-31 | Fujitsu Ltd | 半導体装置 |
US7166495B2 (en) * | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
JP3565319B2 (ja) * | 1999-04-14 | 2004-09-15 | シャープ株式会社 | 半導体装置及びその製造方法 |
JP2003007963A (ja) | 2001-06-20 | 2003-01-10 | Hitachi Ltd | 半導体記憶装置および製造方法 |
JP4062722B2 (ja) | 2002-01-30 | 2008-03-19 | 日本電気株式会社 | 積層型半導体装置及びその製造方法 |
-
2003
- 2003-11-17 JP JP2003387188A patent/JP4381779B2/ja not_active Expired - Fee Related
-
2004
- 2004-10-25 US US10/971,042 patent/US7009303B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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