CN104054172A - 用于堆叠的半导体装置的中介层 - Google Patents

用于堆叠的半导体装置的中介层 Download PDF

Info

Publication number
CN104054172A
CN104054172A CN201280064251.5A CN201280064251A CN104054172A CN 104054172 A CN104054172 A CN 104054172A CN 201280064251 A CN201280064251 A CN 201280064251A CN 104054172 A CN104054172 A CN 104054172A
Authority
CN
China
Prior art keywords
intermediary layer
die
semiconductor
escapement
electrical connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201280064251.5A
Other languages
English (en)
Inventor
P·吉利厄姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Examine Vincent Zhi Cai Management Co
Mosaid Technologies Inc
Original Assignee
Examine Vincent Zhi Cai Management Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Examine Vincent Zhi Cai Management Co filed Critical Examine Vincent Zhi Cai Management Co
Publication of CN104054172A publication Critical patent/CN104054172A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种半导体装置，包括具有至少一个衬底焊盘的衬底。在衬底上堆叠多个半导体裸片。每个半导体裸片具有位于该裸片的有源表面上的至少一个裸片焊盘。将多个中介层中的每一个安装到对应的一个半导体裸片上。每个中介层具有与至少一个裸片焊盘对准的、穿过该中介层形成的孔。在至少一个裸片焊盘和至少一个衬底焊盘之间的电连接至少部分由中介层形成。该电连接包括至少一个引线接合。

Description

用于堆叠的半导体装置的中介层
相关申请的交叉引用及优先权要求
本申请要求在2011年11月29日提交的、申请号为61/564623的美国临时专利申请的优先权的权益，该美国临时专利申请的内容通过引用被全部包含于此。
技术领域
本发明总的涉及半导体存储装置，并且特别涉及多芯片封装。
背景技术
通常将存储器裸片(die)进行堆叠，以便在(例如标准尺寸的封装内的)衬底的有限区域上增加存储密度。由此产生的堆叠的装置被称为多芯片封装(MCP)。
参考图1，一个典型的半导体装置100具有位于每个裸片104的边缘附近的焊盘(bonding pad)102。可以使用简单的中介层106堆叠和接合这些裸片104以创建足够的空间，用于使接合引线108到达位于另一个裸片104下面的一个裸片104并且将该裸片104电连接到衬底110。
参考图2，诸如NAND闪存的其他半导体装置200可具有沿每个裸片204的单个边缘布置的焊盘202。由于可将裸片204彼此错开或者横向偏置来暴露出焊盘202，并且允许接合引线208接入每个裸片以便电连接到衬底210，因此这完全消除了对中介层的需求。
然而，诸如DDR3的高速DDR DRAM装置具有位于裸片的中心脊(spine)上的焊盘。在这种焊盘配置下，不便于使用上述技术中的任何一个技术，这是因为堆叠中较低的裸片的焊盘会被堆叠中较高的裸片挡住，从而使接合引线无法将焊盘连接到衬底。因此，DRAM装置的存储密度被实际限制为单个芯片的容量。
解决这种缺陷的一个方法是使用硅通孔(TSV)来连接DRAM裸片。然而，该方法需要一个复杂过程来形成TSV，该过程增加了制造成本、添加了制造步骤，并且可能降低成品率。此外，TSV占据了裸片上的区域，这可能需要重新设计裸片以便重新配置存储元件，并且这相应地增加了裸片的尺寸或者减少了裸片的存储容量。因此，该方法不适用于与传统DRAM裸片一起使用。
因此，需要一种用于堆叠DRAM裸片使得可将所有堆叠的裸片连接到公共衬底的方法。
还需要一种用于堆叠半导体裸片并且将该裸片与公共衬底接合，且不要求特定的焊盘布置的方法。
还需要一种易于制造的具有堆叠的DRAM裸片的多芯片封装。
发明内容
本发明的一个目的是解决现有技术的一个或多个缺陷。
本发明的另一个目的是提供具有堆叠的DRAM裸片，以及允许引线接合(wire bonding)到每个裸片中心的焊盘的中介层的多芯片封装。
本发明的另一个目的是提供一种用于堆叠半导体裸片的方法，以及提供到不位于裸片边缘处的焊盘的电连接。
本发明的另一个目的是提供具有与位于半导体裸片中心的焊盘大体对准的开口的中介层，以及提供电迹线，该电迹线提供半导体裸片的焊盘与靠近中介层边缘的焊盘之间的电连接，其中可以方便地将该中介层用引线接合到衬底。
在一个方面，半导体装置包括具有至少一个衬底焊盘的衬底。在所述衬底上堆叠多个半导体裸片。每个半导体裸片具有位于该裸片的有源表面上的至少一个裸片焊盘。多个中介层中的每个中介层被安装到所述半导体裸片中对应的一个半导体裸片上。每个中介层具有穿过该中介层形成的、与所述至少一个裸片焊盘对准的孔。在所述至少一个裸片焊盘和所述至少一个衬底焊盘之间形成电连接。所述电连接至少部分由所述中介层形成。所述电连接包括至少一个引线接合。
在另一方面，将多个间隔装置中的每个间隔装置安装到所述中介层中对应的一个中介层上。
在另一方面，所述多个间隔装置中的每一个间隔装置具有穿过该间隔装置形成的孔。该孔与对应的中介层的孔大体对准。
在另一方面，所述至少一个裸片焊盘是多个裸片焊盘。
在另一方面，所述多个裸片焊盘位于所述半导体裸片的有源表面的中心区域。
在另一方面，沿所述半导体裸片的中心脊布置所述多个裸片焊盘。
在另一方面，每个中介层还包括沿所述孔排列的多个孔焊盘。每个孔焊盘与所述多个裸片焊盘中的一个裸片焊盘相对应。
在另一方面，所述电连接包括在每个孔焊盘和对应的裸片焊盘之间的电连接。
在另一方面，在每个孔焊盘和对应的裸片焊盘之间的电连接是引线接合。
在另一方面，将多个间隔装置中的每个间隔装置安装到所述中介层中对应的一个中介层上。
在另一方面，所述多个间隔装置中的每一个间隔装置具有穿过该间隔装置形成的孔。该孔与对应的中介层的孔和孔焊盘大体对准。
在另一方面，所述电连接还包括将每个孔焊盘连接到沿所述中介层的外边缘排列的多个边焊盘中对应的一个边焊盘的导电迹线。
在另一方面，在所述中介层上形成所述导电迹线。
在另一方面，在所述中介层的内部形成所述导电迹线。
在另一方面，所述电连接还包括在每个边焊盘和对应的衬底焊盘之间的引线接合。
在另一方面，所述电连接还包括在每个孔焊盘和对应的裸片焊盘之间的引线接合。
附图说明
图1是根据第一现有技术实施例的多芯片封装(MCP)的示意侧视图；
图2是根据第二现有技术实施例的多芯片封装(MCP)的示意侧视图；
图3A是根据第一实施例的半导体裸片、中介层和间隔装置(spacer)的俯视图；
图3B是沿线I-I得到的图3的半导体裸片、中介层和间隔装置的截面图；
图4是沿线I-I得到的图3的半导体裸片、中介层和间隔装置的堆叠布置的截面正视图；
图5是根据第一实施例的多芯片封装(MCP)的截面正视图；以及
图6是根据第二实施例的多芯片封装(MCP)的截面正视图。
具体实施方式
参考图3至5，将根据第一实施例来描述堆叠的裸片布置。参考图3，将半导体裸片304示出为DRAM裸片，其可以是高速DDR、DDR2或DDR3裸片，在该裸片304的有源表面(active surface)上具有多个裸片焊盘302。裸片焊盘302允许裸片304的电路与诸如(在图5中示出的)衬底310或者另一个裸片304的外部装置之间的电连接。裸片焊盘302是沿裸片304的中心脊布置的，这是DRAM裸片的典型的布置。然而，应将本发明理解为适用于其他类型的半导体裸片，其中该半导体裸片可具有位于该裸片的有源表面的中心区域上的其他位置的焊盘，因此该焊盘离裸片的边缘太远而不能形成如图2所示的引线接合。还应理解，该裸片焊盘302仅是为了进行说明而示出的，并不用于代表DRAM裸片上的焊盘的数量或者相对大小。
仍参考图3，中介层306具有穿过该中介层形成的孔312。该孔312足够大，使得当将中介层306堆叠到裸片304之上时，可从上面接入裸片焊盘302以进行引线接合(将在下文中更详细地描述)。沿孔312布置了多个孔焊盘314，其与裸片304上的多个裸片焊盘302对应。导电迹线316从每个孔焊盘314延伸到沿中介层306的外边缘布置的对应的边焊盘318。可在中介层306的顶层上或者在中介层306的在该顶层下的内部中形成导电迹线316，并且该导电迹线316提供了每个孔焊盘314和该孔焊盘对应的边焊盘318之间的电连接。中介层306可由适合的印刷电路板材料制成，例如FR4。
可在一个互连层中形成导电迹线316，视情况将其他层用于供电分配、屏蔽或者期望的其他目的。仅示意性地示出了导电迹线316，可以预见的是，取决于期望的应用，导电迹线可具有更复杂的形状或者不均匀的宽度。例如，在任何一端或者两端处导电迹线316可能较宽，以便提供焊盘314、318；并且在中间处导电迹线较窄，以便将传输线路阻抗与通过该导电迹线通信的驱动器和接收器进行适当地匹配。导电迹线316还可以被布置为将信号集中在特定的区域中，而不是在中介层306上均匀分布，例如用于简化(将在下文中描述的)封装衬底上的连接。例如，单个堆叠中的不同的中介层306可具有采用不同布置的边焊盘318，以减少到边焊盘的引线接合连接中的拥塞、将用于类似信号的连接分组到一起、或者缩短整体信号路径。如在标题为“SEMICONDUCTOR MEMORY DEVICE WITHPLURAL MEMORY DIE AND CONTROLLER DIE”的美国专利申请12/967918(该申请通过引用被全部包含于此)中公开的，当封装内的独立总线连接到DRAM的不同组时，这样做是有利的。可以进一步预见的是，可以为中介层306的不只一个边缘提供边焊盘318，在这种情况下可在孔312的相对侧布置一些孔焊盘314，用于经由适当布置的导电迹线316连接到位于中介层306的相对侧的边焊盘318。
仍参考图3，间隔装置320具有穿过该间隔装置形成的孔322。该孔322足够大，使得当将间隔装置320堆叠到中介层306上时，可接入裸片304的裸片焊盘302与中介层306的孔焊盘314以进行引线接合，或者可选地，该孔322足够大到不干扰在裸片304的裸片焊盘302和中介层306的孔焊盘314之间的任何存在的引线接合。间隔装置320可由任何适合的非导电材料制成，如FR4。可选地，间隔装置320可由具有良好导热性的导电材料制成以便允许散热，在该情况下，可向间隔装置320提供薄绝缘涂层，以避免中介层306上的导电迹线短路。如果在中介层306的内部层中形成导电迹线316并且由中介层306的绝缘层保护该导电迹线316，则可以不需要该薄绝缘涂层。
参考图4，可选地，可将裸片304、中介层306和间隔装置320堆叠成子装配件324，用于随后装配到多芯片封装(MCP)300(图5)内。为此，裸片304可以是充分测试的已知的良好裸片，优选地其可以是来自硅晶圆(未示出)的裸片，该硅晶圆的背面已被研磨以使裸片薄至100μm或更小(优选地70μm或更小)，这样可将4或8个裸片304装配到总厚度小于1mm的装置内。接着，将中介层306安装到裸片304的有源表面上，使得孔312与裸片焊盘302对准，从而允许由引线接合机器(未示出)来附接接合引线326，在每个裸片焊盘302和其对应的孔焊盘314之间提供电连接。包括边焊盘318的中介层306的边缘延伸到裸片304的边缘之外，使得当堆叠多个子装配件324来形成图5所示的MCP300时，可将边焊盘318用引线接合到衬底310。如果中介层306在不只一个边缘上具有边焊盘318，则可以设置中介层306的尺寸，使得具有边焊盘318的每条边缘将会延伸到裸片304的边缘之外，从而允许在所装配的MCP300中进行引线接合。在附接接合引线326之前或者之后，将间隔装置320安装到中介层306的上表面之上。间隔装置320中的孔322与中介层306中的孔312大体对准，并且该孔322的尺寸被设置为不干扰接合引线326，或者如果在安装间隔装置320之后形成接合引线，则该孔322的尺寸被设置为不干扰形成接合引线326的过程。间隔装置320可具有与裸片304类似的横向延伸，并且足够小到不会挡住边焊盘318，使得之后可将接合引线328(图5)附接到该边焊盘318，从而形成MCP300。间隔装置320的厚度足以提供接合引线326与在间隔装置320之上安装的裸片304之间的间隙，优选地，还要足够薄到允许合理紧凑装配的MCP300。
参考图5，可通过在衬底310上堆叠任何期望数量的子装配件324来装配MCP300(例如用四个或八个子装配件324)，并且在安装子装配件324时，将每个子装配件324的边焊盘318经由接合引线328电连接到位于衬底310上的衬底焊盘330。可选地，在该堆叠的顶部处的子装配件324可以不具有间隔装置320，以便节省成本或制造步骤，或者减少该堆叠的总的高度。或者，可以通过单独地堆叠每一层，并且在过程中的合适阶段用引线接合这些层来装配MCP300。以这种方式，将第一裸片304堆叠到衬底310上，随后堆叠第一中介层306和第一间隔装置320。在堆叠间隔装置320之前或者之后，将中介装置306用引线接合到该裸片304和衬底310。将第二裸片304堆叠到第一间隔装置320上，接着堆叠第二中介层306和第二间隔装置320，其中将第二中介层306用引线接合到该裸片304和衬底310，并且对于另外的裸片304、中介层306和间隔装置320重复该过程，直到达到期望的堆叠高度，例如四个或八个裸片304。
或者，可使用层的不同分组作为子装配件来形成MCP300，例如，将与其中介层306引线接合的每个裸片304作为子装配件进行安装，将中介层306用引线接合到衬底310，并且接着在中介层306上安装间隔装置320，之后将下一个裸片304和中介层306的子装配件安装到间隔装置320的顶部。可重复该过程直到达到期望的堆叠高度，例如四个或八个裸片304。
不管装配MCP300的特定方法如何，应理解，通过接合引线326、328以及中介层306的导电迹线316在每个裸片焊盘302和对应的衬底焊盘330之间形成电连接。衬底焊盘330经由衬底310中的导电迹线(未示出)电连接到衬底310的相对侧上的球栅阵列332。通过这种方式，每个裸片304与衬底310电连通，以便经由衬底310的相对侧上的球栅阵列332向外部装置(未示出)发送或者从外部装置接收数据和其他信号。
一经装配，可采用塑料树脂或者其他封装化合物来覆盖MCP300，以通过提供机械支持以及电隔离接合引线来保护MCP300。
参考图6，MCP400包括与图5的MCP300类似的且以类似的方式连接的组件，该组件已被给予类似的附图标记，并且将不再详细描述。可以采用与图5的MCP300类似的方式来装配MCP400，或者通过堆叠单独的半导体裸片404、中介层406和间隔装置420，或者通过堆叠子装配件424或它们的一些适当的组合，并且附接必要的接合引线。然而，与图5的MCP300不同，MCP400的半导体裸片404并不直接连接到球栅阵列432来与外部电路通信。而是，衬底焊盘430经由衬底410中的导电迹线(未示出)连接到另一组衬底焊盘434。衬底焊盘434经由接合引线436连接到桥芯片440上的对应的焊盘438。例如，如美国专利申请12/967918中公开的(该美国专利申请通过引用被全部包含于此)，还将桥芯片440用引线接合到或者以其他方式电连接到衬底410以与球栅阵列432通信，并且该桥芯片440提供外部电路和裸片404之间的接口。桥芯片440通常远小于裸片404，在这种情况下，该桥芯片440可以安装在顶部中介层406的一侧上，或者顶部间隔装置420(如果提供了顶部间隔装置420)的一侧上，而不会干扰接合引线426。会与顶部中介层406的孔312重叠的足够大的桥芯片440可能需要被安装到顶部中介层406上的间隔装置420，以便允许为接合引线426腾出空间。美国专利申请12/967918中公开了经由MCP400中的桥芯片440进行接口连接的一些优点，并且该优点包括减少的外部总线的电负载。
应理解，本文描述的结构可提供多个优点，例如在单个封装中使用传统的大容量DDR裸片、使用传统的接合引线代替更复杂的TSV连接、节省与TSV相关联的附加的处理步骤，以及不需要独立的主和从裸片来实现多裸片布置。
对本发明的上述实施例的修改和改进对于本领域技术人员来说可能是显而易见的。上文的描述意在提供示例而非用于限制。

Claims (16)

1.一种半导体装置，包括：
具有至少一个衬底焊盘的衬底；
在所述衬底上堆叠的多个半导体裸片，每个半导体裸片具有位于该裸片的有源表面上的至少一个裸片焊盘；
多个中介层，每个中介层被安装到所述半导体裸片中对应的一个半导体裸片上，每个中介层具有穿过该中介层形成的且与所述至少一个裸片焊盘对准的孔；以及
在所述至少一个裸片焊盘和所述至少一个衬底焊盘之间的电连接，所述电连接至少部分由所述中介层形成，所述电连接包括至少一个引线接合。
2.根据权利要求1所述的半导体装置，还包括：
多个间隔装置，每个间隔装置被安装到所述中介层中对应的一个中介层上。
3.根据权利要求2所述的半导体装置，其中所述多个间隔装置中的每一个间隔装置具有穿过该间隔装置形成的孔，该孔与对应的中介层的孔大体对准。
4.根据权利要求1所述的半导体装置，其中所述至少一个裸片焊盘是多个裸片焊盘。
5.根据权利要求4所述的半导体装置，其中所述多个裸片焊盘位于所述半导体裸片的有源表面的中心区域。
6.根据权利要求5所述的半导体装置，其中沿所述半导体裸片的中心脊布置所述多个裸片焊盘。
7.根据权利要求4所述的半导体装置，其中每个中介层还包括沿所述孔排列的多个孔焊盘，每个孔焊盘与所述多个裸片焊盘中的一个裸片焊盘相对应。
8.根据权利要求7所述的半导体装置，其中所述电连接包括在每个孔焊盘和对应的裸片焊盘之间的电连接。
9.根据权利要求8所述的半导体装置，其中在每个孔焊盘和对应的裸片焊盘之间的电连接是引线接合。
10.根据权利要求9所述的半导体装置，还包括多个间隔装置，每个间隔装置被安装到所述中介层中对应的一个中介层上。
11.根据权利要求10所述的半导体装置，其中所述多个间隔装置中的每一个间隔装置具有穿过该间隔装置形成的孔，该孔与对应的中介层的孔和孔焊盘大体对准。
12.根据权利要求9所述的半导体装置，其中所述电连接还包括将每个孔焊盘连接到沿所述中介层的外边缘排列的多个边焊盘中对应的一个边焊盘的导电迹线。
13.根据权利要求12所述的半导体装置，其中在所述中介层上形成所述导电迹线。
14.根据权利要求12所述的半导体装置，其中在所述中介层的内部形成所述导电迹线。
15.根据权利要求12所述的半导体装置，其中所述电连接还包括在每个边焊盘和对应的衬底焊盘之间的引线接合。
16.根据权利要求15所述的半导体装置，其中所述电连接还包括在每个孔焊盘和对应的裸片焊盘之间的引线接合。
CN201280064251.5A 2011-11-29 2012-11-28 用于堆叠的半导体装置的中介层 Pending CN104054172A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161564623P 2011-11-29 2011-11-29
US61/564,623 2011-11-29
PCT/CA2012/001088 WO2013078538A1 (en) 2011-11-29 2012-11-28 Interposer for stacked semiconductor devices

Publications (1)

Publication Number Publication Date
CN104054172A true CN104054172A (zh) 2014-09-17

Family

ID=48466098

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280064251.5A Pending CN104054172A (zh) 2011-11-29 2012-11-28 用于堆叠的半导体装置的中介层

Country Status (7)

Country Link
US (1) US8836148B2 (zh)
EP (1) EP2795673A4 (zh)
JP (1) JP2014533895A (zh)
KR (1) KR20140116079A (zh)
CN (1) CN104054172A (zh)
TW (1) TW201342569A (zh)
WO (1) WO2013078538A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550565A (zh) * 2018-04-04 2018-09-18 华进半导体封装先导技术研发中心有限公司 芯片封装结构及封装方法
CN110491872A (zh) * 2018-05-14 2019-11-22 美光科技公司 半导体裸片组合件、封装和***以及操作方法
CN114258588A (zh) * 2019-08-28 2022-03-29 美光科技公司 包含线接合和直接芯片附接的堆叠裸片封装以及相关方法、装置和设备
CN115547404A (zh) * 2022-11-30 2022-12-30 普赛微科技(杭州)有限公司 用于先进封装mram存储器的测试架构及方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987009B1 (en) 2013-01-15 2015-03-24 Xilinx, Inc. Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
US9710173B2 (en) * 2014-05-20 2017-07-18 Micron Technology, Inc. Read cache memory with DRAM class promotion
US11610844B2 (en) * 2017-10-11 2023-03-21 Octavo Systems Llc High performance module for SiP
KR102365682B1 (ko) * 2017-11-13 2022-02-21 삼성전자주식회사 반도체 패키지
KR102591697B1 (ko) * 2019-03-06 2023-10-20 에스케이하이닉스 주식회사 하이브리드 와이어 본딩 구조를 포함한 스택 패키지
US11309301B2 (en) 2020-05-28 2022-04-19 Sandisk Technologies Llc Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same
US11335671B2 (en) 2020-05-28 2022-05-17 Sandisk Technologies Llc Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278616B1 (en) * 1998-07-07 2001-08-21 Texas Instruments Incorporated Modifying memory device organization in high density packages
US20040113256A1 (en) * 2002-11-04 2004-06-17 Jochen Thomas Stack arrangement of a memory module
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
US7619305B2 (en) * 2007-08-15 2009-11-17 Powertech Technology Inc. Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6984545B2 (en) * 2002-07-22 2006-01-10 Micron Technology, Inc. Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
JP4381779B2 (ja) * 2003-11-17 2009-12-09 株式会社ルネサステクノロジ マルチチップモジュール
US7492039B2 (en) 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
JP5168284B2 (ja) 2007-08-24 2013-03-21 日本電気株式会社 スペーサ及びその製造方法
JP5628470B2 (ja) * 2007-12-04 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US8035210B2 (en) * 2007-12-28 2011-10-11 Stats Chippac Ltd. Integrated circuit package system with interposer
US9385055B2 (en) 2010-08-20 2016-07-05 Ati Technologies Ulc Stacked semiconductor chips with thermal management
US20120199960A1 (en) 2011-02-07 2012-08-09 Texas Instruments Incorporated Wire bonding for interconnection between interposer and flip chip die
US8409917B2 (en) * 2011-03-22 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with an interposer substrate and method of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278616B1 (en) * 1998-07-07 2001-08-21 Texas Instruments Incorporated Modifying memory device organization in high density packages
US20040113256A1 (en) * 2002-11-04 2004-06-17 Jochen Thomas Stack arrangement of a memory module
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
US7619305B2 (en) * 2007-08-15 2009-11-17 Powertech Technology Inc. Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550565A (zh) * 2018-04-04 2018-09-18 华进半导体封装先导技术研发中心有限公司 芯片封装结构及封装方法
CN110491872A (zh) * 2018-05-14 2019-11-22 美光科技公司 半导体裸片组合件、封装和***以及操作方法
CN110491872B (zh) * 2018-05-14 2021-03-30 美光科技公司 半导体裸片组合件、封装和***以及操作方法
US11380665B2 (en) 2018-05-14 2022-07-05 Micron Technology, Inc. Semiconductor dice assemblies, packages and systems, and methods of operation
CN114258588A (zh) * 2019-08-28 2022-03-29 美光科技公司 包含线接合和直接芯片附接的堆叠裸片封装以及相关方法、装置和设备
US11705432B2 (en) 2019-08-28 2023-07-18 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices
CN115547404A (zh) * 2022-11-30 2022-12-30 普赛微科技(杭州)有限公司 用于先进封装mram存储器的测试架构及方法

Also Published As

Publication number Publication date
JP2014533895A (ja) 2014-12-15
EP2795673A1 (en) 2014-10-29
EP2795673A4 (en) 2015-06-03
KR20140116079A (ko) 2014-10-01
US8836148B2 (en) 2014-09-16
TW201342569A (zh) 2013-10-16
US20130134607A1 (en) 2013-05-30
WO2013078538A1 (en) 2013-06-06

Similar Documents

Publication Publication Date Title
CN104054172A (zh) 用于堆叠的半导体装置的中介层
US9502345B2 (en) Ball-grid-array package, electronic system and method of manufacture
KR101329355B1 (ko) 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
CN102867821B (zh) 半导体器件
US7297574B2 (en) Multi-chip device and method for producing a multi-chip device
US7321164B2 (en) Stack structure with semiconductor chip embedded in carrier
CN101355067B (zh) 多芯片模块的改进的电连接
KR101766725B1 (ko) 칩 스택을 구비하는 반도체 장치, 반도체 시스템 및 그 제조 방법
US9899347B1 (en) Wire bonded wide I/O semiconductor device
KR100813625B1 (ko) 반도체 소자 패키지
US20070222050A1 (en) Stack package utilizing through vias and re-distribution lines
US20130161836A1 (en) Semiconductor package having interposer comprising a plurality of segments
US20110089575A1 (en) Multichip package and method of manufacturing the same
US7888808B2 (en) System in package integrating a plurality of semiconductor chips
CN106298731B (zh) 电路板和包括该电路板的半导体封装件
US20200402959A1 (en) Stacked semiconductor package having an interposer
CN102130025B (zh) 晶片及其处理方法和制造半导体装置的方法
JP2013131557A (ja) 半導体装置およびその製造方法
CN103229293A (zh) 半导体芯片封装、半导体模块及其制造方法
CN102790042A (zh) 半导体芯片堆叠构造
CN106847712B (zh) 一种扇出型晶圆级封装结构及其制作方法
CN103383940A (zh) 半导体封装件及其制法
TWI529918B (zh) 半導體記憶卡
JP2011222807A (ja) 半導体装置
KR102671078B1 (ko) 팬 아웃 서브 패키지를 포함한 스택 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20140917