JP4332567B2 - 半導体装置の製造方法及び実装方法 - Google Patents
半導体装置の製造方法及び実装方法 Download PDFInfo
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- JP4332567B2 JP4332567B2 JP2007081852A JP2007081852A JP4332567B2 JP 4332567 B2 JP4332567 B2 JP 4332567B2 JP 2007081852 A JP2007081852 A JP 2007081852A JP 2007081852 A JP2007081852 A JP 2007081852A JP 4332567 B2 JP4332567 B2 JP 4332567B2
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Description
この半導体装置は、下段の半導体素子101,102が、その回路面が多層回路基板200に向き合うようにフェイスダウン実装され、上段の半導体素子103が2つの半導体素子101,102にまたがって搭載されている。半導体素子103は、回路面が半導体素子101,102と向き合うようにフェイスダウン実装されている。
本発明の他の半導体装置の製造方法は、中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、前記主配線基板の開口部に樹脂またはオイルの熱伝導材を充填する処理と、金属製の封止板で前記主配線基板の開口部を覆う処理とを、順次行うことを特徴とする。
本発明の半導体装置の実装方法は、前記発明の半導体装置の製造方法により製造された半導体装置を、前記外部端子を実装基板の表面に設けられた配線パターンに接続すると共に前記金属製の封止板を該実装基板の表面に設けられたアース配線に半田を介して接続することにより、該実装基板に実装することを特徴とする。
この半導体装置は、ASIC(Application Specified IC)やマイクロコントローラ等の制御用LSIとメモリ等の汎用LSIを組み合わせて1つのパッケージにまとめたSIP(System in Package)構造の半導体装置である。
中継配線基板2の上に、マイクロバンプ3を用いてASICチップ1aとメモリチップ1bをフリップチップ接続する(図3a)。
フリップチップ接続したASICチップ1a及びメモリチップ1bと中継配線基板2の間に、アンダーフィル樹脂4を充填する(図3b)。
中央部に中継配線基板2が丁度収まるような開口部Hが設けられ、この開口部Hの周囲に設けられた段差部Sと表面の間に配線が施され、かつ裏面に放熱板5が貼り付けられたBGA基板10を準備する。そして、このBGA基板10の開口部Hの放熱板5の内側に、工程2で組み立てた中継配線基板2を、熱伝導性のある接着材6で接着して搭載する(図3c)。
中継配線基板2の周辺部に引き出されたアルミ電極と、BGA基板10の段差部Sに引き出された配線の間を、ボンディング・ワイヤ7で電気的に接続する。更に、中継配線基板2にフリップチップ接続されたASICチップ1a及びメモリチップ1bの上に、熱伝導材9を適量塗布する(図3d)。
BGA基板10の開口部Hを覆うように、金属キャップ8を被せ、周囲を接着する。このとき、金属キャップ8とASICチップ1a及びメモリチップ1bの間が、熱伝導材9で充填されるように、工程4で塗布する熱伝導材の量を設定しておく必要がある。
(1) 中継配線基板2に搭載する半導体チップは、ASICやメモリに限定されない。また、個数も2個に限定されない。
(2) パッケージの主要部としてBGA基板10を使用した半導体装置を例示したが、パッケージの主配線基板はBGA基板に限定するものではない。
(3) 実施例2のように開口部Hに高熱伝導性の樹脂またはオイル9Aを充填する場合は、フリップチップ接続したASICチップ1a及びメモリチップ1bと中継配線基板2の間に、アンダーフィル樹脂4を充填する必要は無い。
1b メモリチップ
2 中継配線基板
3 マイクロバンプ
4 アンダーフィル樹脂
5 放熱板
6 接着材
7 ボンディング・ワイヤ
8 金属キャップ
9 熱伝導材
9A 樹脂またはオイル
10 BGA基板
11 外部端子
H 開口部
S 段差部
Claims (6)
- 中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、
前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、
前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、
前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、
前記複数の半導体チップの裏面に熱伝導材を塗布する処理と、
前記熱伝導材を介して前記複数の半導体チップと接続するように、金属製の封止板で前記主配線基板の開口部を覆う処理とを、
順次行うことを特徴とする半導体装置の製造方法。 - 中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、
前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、
前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、
前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、
前記主配線基板の開口部に樹脂またはオイルの熱伝導材を充填する処理と、
金属製の封止板で前記主配線基板の開口部を覆う処理とを、
順次行うことを特徴とする半導体装置の製造方法。 - 前記主配線基板は、前記開口部内に該主配線基板の前記表面とは異なる高さの段差部を有し、かつ該段差部上には前記外部端子と電気的に接続する配線が形成されており、
前記段差部上に形成された前記配線と前記中継配線基板とを、前記ボンディング・ワイヤにより電気的に接続することを特徴とする請求項1または2記載の半導体装置の製造方法。 - 前記中継配線基板は、表面に配線が形成されたシリコン基板であることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置の製造方法。
- 前記複数の半導体チップは、2個の半導体チップであり、
一方の半導体チップはASICチップであり、他方の半導体チップはメモリチップであることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法により製造された半導体装置を、前記外部端子を実装基板の表面に設けられた配線パターンに接続すると共に前記金属製の封止板を該実装基板の表面に設けられたアース配線に半田を介して接続することにより、該実装基板に実装することを特徴とする半導体装置の実装方法。
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JP2010161184A (ja) * | 2009-01-08 | 2010-07-22 | Hitachi Ltd | 半導体装置 |
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TWI408310B (zh) * | 2009-09-29 | 2013-09-11 | Liang Meng Plastic Share Co Ltd | 照明裝置及其製造方法 |
US8378480B2 (en) * | 2010-03-04 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy wafers in 3DIC package assemblies |
DE102010026344A1 (de) * | 2010-07-07 | 2012-01-12 | Osram Opto Semiconductors Gmbh | Leuchtdiode |
DE102010050395A1 (de) * | 2010-11-03 | 2012-05-03 | Emitec Gesellschaft Für Emissionstechnologie Mbh | Thermoelektrisches Modul für einen thermoelektrischen Generator eines Fahrzeugs |
JP2012109307A (ja) * | 2010-11-15 | 2012-06-07 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP5924110B2 (ja) * | 2012-05-11 | 2016-05-25 | 株式会社ソシオネクスト | 半導体装置、半導体装置モジュールおよび半導体装置の製造方法 |
US10008475B2 (en) * | 2012-09-27 | 2018-06-26 | Intel Corporation | Stacked-die including a die in a package substrate |
US9564958B2 (en) | 2013-08-08 | 2017-02-07 | Intel IP Corporation | Power saving mode optimizations and related procedures |
ES2716903T3 (es) | 2013-08-08 | 2019-06-17 | Intel Ip Corp | Método, aparato y sistema para ajuste de inclinación hacia abajo eléctrica en un sistema de múltiple entrada múltiple salida |
JP2015220291A (ja) * | 2014-05-15 | 2015-12-07 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
US9609739B2 (en) | 2015-03-10 | 2017-03-28 | Kabushiki Kaisha Toshiba | Electronic device |
JP2017022352A (ja) | 2015-07-15 | 2017-01-26 | 富士通株式会社 | 半導体装置 |
US9781819B2 (en) * | 2015-07-31 | 2017-10-03 | Laird Technologies, Inc. | Multifunctional components for electronic devices and related methods of providing thermal management and board level shielding |
JP2018037520A (ja) | 2016-08-31 | 2018-03-08 | 富士通株式会社 | 半導体装置、電子装置、半導体装置の製造方法及び電子装置の製造方法 |
JP6880777B2 (ja) * | 2017-01-27 | 2021-06-02 | 富士通株式会社 | 光モジュール |
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US11404394B2 (en) * | 2019-09-09 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure with integrated device integrated beneath the semiconductor chip |
TWI757864B (zh) | 2019-09-09 | 2022-03-11 | 台灣積體電路製造股份有限公司 | 封裝結構及其形成方法 |
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JP2695175B2 (ja) * | 1988-01-29 | 1997-12-24 | 株式会社日立製作所 | 半導体装置の製造方法 |
JP2591499B2 (ja) * | 1994-10-21 | 1997-03-19 | 日本電気株式会社 | 半導体装置 |
JP2001110928A (ja) * | 1999-10-04 | 2001-04-20 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法 |
JP3910391B2 (ja) | 2001-09-04 | 2007-04-25 | 株式会社ルネサステクノロジ | 積層型半導体装置 |
TW582100B (en) * | 2002-05-30 | 2004-04-01 | Fujitsu Ltd | Semiconductor device having a heat spreader exposed from a seal resin |
JP2005175423A (ja) * | 2003-11-18 | 2005-06-30 | Denso Corp | 半導体パッケージ |
US7786591B2 (en) * | 2004-09-29 | 2010-08-31 | Broadcom Corporation | Die down ball grid array package |
US7271479B2 (en) * | 2004-11-03 | 2007-09-18 | Broadcom Corporation | Flip chip package including a non-planar heat spreader and method of making the same |
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