JP2000036511A - 電子部品の製造方法 - Google Patents

電子部品の製造方法

Info

Publication number
JP2000036511A
JP2000036511A JP11187336A JP18733699A JP2000036511A JP 2000036511 A JP2000036511 A JP 2000036511A JP 11187336 A JP11187336 A JP 11187336A JP 18733699 A JP18733699 A JP 18733699A JP 2000036511 A JP2000036511 A JP 2000036511A
Authority
JP
Japan
Prior art keywords
wire
layer
solder
metal layer
solderable metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11187336A
Other languages
English (en)
Other versions
JP4766725B2 (ja
Inventor
K Fauty Joseph
ヨセフ・ケイ・ファウティ
Jr James P Letterman
ジェームス・ピー・レターマン，ジュニア
J Sedon Michael
マイケル・ジェイ・セドン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JP2000036511A publication Critical patent/JP2000036511A/ja
Application granted granted Critical
Publication of JP4766725B2 publication Critical patent/JP4766725B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004—Wire welding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/16—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas
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Abstract

(57)【要約】 【課題】 大電力用途における使用に適し、オン抵抗が
小さく、しかも生産性を向上させる電子部品の製造方法
を提供する。 【解決手段】 電子部品の製造方法は、基板（１０１）
を用意する段階、基板（１０１）上に半導体素子を形成
する段階、基板（１０１）上に金属層（１０７）を堆積
し、半導体素子に電気的に結合する段階、はんだの層
（１０８）を金属層上に堆積する段階、およびワイヤ
（１０９）を金属層（１０７）にワイヤ・ボンドする段
階を含む。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、一般的に、電子回
路に関し、更に特定すれば、電子部品および製造方法に
関するものである。
【０００２】
【従来の技術】半導体素子をリードフレームに電気的に
接続するために、ウェッジ・ボンド・アルミニウム・ワ
イヤ・ボンド(wedge bonded aluminum wire bond)が用
いられている。大電力素子では、アルミニウム・ワイヤ
・ボンドの直径は、典型的に、０．１ないし０．７ミリ
メートルとし、大電流搬送能力を備えている。しかしな
がら、アルミニウム・ワイヤを用いる素子は、銅ワイヤ
と比較すると、オン抵抗が高く、オン抵抗が高い程、素
子の電気的性能が低下する。更に、導電率を高めるため
には、１つ以上のアルミニウム・ワイヤをボンディング
・パッドにボンドしなければならないか、あるいは多数
のボンドを同じワイヤで作らなければならない。しかし
ながら、これら余分な製造工程は、生産性低下を招く。
【０００３】銅ワイヤの使用により、アルミニウム・ワ
イヤよりもオン抵抗が減少し、素子の電気的性能が向上
するが、銅ワイヤを使用すると、素子の生産性が低下す
る。即ち、大きな直径の銅ワイヤは、半導体基板または
それを覆う誘電体層にクラックまたはクレータを形成し
なくてはボンディング・パッドにボンドすることができ
ず、素子に損傷を与えることになる。
【０００４】
【発明が解決しようとする課題】したがって、大電力用
途における使用に適し、オン抵抗が小さく、しかも生産
性を向上させる電子部品を製造する、改良された製造方
法が必要とされている。
【０００５】
【発明の実施の形態】はじめに、図示の簡略化および明
確化のため、図面内のエレメントは必ずしも同じ拡縮率
で描かれている訳ではなく、異なる図における同一の参
照番号は、同一のエレメントを示すものとする。
【０００６】図１は、電子部品１００の部分概略図を示
す。部品１００は、基板１０１，基板１０１上にある電
気絶縁層１０３，層１０３上にある導電層１０４，１０
５，１０６，１０７，１０８，および層１０７，１０８
にボンドされたワイヤ１０９を含む。基板１０１は、半
導体素子を支持する。半導体素子は、図１ではエレメン
ト１０２によって全体的に示されており、ダイオード，
トランジスタ，集積回路等とすることができる。したが
って、基板１０１は、半導体材料で構成することがで
き、更に半導体素子の異なる部分の適正な電気配線およ
び分離のために、追加の電気絶縁層および導電層を含む
ことができる。
【０００７】層１０３は、例えば、二酸化シリコンおよ
び窒化シリコンから成る単一層または複数の層とするこ
とができる。層１０３は、基板１０１の部分を、上に位
置する導電層１０４，１０５，１０６，０１７，１０７
から電気的に分離する。層１０３は、ビア（図１には示
されていない）を有し、これを通じて上に位置する層１
０４，１０５，１０６，１０７，１０８を基板１０１の
他の部分および半導体素子に電気的に結合する。
【０００８】層１０４，１０５，１０６，１０７，１０
８は、部品１００のボンディング・パッドを形成する。
層１０４，１０５，１０６，１０７，１０８は、順次層
１０３上に配置または堆積され、半導体素子の上に位置
することができる。層１０４，１０６はオプションの接
着またはバリア層であり、層１０５は相互接続層であ
り、層１０７ははんだ可能メタライゼーション層であ
り、層１０８ははんだ層である。一例として、層１０
４，１０６は、チタン・タングステン，窒化チタン，窒
化チタン・タングステン，クロム等で作ることができ
る。追加の例として、層１０５は、銅，アルミニウム，
アルミニウム・シリコン，アルミニウム銅，アルミニウ
ム・シリコン銅等で作ることができる。更に、層１０７
は、例えば、（１）チタン，ニッケル，および銀（２）
無電解ニッケルおよび浸漬金、（３）クロム，ニッケ
ル，および銀（４）スパッタリングによる銅およびめっ
きした銅、（５）スパッタリングによる銅，無電解ニッ
ケル，および浸漬金、等のように、複数の層で作ること
ができる。層１０８は、例えば、９５％鉛および５％
錫，または４０％鉛および６０％錫のような、いずれか
の鉛系、錫系、または金系はんだを含むが、これらには
限定されない、適切なはんだで構成することができる。
部品１００の一体性および信頼性を維持するためには、
層１０８の変形温度即ち融点は、部品１００の最も高い
動作温度よりも少なくとも約１０℃高くなければならな
い。
【０００９】ワイヤ１０９の一端を、コンタクト層１０
８にワイヤ・ボンドする。ワイヤ１０９は、大電力用途
における使用に適することが好ましい。したがって、ワ
イヤ１０９の直径は、約０．１ミリメートル以上と大き
くすることが好ましい。更に、部品１００のオン抵抗を
小さくするために、ワイヤ１０９は、アルミニウムの代
わりに銅で構成することができる。何故なら、銅の抵抗
率はアルミニウムよりも約３５パーセント低いからであ
る。好ましくは、ワイヤ１０９は本質的に銅から成る。
また、ワイヤ１０９の銅は、完全にアニールするかある
いは過剰アニール(over anneal)し、以下に説明する理
由のために、ワイヤ１０９の剛性が大きすぎないよう
に、即ち、硬すぎることがないようにすることが好まし
い。ワイヤ１０９は、銅合金で構成することができる
が、同じ理由により、合金は純粋な銅よりも小さな剛性
であることが好ましい。
【００１０】図２は、図１の部品１００の製造方法２０
０を纏めたものである。概略的に、方法２００は、自動
ワイヤ・ボンディング・プロセスにおいてはんだを用い
る。方法２００は、図１の基板１０１のような基板を用
意する工程２０１を含む。方法は、工程２０２に進み、
図１のエレメント１０２のような半導体素子を基板内に
形成する。次に、工程２０３において、図１の層１０
４，１０５，１０６のような少なくとも１つの金属層
を、基板および半導体素子上に堆積する。次に、工程２
０４において、図１の層１０７のようなはんだ可能金属
層（はんだ付けが可能な金属層）を、はんだ不可能金属
層上に堆積する。
【００１１】続いて、方法２００は工程２０５に進み、
図１のワイヤ１０９のようなワイヤを、はんだ層の直下
にあるはんだ可能金属層にワイヤ・ボンドする。工程２
０５については、以下で図３において更に詳しく説明す
る。次に、工程２０６において、ワイヤの対向端を異な
る金属層にボンド（結合）する。好適実施例では、工程
２０５を実行する前に、工程２０１の基板をリードフレ
ームのフラグ上に取り付ける。工程２０６の異なる金属
層とは、リードフレームのリードである。
【００１２】図３は、図２の方法２００における工程２
０５の要点を更に詳しく示す。図３に示すように、工程
２０５は、ワイヤをはんだ可能金属層にワイヤ・ボンド
する際に、２つの可能な経路に分岐する。２つの分岐路
の各々では、異なるシーケンスで、はんだ可能金属層上
にはんだ層を堆積し、ワイヤをはんだ可能金属層に合わ
せる(tack)。以下で更に詳しく説明するが、はんだ層
は、電子部品の電気的性能を向上させ、しかもワイヤと
はんだ可能金属層との間のボンドの機械的強度を高め
る。
【００１３】図３の工程２０５の左側の分岐路は、工程
３０１を含む。工程３０１では、図１の層１０８のよう
なはんだ層を、はんだ可能金属層上に堆積する。一例と
して、はんだ層の厚さは、約２５マイクロメートルとす
ることができる。次に、図３の工程２０５の左側の分岐
路は工程３０２に進み、はんだ層を加熱して、ワイヤを
はんだ可能金属層に合わせる。工程３０２については、
以下で図４において更に詳しく説明する。
【００１４】図３における工程２０５の右側の分岐路
は、工程３０３を含み、はんだ可能金属層に接触してい
るワイヤの一端に圧力を加え、ワイヤおよびはんだ可能
金属層に超音波を印加することによって、ワイヤをはん
だ可能金属に合わせる。超音波の作用により、ワイヤと
はんだ可能金属層との間に弱い機械的結合を形成する。
工程３０３は、はんだ可能金属層上にいずれのはんだも
配する前に実行する。次に、図３における工程２０５の
右側の分岐路は、工程３０４に進み、はんだ可能金属層
およびワイヤの一端に加熱はんだを投与し、ワイヤの一
端をはんだ可能金属層に更に強力にボンドする。尚、工
程３０３は工程３０４の前に開始するが、工程３０３は
工程３０４の実行の間にも継続することが好ましく、そ
の場合工程３０４は熱音波プロセス(thermosonic proce
ss)となる。
【００１５】右側の分岐路または左側の分岐路のいずれ
かが完了した後、図３における工程２０５は、工程３０
５に進み、硬化したはんだ層の冷却またはその他の方法
による固化を行う。工程３０３の超音波は、はんだが適
正に固化し、ワイヤとはんだ可能金属層との間のボンド
を補強することができるように、工程３０５まで継続さ
せないことが好ましい。しかしながら、工程３０３にお
いてワイヤの一端に加える圧力は、工程３０５の間もワ
イヤの一端に維持しておき、はんだが固化する前に、工
程３０２，３０３のタック・ボンド(tack bond)が破壊
されないことを保証する。続いて、工程３０６において
加えていた圧力を解除し、工程２０５のワイヤ・ボンデ
ィング・プロセスが完了する。
【００１６】図４は、図３の工程３０２の要点を更に詳
しく説明する。図４に示すように、工程３０２は、ワイ
ヤをはんだ可能金属層にワイヤ・ボンドする際に、３つ
の可能な経路に分岐する。３つの分岐路の各々では、異
なるシーケンスで、はんだ層を加熱し、ワイヤをはんだ
可能金属層にタックする。
【００１７】図４における工程３０２の左側の分岐路で
は、ワイヤ・タック工程の前に、はんだ加熱工程を実行
する。即ち、左側の分岐路は、工程４０１を含み、最初
にはんだ層を加熱して、このはんだ層を軟化即ちリフロ
ーさせる。はんだ層を加熱するには、このはんだ層を直
接加熱するか、あるいは下地の基板を介して間接的には
んだ層を加熱することができる。一例として、テープ自
動化ボンディング技法において用いられるものと同様
の、パルス加熱方法(pulse heating method)によって熱
を加えることができる。
【００１８】次に、図４における工程３０２の左側の分
岐路は工程４０２に進み、ワイヤの一端に圧力を加え、
軟化したはんだ層を貫通してワイヤをはんだ可能金属層
に接触させることによって、ワイヤをはんだ可能金属層
にタックする。しかしながら、加える力は、溶融即ち軟
化したはんだ層の表面張力を突破するのに十分な大きさ
でなければならない。また、工程４０２は、ワイヤおよ
びはんだ可能金属層に対する超音波の印加も含む。超音
波の作用により、ワイヤとはんだ可能金属層との間に弱
い機械的ボンドを形成する。工程４０１は工程４０２の
前に開始するが、工程４０１は工程４０２の実行の間も
継続し、工程４０２を熱音波工程とすることが可能であ
る。
【００１９】図４における工程３０２の中央の選択肢
は、工程４０３を含み、ワイヤの一端に圧力を加え、は
んだ層と接触させる。加える圧力は、工程４０２におい
て既に説明したものと同様とする。次に、中央の選択肢
は工程４０４に進み、はんだ層を加熱し、はんだ層の直
下に位置するはんだ可能金属層にワイヤをタックする。
工程４０４では、工程４０３の加圧を継続し、軟化した
はんだ層を貫通してワイヤの一端を下地のはんだ可能金
属に接触させる。また、工程４０４は、工程４０２にお
いて先に説明した超音波プロセスと同様の超音波プロセ
スも含む。したがって、工程４０４は、熱音波工程とな
る。工程４０４では、工程４０１において既に説明した
ようにはんだ層を加熱することができ、あるいはワイヤ
を通じてはんだ層を間接的に加熱することも可能であ
る。
【００２０】図４における工程の右側の分岐路は、工程
４０５を含み、はんだ層の加熱およびワイヤのはんだ可
能金属層へのタックを同時に行う。工程４０５のタッキ
ング技法は、工程４０２，４０４において既に説明した
加圧プロセスおよび超音波プロセスと同様のプロセスを
含むことができる。したがって、工程４０５は、熱音波
工程とすることができる。一例として、同時加熱および
タックは、ワイヤの一端を高熱水素炎で加熱し、次いで
加熱したワイヤをはんだ層に接触させることによって行
うことができる。
【００２１】従来技術の自動ワイヤ・ボンド・プロセス
において銅ワイヤを用いる場合、必要な圧力即ち力の量
は、同じサイズのアルミニウム・ワイヤよりも、少なく
とも２倍大きい。この圧力増大が必要となるのは、銅の
方がアルミニウムよりも硬く、展性がないからである。
しかしながら、圧力増大は、ダイにクラックやクレータ
が形成されることを含む多くの問題を生ずる。尚、問題
はこれに限られる訳ではない。
【００２２】ここに記載する方法および部品においては
んだを用いることにより、従来技術に比較して、低い圧
力をワイヤ・ボンド・プロセスにおいて使用することが
可能となる。実際、はんだを用いた場合、大径のアルミ
ニウム・ワイヤに用いる圧力を、同じサイズの銅ワイヤ
にも用いることが可能となる。大径のアルミニウム・ワ
イヤに用いる圧力は、以前に必要であった銅ワイヤに対
する高い圧力に伴う問題を生ずることはない。一例とし
て、直径０．１ミリメートルの銅ワイヤの場合、はんだ
を用いない場合に３５０グラムの力が必要であるのに対
して、ここに記載する方法は約１５０グラムの力を用い
ることができる。
【００２３】従来技術の自動ワイヤ・ボンド技法は、１
９６０年代始めから一般に使用されているが、はんだを
用いたことは全くない。従来技術の自動ワイヤ・ボンド
技法は、手作業のワイヤはんだ技法に取って代わった。
手作業のワイヤはんだ技法では、ワイヤをボンディング
・パッドにワイヤ・ボンドまたはタックすることができ
なかった。代わりに、ワイヤを適所に保持しボンディン
グ・パッドに接触するためには、ワイヤはんだ技法のみ
が用いられていた。
【００２４】ここに記載するワイヤ・ボンディング・プ
ロセスのタッキング技法は、自動化プロセスであり、好
ましくはウェッジ・ボンディング(wedge bonding)技法
を用い、好ましくはボール・ボンディング技法を用いな
い。ウェッジ・ボンディング技法は、ワイヤの一端即ち
先端を、ボール・ボンディング技法におけるように、ワ
イヤの直径の３倍以上もある直径を有するボールに変形
させることはない。したがって、ウェッジ・ボンディン
グ技法は、より小さなボンディング・パッドとでも用い
ることができ、一層小型化され安価な半導体部品を生産
することが可能となる。
【００２５】工程３０３，４０２，４０４，４０５のタ
ッキング・プロセスは、ワイヤとはんだ可能金属層との
間に弱いボンドを形成する。固化したはんだは、ワイヤ
とはんだ可能金属層との間の機械的ボンドを改善即ち強
化する。更に、はんだは、ワイヤとはんだ可能金属層と
の間の電気的接触面積を広げ、接触面積の拡大によって
オン抵抗が減少し、部品の電気的性能が改善する。半導
体部品の製造コストを削減するためには、図２における
工程２０６のワイヤ・ボンディング・プロセスにははん
だを用いないことが好ましい。
【００２６】以上のように、従来技術の欠点を克服す
る、改善された電子部品および製造方法を提供した。こ
の電子部品は、ここで述べたように、大電力用途に適
し、オン抵抗が小さく、より短いサイクル・タイムで製
造可能である。ここに記載した熱音波ウェッジ・ボンデ
ィング・プロセスは、電子部品のボンド・パッドにはん
だを用いて導電性の高い構造を形成し、電子部品のオン
抵抗を小さくして、半導体部品の電気的特性を改善す
る。ボンド・パッドにおいてはんだを用いることによ
り、更に直径が大きい銅ワイヤの使用が可能となり、オ
ン抵抗が減少し、多数のワイヤやステッチ・ボンディン
グ(stitch bonding)の必要性を排除することも可能とな
る。多数のワイヤやステッチ・ボンディングを不要とす
ることにより、半導体部品を製造するために必要なサイ
クル・タイムが短縮する。また、ウェッジ・ボンディン
グ・プロセスは、従来のボール・ボンディング・プロセ
スと比較すると、基板全体で消費する空間も少なくて済
む。
【００２７】以上、好適実施例を主に参照しながら、本
発明を特定的に示しかつ説明したが、本発明の精神およ
び範囲から逸脱することなく、その形態および詳細には
変更が可能であることは、当業者には認められよう。例
えば、ここに明記した数多くの詳細、例えば、具体的な
寸法や具体的な材料組成は、本発明の理解を容易にする
ために提示したのであって、本発明の範囲を限定するた
めに提示したのではない。一例として、図１における層
１０８は、はんだで構成すると説明したが、他の導電層
または接着層をはんだと交換したり、あるいははんだと
共に使用可能であることは理解されよう。
【００２８】加えて、図１のワイヤ１０９は、アルミニ
ウムで構成されたコアおよび本質的に銅から成る外部コ
ーティング、またはその逆を有することができる。更
に、図１のワイヤ１０９にはんだをコートし、図３の工
程３０１，３０４におけるはんだの堆積を不要とするこ
とも可能である。更にまた、図４における工程４０２，
４０４，４０５で加える圧力を小さくすることができ、
これら同じ工程の超音波を省略し、ワイヤをはんだ可能
金属層にタックしないようにすることも可能である。こ
の実施例では、冷却したはんだが、はんだ可能金属層に
取り付けられたワイヤを保持する。
【００２９】別の例として、図２における工程２０５を
修正し、はんだを除去して、十分な強度でワイヤをはん
だ可能金属層にウェッジ・ボンドまたはタックすれば、
ウェッジ・ボンドが外れることがないように工程２０６
を実行することが可能である。工程２０６の後、ウェッ
ジ・ボンド周囲にはんだを分与および／またはリフロー
し、次いではんだ層を冷却することができる。追加の例
として、図３の工程３０１において、はんだ層に孔を配
し、即ち、穿設し、下地のはんだ可能金属層の一部分を
露出させることができる。次いで、工程４０３，４０５
を修正し、この孔にワイヤを挿入し、はんだ層に接触す
ることなく、露出したはんだ可能金属層に直接ワイヤを
接触させることができる。工程４０４，４０５の間、は
んだ層はリフローし、ワイヤのコンタクト部分周囲に集
まる(wick)。
【００３０】別の例として、図２における工程２０５を
修正し、はんだ層をその融点未満の温度に加熱し、次い
で十分な強度でワイヤを下地のはんだ可能金属層にウェ
ッジ・ボンドまたはタックすれば、ウェッジ・ボンドが
外れることなく工程２０６を実行することが可能であ
る。図２における工程２０６の後、ウエッジ・ボンド周
囲にはんだをリフローすることができ、次いではんだ層
を冷却することができる。追加の例として、図２の工程
２０６の後、ワイヤおよびはんだ可能金属層上に、追加
のはんだ層を配することができる。この追加のはんだ層
によって、ワイヤとはんだ層との間の接触面積を更に広
げ、電子部品のオン抵抗を更に小さくする。
【図面の簡単な説明】
【図１】本発明による電子部品の一実施例の部分構成
図。
【図２】本発明による図１の電子部品を製造する方法を
纏めた図。
【図３】本発明による図２の方法における一工程の要点
を更に詳細に示す図。
【図４】本発明による図３の工程の一部の要点を更に詳
細に示す図。
【符号の説明】
１００ 電子部品 １０１ 基板 １０２ 半導体素子 １０３ 電気絶縁層 １０４，１０５，１０６，１０７ 導電層 １０８ コンタクト層 １０９ ワイヤ
フロントページの続き (72)発明者 ジェームス・ピー・レターマン，ジュニア アメリカ合衆国アリゾナ州メサ、サウス・ ブライトン・サークル1802 (72)発明者 マイケル・ジェイ・セドン アメリカ合衆国アリゾナ州ギルバート、ノ ース・キングストン・ストリート856

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】電子部品の製造方法であって：銅で構成さ
    れ、約０．１ミリメートル以上の直径を有するワイヤ
    （１０９）を準備する段階；はんだ層（１０８）を与え
    る段階；および前記はんだを加熱しつつ、更に前記ワイ
    ヤに超音波を印加しつつ、前記ワイヤを前記はんだ層に
    ウェッジ・ボンドする段階；から成ることを特徴とする
    方法。
  2. 【請求項２】前記方法は：はんだ付けが可能な金属層を
    与える段階；および前記はんだ付けが可能な金属層上に
    前記はんだ層を堆積する段階であって、該はんだ層が、
    前記金属層の一部分を露出させる孔を有する、段階；を
    更に含み、 前記ウェッジ・ボンドする段階は：前記堆積する段階の
    後、前記金属層の前記一部分に前記ワイヤを接触させる
    段階；および前記はんだをリフローさせ、前記ワイヤの
    コンタクト部分の周囲にはんだを集める段階；を含むこ
    とを特徴とする請求項１記載の方法。
  3. 【請求項３】電子部品の製造方法であって：半導体基板
    （１０１）を用意する段階；前記半導体基板内に半導体
    素子（１０１）を形成する段階；前記半導体基板上に金
    属層（１０７）を配し、前記半導体素子に電気的に結合
    させる段階；前記金属層上にはんだ層（１０８）を堆積
    する段階；および前記堆積する段階の後、前記金属層に
    ワイヤ（１０９）をワイヤ・ボンドする段階；から成る
    ことを特徴とする方法。
  4. 【請求項４】前記ワイヤ・ボンドする段階は：本質的に
    銅から成る前記ワイヤを与える段階；および前記ワイヤ
    を前記はんだ層にウェッジ・ボンドする段階；を更に含
    むことを特徴とする請求項３記載の方法。
  5. 【請求項５】前記堆積する段階は、アルミニウムで構成
    されたはんだ付けが不可能な金属層で構成された金属層
    を与える段階を含み；前記方法は、前記金属層と前記は
    んだ層との間にはんだ付けが可能なメタライゼーション
    層を堆積する段階を含む；ことを特徴とする請求項３記
    載の方法。
JP18733699A 1998-07-01 1999-07-01 電子部品の製造方法 Expired - Lifetime JP4766725B2 (ja)

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US09/108,448 US6164523A (en) 1998-07-01 1998-07-01 Electronic component and method of manufacture

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