FR2968121B1 - Procede de transfert d'une couche a haute temperature - Google Patents
Procede de transfert d'une couche a haute temperatureInfo
- Publication number
- FR2968121B1 FR2968121B1 FR1059903A FR1059903A FR2968121B1 FR 2968121 B1 FR2968121 B1 FR 2968121B1 FR 1059903 A FR1059903 A FR 1059903A FR 1059903 A FR1059903 A FR 1059903A FR 2968121 B1 FR2968121 B1 FR 2968121B1
- Authority
- FR
- France
- Prior art keywords
- layer
- donor substrate
- concentration
- substrate
- transferring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 abstract 9
- 238000002513 implantation Methods 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- -1 silicon ions Chemical class 0.000 abstract 3
- 238000003776 cleavage reaction Methods 0.000 abstract 2
- 230000007017 scission Effects 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1059903A FR2968121B1 (fr) | 2010-11-30 | 2010-11-30 | Procede de transfert d'une couche a haute temperature |
US13/990,539 US9275892B2 (en) | 2010-11-30 | 2011-11-23 | Method of high temperature layer transfer |
PCT/EP2011/070756 WO2012072459A1 (fr) | 2010-11-30 | 2011-11-23 | Procédé de transfert de couche à haute température |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1059903A FR2968121B1 (fr) | 2010-11-30 | 2010-11-30 | Procede de transfert d'une couche a haute temperature |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2968121A1 FR2968121A1 (fr) | 2012-06-01 |
FR2968121B1 true FR2968121B1 (fr) | 2012-12-21 |
Family
ID=43533313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1059903A Active FR2968121B1 (fr) | 2010-11-30 | 2010-11-30 | Procede de transfert d'une couche a haute temperature |
Country Status (3)
Country | Link |
---|---|
US (1) | US9275892B2 (fr) |
FR (1) | FR2968121B1 (fr) |
WO (1) | WO2012072459A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3043248B1 (fr) * | 2015-10-30 | 2017-12-15 | Commissariat Energie Atomique | Procede d'elimination de defauts dans un film semiconducteur comprenant la formation d'une couche de piegeage d'hydrogene |
CN106783725B (zh) * | 2016-12-27 | 2019-09-17 | 上海新傲科技股份有限公司 | 带有绝缘埋层的衬底的制备方法 |
CN107146758B (zh) | 2016-12-27 | 2019-12-13 | 上海新傲科技股份有限公司 | 带有载流子俘获中心的衬底的制备方法 |
FR3076069B1 (fr) * | 2017-12-22 | 2021-11-26 | Commissariat Energie Atomique | Procede de transfert d'une couche utile |
FR3076070B1 (fr) * | 2017-12-22 | 2019-12-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2874455B1 (fr) | 2004-08-19 | 2008-02-08 | Soitec Silicon On Insulator | Traitement thermique avant collage de deux plaquettes |
FR2839385B1 (fr) | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | Procede de decollement de couches de materiau |
US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
JP2005085964A (ja) | 2003-09-08 | 2005-03-31 | Sumitomo Mitsubishi Silicon Corp | 貼り合わせ基板の製造方法 |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
EP1571241A1 (fr) | 2004-03-01 | 2005-09-07 | S.O.I.T.E.C. Silicon on Insulator Technologies | Méthode de fabrication d'un substrat |
FR2867310B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
US20060014363A1 (en) | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
CN100474529C (zh) | 2004-09-16 | 2009-04-01 | S.O.I.泰克绝缘体硅技术公司 | 制造二氧化硅层的方法 |
WO2006037783A1 (fr) | 2004-10-04 | 2006-04-13 | S.O.I.Tec Silicon On Insulator Technologies | Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline |
EP1659623B1 (fr) | 2004-11-19 | 2008-04-16 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Méthode de fabrication d'une plaquette de type germanium sur isolant (GeOI) |
FR2884046B1 (fr) | 2005-03-31 | 2007-06-22 | Soitec Silicon On Insulator | Procede de fabrication de substrat, et substrat |
FR2890489B1 (fr) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant |
FR2902233B1 (fr) * | 2006-06-09 | 2008-10-17 | Soitec Silicon On Insulator | Procede de limitation de diffusion en mode lacunaire dans une heterostructure |
FR2903808B1 (fr) | 2006-07-11 | 2008-11-28 | Soitec Silicon On Insulator | Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique |
US7575988B2 (en) | 2006-07-11 | 2009-08-18 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating a hybrid substrate |
FR2905801B1 (fr) * | 2006-09-12 | 2008-12-05 | Soitec Silicon On Insulator | Procede de transfert d'une couche a haute temperature |
FR2907966B1 (fr) | 2006-10-27 | 2009-01-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat. |
FR2914495B1 (fr) | 2007-03-29 | 2009-10-02 | Soitec Silicon On Insulator | Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. |
FR2918792B1 (fr) | 2007-07-10 | 2010-04-23 | Soitec Silicon On Insulator | Procede de traitement de defauts d'interface dans un substrat. |
FR2926672B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication de couches de materiau epitaxie |
FR2926925B1 (fr) | 2008-01-29 | 2010-06-25 | Soitec Silicon On Insulator | Procede de fabrication d'heterostructures |
FR2934925B1 (fr) | 2008-08-06 | 2011-02-25 | Soitec Silicon On Insulator | Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage. |
EP2200084A1 (fr) | 2008-12-22 | 2010-06-23 | S.O.I. TEC Silicon | Procédé de fabrication d'un capteur d'image rétro-éclairé |
ATE535937T1 (de) | 2009-05-18 | 2011-12-15 | Soitec Silicon On Insulator | Herstellungsverfahren für ein hybrid- halbleitersubstrat |
EP2378549A1 (fr) | 2010-04-06 | 2011-10-19 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de fabrication d'un substrat semi-conducteur |
EP2390907B1 (fr) | 2010-05-25 | 2012-11-14 | Soitec | Structure de tranchée dans une tranche multicouche |
FR2972567B1 (fr) | 2011-03-09 | 2013-03-22 | Soitec Silicon On Insulator | Méthode de formation d'une structure de ge sur iii/v sur isolant |
-
2010
- 2010-11-30 FR FR1059903A patent/FR2968121B1/fr active Active
-
2011
- 2011-11-23 WO PCT/EP2011/070756 patent/WO2012072459A1/fr active Application Filing
- 2011-11-23 US US13/990,539 patent/US9275892B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2012072459A1 (fr) | 2012-06-07 |
FR2968121A1 (fr) | 2012-06-01 |
US20130302970A1 (en) | 2013-11-14 |
US9275892B2 (en) | 2016-03-01 |
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Legal Events
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