SG11201807344RA - Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor–on–insulator type - Google Patents

Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor–on–insulator type

Info

Publication number
SG11201807344RA
SG11201807344RA SG11201807344RA SG11201807344RA SG11201807344RA SG 11201807344R A SG11201807344R A SG 11201807344RA SG 11201807344R A SG11201807344R A SG 11201807344RA SG 11201807344R A SG11201807344R A SG 11201807344RA SG 11201807344R A SG11201807344R A SG 11201807344RA
Authority
SG
Singapore
Prior art keywords
donor substrate
substrate
determining
implanting energy
receiver
Prior art date
Application number
SG11201807344RA
Inventor
Ludovic Ecarnot
Mohamed Nadia Ben
Carine Duret
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201807344RA publication Critical patent/SG11201807344RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

OF THE DISCLOSURE METHOD FOR DETERMINING A SUITABLE IMPLANTING ENERGY IN A DONOR SUBSTRATE AND PROCESS FOR FABRICATING A STRUCTURE OF SEMICONDUCTOR –ON –INSULATOR TYPE 5 The invention concerns a method for determining a suitable implanting energy of at least two atomic species in a donor substrate (30) to create a weakened zone (31) defining a monocrystalline semiconductor layer (32) to be transferred onto a receiver substrate (10), comprising the following steps: 10 (i) forming a dielectric layer on at least one of the donor substrate (30) and the receiver substrate (10); (ii) co –implanting said species in the donor substrate (30); (iii) bonding the donor substrate (30) on the receiver substrate (10); (iv) detaching the donor substrate (30) along the weakened zone (31) to 15 transfer the monocrystalline semiconductor layer (32) and recover the remainder (34) of the donor substrate; (v) inspecting the peripheral crown of the remainder (34) of the donor substrate, or of the receiver substrate (10) on which the monocrystalline semiconductor layer (32) was transferred at step (iv); 20 (vi) if said crown exhibits zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is too high; (vii) if said crown does not exhibit zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is suitable. 25 Fig. 5
SG11201807344RA 2016-03-02 2017-03-02 Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor–on–insulator type SG11201807344RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1651747A FR3048548B1 (en) 2016-03-02 2016-03-02 METHOD FOR DETERMINING APPROPRIATE ENERGY FOR IMPLANTATION IN DONOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR TYPE STRUCTURE ON INSULATION
PCT/FR2017/050471 WO2017149253A1 (en) 2016-03-02 2017-03-02 Method for determining a suitable energy for implantation in a donor substrate and process for fabricating a semiconductor-on-insulator structure

Publications (1)

Publication Number Publication Date
SG11201807344RA true SG11201807344RA (en) 2018-09-27

Family

ID=56322049

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201807344RA SG11201807344RA (en) 2016-03-02 2017-03-02 Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor–on–insulator type

Country Status (7)

Country Link
US (1) US10777447B2 (en)
JP (1) JP6965260B2 (en)
CN (1) CN108701627B (en)
FR (1) FR3048548B1 (en)
SG (1) SG11201807344RA (en)
TW (1) TWI724114B (en)
WO (1) WO2017149253A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
WO2017087393A1 (en) 2015-11-20 2017-05-26 Sunedison Semiconductor Limited Manufacturing method of smoothing a semiconductor surface
FR3063176A1 (en) * 2017-02-17 2018-08-24 Soitec MASKING A ZONE AT THE EDGE OF A DONOR SUBSTRATE DURING AN ION IMPLANTATION STEP
EP4210092A1 (en) 2018-06-08 2023-07-12 GlobalWafers Co., Ltd. Method for transfer of a thin layer of silicon
FR3091620B1 (en) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Layer transfer method with localized reduction of an ability to initiate a fracture

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4304879B2 (en) * 2001-04-06 2009-07-29 信越半導体株式会社 Method for determining the implantation amount of hydrogen ions or rare gas ions
FR2835097B1 (en) * 2002-01-23 2005-10-14 OPTIMIZED METHOD FOR DEFERRING A THIN LAYER OF SILICON CARBIDE ON A RECEPTACLE SUBSTRATE
EP1427001A1 (en) * 2002-12-06 2004-06-09 S.O.I. Tec Silicon on Insulator Technologies S.A. A method for recycling a surface of a substrate using local thinning
JP4492054B2 (en) * 2003-08-28 2010-06-30 株式会社Ｓｕｍｃｏ Reclaimed wafer reclaim processing method and reclaimed wafer
CN101027768B (en) * 2004-09-21 2010-11-03 S.O.I.Tec绝缘体上硅技术公司 Thin layer transfer method wherein a co-implantation step is performed according to conditions avoiding blisters formation and limiting roughness
FR2880988B1 (en) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TREATMENT OF A LAYER IN SI1-yGEy TAKEN
EP1777735A3 (en) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Recycling process of an epitaxial donor wafer
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
US7575988B2 (en) * 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
JP5155536B2 (en) * 2006-07-28 2013-03-06 一般財団法人電力中央研究所 Method for improving the quality of SiC crystal and method for manufacturing SiC semiconductor device
EP2015354A1 (en) * 2007-07-11 2009-01-14 S.O.I.Tec Silicon on Insulator Technologies Method for recycling a substrate, laminated wafer fabricating method and suitable recycled donor substrate
FR2920912B1 (en) 2007-09-12 2010-08-27 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A LAYER TRANSFER STRUCTURE
FR2926672B1 (en) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator PROCESS FOR MANUFACTURING LAYERS OF EPITAXY MATERIAL
FR2971365B1 (en) * 2011-02-08 2013-02-22 Soitec Silicon On Insulator METHOD FOR RECYCLING A SOURCE SUBSTRATE

Also Published As

Publication number Publication date
US20190074215A1 (en) 2019-03-07
CN108701627A (en) 2018-10-23
FR3048548B1 (en) 2018-03-02
WO2017149253A1 (en) 2017-09-08
JP6965260B2 (en) 2021-11-10
TW201735124A (en) 2017-10-01
TWI724114B (en) 2021-04-11
CN108701627B (en) 2023-08-15
US10777447B2 (en) 2020-09-15
JP2019511112A (en) 2019-04-18
FR3048548A1 (en) 2017-09-08

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