FR2926672B1 - Procede de fabrication de couches de materiau epitaxie - Google Patents

Procede de fabrication de couches de materiau epitaxie

Info

Publication number
FR2926672B1
FR2926672B1 FR0850362A FR0850362A FR2926672B1 FR 2926672 B1 FR2926672 B1 FR 2926672B1 FR 0850362 A FR0850362 A FR 0850362A FR 0850362 A FR0850362 A FR 0850362A FR 2926672 B1 FR2926672 B1 FR 2926672B1
Authority
FR
France
Prior art keywords
thin film
layer
support substrate
oxide
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0850362A
Other languages
English (en)
Other versions
FR2926672A1 (fr
Inventor
Bruce Faure
Alexandra Marcovecchio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0850362A priority Critical patent/FR2926672B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to US12/663,696 priority patent/US8153500B2/en
Priority to EP09704183A priority patent/EP2232546B1/fr
Priority to AT09704183T priority patent/ATE522930T1/de
Priority to JP2010543450A priority patent/JP5005097B2/ja
Priority to KR1020107015994A priority patent/KR101568890B1/ko
Priority to PCT/EP2009/050086 priority patent/WO2009092624A1/fr
Priority to CN2009801025906A priority patent/CN101925995B/zh
Publication of FR2926672A1 publication Critical patent/FR2926672A1/fr
Application granted granted Critical
Publication of FR2926672B1 publication Critical patent/FR2926672B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
FR0850362A 2008-01-21 2008-01-21 Procede de fabrication de couches de materiau epitaxie Active FR2926672B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0850362A FR2926672B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication de couches de materiau epitaxie
EP09704183A EP2232546B1 (fr) 2008-01-21 2009-01-06 Procédé de fabrication de couches épitaxiales sur une structure composite
AT09704183T ATE522930T1 (de) 2008-01-21 2009-01-06 Herstellungsverfahren von epitaxial gewachsenen schichten auf einer verbundstruktur
JP2010543450A JP5005097B2 (ja) 2008-01-21 2009-01-06 複合構造上でエピタキシーによって成長する層の製造方法
US12/663,696 US8153500B2 (en) 2008-01-21 2009-01-06 Method of fabricating an epitaxially grown layer on a composite structure
KR1020107015994A KR101568890B1 (ko) 2008-01-21 2009-01-06 컴포지트 구조물 위에 에피택시얼하게 성장된 층을 제조하는 방법
PCT/EP2009/050086 WO2009092624A1 (fr) 2008-01-21 2009-01-06 Procédé de fabrication de couches épitaxiales sur une structure composite
CN2009801025906A CN101925995B (zh) 2008-01-21 2009-01-06 在复合结构上制造外延生长层的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0850362A FR2926672B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication de couches de materiau epitaxie

Publications (2)

Publication Number Publication Date
FR2926672A1 FR2926672A1 (fr) 2009-07-24
FR2926672B1 true FR2926672B1 (fr) 2010-03-26

Family

ID=39772865

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0850362A Active FR2926672B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication de couches de materiau epitaxie

Country Status (8)

Country Link
US (1) US8153500B2 (fr)
EP (1) EP2232546B1 (fr)
JP (1) JP5005097B2 (fr)
KR (1) KR101568890B1 (fr)
CN (1) CN101925995B (fr)
AT (1) ATE522930T1 (fr)
FR (1) FR2926672B1 (fr)
WO (1) WO2009092624A1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
JP2012124473A (ja) * 2010-11-15 2012-06-28 Ngk Insulators Ltd 複合基板及び複合基板の製造方法
FR2968121B1 (fr) * 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
CN102820393A (zh) * 2011-06-10 2012-12-12 光达光电设备科技（嘉兴）有限公司 复合衬底结构及其制作方法
US8927318B2 (en) * 2011-06-14 2015-01-06 International Business Machines Corporation Spalling methods to form multi-junction photovoltaic structure
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8940620B2 (en) * 2011-12-15 2015-01-27 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
US8928037B2 (en) 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
FR3007892B1 (fr) * 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
JP6454606B2 (ja) * 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
FR3048548B1 (fr) * 2016-03-02 2018-03-02 Soitec Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
FR3068508B1 (fr) * 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
EP3989272A1 (fr) * 2017-07-14 2022-04-27 Sunedison Semiconductor Limited Procédé de fabrication d'une structure semi-conducteur sur isolant
JP2019151896A (ja) * 2018-03-05 2019-09-12 日本特殊陶業株式会社 ＳｉＣ部材及びこれからなる基板保持部材並びにこれらの製造方法
FR3079660B1 (fr) * 2018-03-29 2020-04-17 Soitec Procede de transfert d'une couche

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2767604B1 (fr) * 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
JP2000353797A (ja) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp 半導体ウエハおよびその製造方法
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
FR2857982B1 (fr) 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2857983B1 (fr) 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
FR2860249B1 (fr) 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
FR2865574B1 (fr) 2004-01-26 2006-04-07 Soitec Silicon On Insulator Procede de fabrication d'un substrat demontable
JP2005005723A (ja) * 2004-06-25 2005-01-06 Hitachi Cable Ltd 窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハ
WO2006113442A2 (fr) * 2005-04-13 2006-10-26 The Regents Of The University Of California Technique de separation de plaquettes pour la fabrication de plaquettes de (al, in, ga)n autonomes

Also Published As

Publication number Publication date
WO2009092624A1 (fr) 2009-07-30
FR2926672A1 (fr) 2009-07-24
US8153500B2 (en) 2012-04-10
ATE522930T1 (de) 2011-09-15
US20100178749A1 (en) 2010-07-15
KR101568890B1 (ko) 2015-11-12
EP2232546B1 (fr) 2011-08-31
KR20100100980A (ko) 2010-09-15
JP5005097B2 (ja) 2012-08-22
JP2011510507A (ja) 2011-03-31
CN101925995A (zh) 2010-12-22
CN101925995B (zh) 2013-06-19
EP2232546A1 (fr) 2010-09-29

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