EP0483537A2 - Circuit de source de courant - Google Patents

Circuit de source de courant Download PDF

Info

Publication number
EP0483537A2
EP0483537A2 EP91116900A EP91116900A EP0483537A2 EP 0483537 A2 EP0483537 A2 EP 0483537A2 EP 91116900 A EP91116900 A EP 91116900A EP 91116900 A EP91116900 A EP 91116900A EP 0483537 A2 EP0483537 A2 EP 0483537A2
Authority
EP
European Patent Office
Prior art keywords
current
field effect
current source
transistor
effect transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91116900A
Other languages
German (de)
English (en)
Other versions
EP0483537B1 (fr
EP0483537A3 (en
Inventor
Ernst Lingstaedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Conti Temic Microelectronic GmbH
Original Assignee
Eurosil Electronic GmbH
Temic Telefunken Microelectronic GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eurosil Electronic GmbH, Temic Telefunken Microelectronic GmbH filed Critical Eurosil Electronic GmbH
Publication of EP0483537A2 publication Critical patent/EP0483537A2/fr
Publication of EP0483537A3 publication Critical patent/EP0483537A3/de
Application granted granted Critical
Publication of EP0483537B1 publication Critical patent/EP0483537B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to a current source circuit with a first, second, third and fourth field effect transistor according to the preamble of claim 1.
  • Such a current source circuit is known from the journal "IEEE Journal of Solid States Circuits", June 1977, pages 224 to 231, in particular FIG. 8 on page 228.
  • This circuit is shown in FIG. 1, according to which the field effect transistors T1 to T4 together with the resistor R1 form a reference current source.
  • the two n-channel transistors T1 and T2 represent a first current mirror.
  • the two p-channel transistors T3 and T4 additionally form a second current mirror.
  • a current i3 is taken from the reference current source via an n-channel field effect transistor T5. which, depending on the selected size ratio of the first current mirror (W / L [T5] / W / L [T1]), is a fraction or a multiple of the current i1, the current i3 naturally having the same temperature dependency as the current i1.
  • the current i1 for the specified circuit dimensioning is 54 nA;
  • this reference current source according to FIG. 1 itself already consumes a current of approx.
  • this current draw is too large for many applications.
  • Another possibility is to increase the resistance value from R1 to, for example, 10 M ⁇ , as a result of which the current consumption of the reference current source drops to approximately 10 nA, which can thus also be tolerated in the case of "low power" circuits.
  • this resistor R1 is usually - as already explained above - formed by a p-well resistor and its sheet resistance is technology-related only approx. 2 k ⁇ /, a disproportionately large chip area (approx. 1 mm2) was required for such a resistor, which is of course also undesirable.
  • the invention is therefore based on the object of providing a current source circuit of the type mentioned at the outset which allows current to be drawn, the current of which is largely constant with little overall power consumption by the current source circuit.
  • the essence of the invention consists in simulating the resistor R1 according to FIG. 1 by a switched capacitance.
  • a stable quartz frequency of, for example, 32.768 kHz is available, a resistance of approx. 10 M ⁇ can easily be realized here with a small capacitance of a few pF.
  • a capacitive resistance of 10.1 M ⁇ results.
  • a thin silicon dioxide layer (gate oxide), which is generated in any case during the production of an integrated CMOS circuit, is usually used as the dielectric for such a capacitance.
  • the layer thickness of this oxide is typically a few 100 ⁇ and is manufactured within narrow tolerance limits of less than +/- 5%. Capacities with very small variations in the absolute value can thus be produced without additional process steps, so that under the stipulation of a constant clock frequency, a reference current source with small variations in the current i3 drawn by the transistor T5 with a low current consumption of the circuit itself, e.g. B. less than 10 nA and small chip area requirements.
  • a current source circuit is specified by the characterizing features of claim 2, which current output circuit with a preset temperature coefficient delivers.
  • the temperature coefficient of this output current is determined by the capacitors provided in the circuit arrangement controlled by the second current mirror, the sign of which is predetermined by the phase position of the clock signals supplied to this circuit arrangement.
  • the basic structure of the current source circuit according to FIG. 2 corresponds to that according to FIG. 1 with 5 field effect transistors T1 to T5.
  • the two n-channel transistors T1 and T2 and the two p-channel transistors T3 and T4 form a first and a second current mirror, for which purpose the control electrode of the transistor T1 with its drain electrode and the control electrode of the transistor T3 also with it Drain electrode are connected. Furthermore, the control electrodes of the transistors T1 and T2 or T3 and T4 forming a current mirror are connected to one another.
  • the two transistors T2 and T3 are connected in series via their channel paths and connect the reference potential of the circuit to an operating voltage source V DD , in that the transistor T2 has its source electrode at the reference potential and the source electrode of the transistor T3 is at the operating potential.
  • these two transistors T2 and T3 form a main current branch 2 which connects the reference potential to the operating voltage potential V DD .
  • a further main current branch 1, which is parallel to this, is connected by a series connection of transistor T1, transistor T4, a resistor R2 and two p Channel transistors T6 and T7, starting from the reference potential of the circuit and connected to one another in the order listed, the source electrode of transistor T6 being at the operating potential of the operating voltage source V DD .
  • an n-channel transistor T5 is provided, the gate electrode of which is connected to the first current mirror via the gate electrode of the transistor T1 and the source electrode of which is also at the reference potential of the circuit.
  • a current i3 can be taken from the drain electrode of this transistor T5, the magnitude of which corresponds to the current i1 flowing in the main circuit 1 with the same dimensions of the transistors T1 and T5. In the equilibrium state of the circuit, the current i1 corresponds to the current i2 flowing in the main circuit 2.
  • a first and second capacitor C1 and C2 are provided, the first capacitor C1 being arranged parallel to the channel path of the transistor T6 and the second capacitor C2 having its first connection at the reference potential of the circuit and with its second connection to the Control electrode of the first and second transistor T1 and T2 is connected.
  • the two control electrodes of the transistors T6 and T7 are supplied with clock signals Cl1 and Cl2 which are in phase opposition to one another, that is to say if the gate electrode of the transistor T7 receives a low signal (L level), and is simultaneously present on the gate electrode of the other transistor T6 High signal (H level) on.
  • the mode of operation of the circuit arrangement according to FIG. 2 will now be explained below:
  • the capacitor C1 is discharged by the transistor T6 at the L level during the clock phase, since the transistor T6 is turned on and at the same time the transistor T7 is in the blocked state.
  • the control electrode of transistor T6 is at an H level and at the same time the gate electrode of transistor T7 is at an L level, as a result of which capacitor C1 now charges up to a voltage value V C , which is determined by the size relationships of the Transistors T1 to T4 results.
  • the resistor R2 in the main current branch 1 only has the function of a current limitation and is intended to prevent the transistors from changing from H to L level when the clock signal Cl1 changes on the edge T1 to T4 briefly an excessive current flow occurs.
  • the value of this resistor R2 is not critical and can therefore z. B. be formed by an appropriately dimensioned p-channel transistor T7 itself, which has the desired resistance value in the conductive state. Since in this circuit the current i1 is not constant over time in comparison to that according to FIG.
  • the capacitor C2 already mentioned is of the common type Gate connection of the transistors T1, T2 and T5 connected as smoothing capacitance to the reference potential, the value of which is also on the order of a few pF.
  • an output current i3 can thus be generated with minimal space requirement and low power consumption, which has only small manufacturing-related tolerances and whose absolute value is almost exclusively dependent on the selected transistor dimensions of the transistors T1 to T5, the capacitance value of the capacitor C1 and the Frequency of the applied clock signal Cl1 and Cl2 depends.
  • the achievable temperature coefficient of the output current i3 is fixed and is approximately +3000 ppm / K, since the capacitor C1 itself has only a very low temperature coefficient.
  • the exemplary embodiment according to FIG. 3 contains, with the switching elements T1 to T7, C1 and C2 and R2, a circuit part which corresponds to the circuit arrangement according to FIG. 2. Therefore, this circuit part in following are no longer explained.
  • this circuit arrangement contains a current source transistor T8 which is controlled by the first current mirror T1 and T2 and is designed as an n-channel field effect transistor.
  • This transistor T8 which has its source electrode at the reference potential of the circuit, supplies an emitter current i4 for an npn bipolar transistor Q1, which serves as a reference voltage source Q ref .
  • its base electrode and its collector electrode are at the potential of the operating voltage source V DD , in order to thereby generate the base-emitter voltage V BE of the transistor Q1 at the circuit node K1 which is required as a temperature-dependent reference voltage.
  • a series circuit comprising two field effect transistors T9 and T10 connects this circuit node K1 to the operating voltage source V DD , the transistor T9 connected to this potential being of the p-channel type and the transistor T10 connected to the circuit node K1 being the n-channel type.
  • the connection point of the two channel sections of these transistors T9 and T10 leads to a connection K3 of a circuit arrangement 3.
  • a current i5 can be taken from the circuit arrangement 3 and, as will be shown further below, a certain temperature coefficient can be impressed on it.
  • this circuit arrangement 3 contains one of the second current mirror T3 and T4 controlled current source transistor T13 of the p-channel type, whose drain electrode supplies said output current i5 and whose source electrode is connected to the operating voltage source V DD via a series circuit comprising two p-channel effect transistors.
  • the control electrode of the transistor T11 is supplied with the clock signal Cl1 and the control electrode of the transistor T12 with the clock signal Cl2, which is in phase opposition to the clock signal Cl1, or vice versa, the clock signal Cl2 and the transistor T12 with the clock signal Cl1.
  • the clock signal lines are connected to the connections K5 and K6 of the circuit arrangement 3.
  • the output current i5 is withdrawn at a connection K7.
  • a first capacitor C4 of this circuit arrangement 3 corresponds to the capacitor C1 parallel to the channel section of the transistor T11, while a second capacitor C3 connects the connection point K4 of the two channel sections of the transistors T11 and T12 to the node K3.
  • the mode of operation of the circuit arrangement according to FIG. 3 is as follows:
  • the base-emitter voltage V BE of the vertical npn transistor Q1 manufactured in integrated CMOS technology is subject to only slight fluctuations in the given manufacturing process with the parameter scatter to be expected over several manufacturing lots.
  • the absolute value and temperature profile of this voltage are also only influenced by the current density, that is to say by the ratio of the emitter area of the transistor Q1 to the emitter current i4. Since the current i4, the size of which corresponds to the size of the current i1 with the same dimensioning of the transistors T1 and T8, is, however, only subject to slight production variations, the absolute value and temperature dependence of the reference voltage V BE of the reference voltage source Q ref can be determined very precisely in the given circuit dimensioning.
  • the capacitor C3 of the circuit arrangement 3 is initially disregarded, it is found that the arrangement of the switching elements T11, T12, T13 and C4 corresponds exactly to the circuit arrangement of the switching elements T4, T6, T7 and C1, that is, with the same dimensioning of the Capacitor C4 of transistors T11 to T13, like capacitor C1 and transistors T4, T6 and T7, the output current i5 and its temperature profile will correspond to the current i1.
  • Diagrams a, b according to FIG. 4 show the level curve of the clock signals Cl1 and Cl2, which are in phase opposition to one another.
  • the voltage diagram c shows the voltage curve V C4 of the capacitor C4. At time t 1, this capacitor C4 - C3 would not be present - charged by a voltage amount -V C4 to a final voltage -V end at time t2.
  • the capacitor C3 is now taken into consideration, the following occurs under the assumption that the transistors T9, T10 and T11 are driven with the clock signal Cl1 according to FIG. 4a and T12 with the inverted clock signal Cl2 according to FIG. 4b: While the clock signal is Cl1 to L level, the capacitor C4 is discharged via the transistor T11 to the operating potential V DD and at the same time the node K3 is also held via the transistor T9 to the operating potential V DD, that is, the capacitor C3 is also discharged .
  • the terminal K3 is connected to the reference voltage V BE via the transistor T10 which is turned on, while at the same time the capacitor C4 is discharged via the transistor T11 to the operating potential V DD , since the clock signal Cl2 switches to L level, that is, the capacitor C3 is simultaneously charged to the reference voltage V BE .
  • the reference voltage V BE becomes smaller and thus the initial charging voltage + V C4 is also reduced, i.e. the charge on the capacitor C4 from the initial voltage value + V C4 to the final voltage value -V end takes place over a smaller voltage range and with increasing temperature this means that the current i5 that can be drawn also becomes smaller with increasing temperature, that is to say that i5 has a negative temperature coefficient.
  • circuit arrangements 31, 32, 33, ... are connected in parallel, output currents i5, i51, i52, i53,. .. are generated with different temperature behavior.
  • Such a current source circuit is shown in FIG. 5, the reference voltage source Q ref and the switching elements T1 to T7, C1 and C2 are not shown.
  • Each of these circuit arrangements 31, 32, 33, ... correspond to their structure of the circuit arrangement 3 according to Figure 3. They thus contain transistors T111, T121, T131, T112, T122, T132, ... and capacitors C31, C41, C32, C42 , .... At the terminals K71, K72, K73, ... a current i51, i52, i53, ... can be removed.
  • FIG. 6 now shows a circuit with which the current source circuit according to FIG. 3 can be supplemented to generate an output current with negative temperature coefficients. It is assumed here that the circuit according to FIG. 3 supplies an output current i5 with a positive temperature coefficient. Instead of the current source circuit according to FIG. 3, FIG. 6 shows only the circuit branches supplying the output current i3 and the output current i5.
  • the output current i3 represents the input current for a current mirror made up of two p-channel field effect transistors, while the output current i5 is fed as an input current into a further current mirror made up of two n-channel field effect transistors T14 and T15.
  • the first current mirror T16, T17 is connected to the operating voltage source V DD and supplies an output current i6 via the transistor T17.
  • the second current mirror T14, T15 is connected to the reference potential of the circuit and supplies an output current i7 via the transistor T15. These two output currents i6 and i7 are summed to an output current i8 at a circuit node K8.
  • the output current i3 and thus also the output current i6 has a very low positive temperature coefficient
  • the output current i5 can have a very large positive temperature coefficient depending on the dimensioning of the capacitors C3 and C4
  • the total output current i8 which can be seen in the circuit according to FIG Difference of the current i6 and the current i7, have a negative temperature coefficient, the value of this temperature coefficient is only specified by the dimensioning of the transistors T15 and T17.
  • FIG. 7 shows a circuit expanded according to FIG. 6, in which further transistors T151, T152, T153, ... and T171, T172, T173, ... are provided as current source transistors controlled by the current mirrors.
  • the paired current source transistors T151, T171 and T152, T172 and T153, T173 each deliver an output current i71, i61 and i72, i62 and i73, i63, which are each added up in a circuit node K81, K82 and K83 to produce an output current i81, i82 and i83, these output currents i81, i82 and i83 having different negative temperature coefficients, whereby the values of these temperature coefficients only depend on the dimensioning of the transistors T151 to T153 and T171 to T173 is specified.
  • circuits described above which are built in integrated CMOS technology, can, contrary to the conditions shown, also be operated with a different polarity of the operating voltage source V DD by swapping the p- and n-channel transistors and changing the reference point of the reference voltage V BE , the capacitors C1 and C4 from + V DD to -V DD .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
EP91116900A 1990-10-29 1991-10-04 Circuit de source de courant Expired - Lifetime EP0483537B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4034371 1990-10-29
DE4034371A DE4034371C1 (fr) 1990-10-29 1990-10-29

Publications (3)

Publication Number Publication Date
EP0483537A2 true EP0483537A2 (fr) 1992-05-06
EP0483537A3 EP0483537A3 (en) 1992-11-25
EP0483537B1 EP0483537B1 (fr) 1996-06-05

Family

ID=6417260

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91116900A Expired - Lifetime EP0483537B1 (fr) 1990-10-29 1991-10-04 Circuit de source de courant

Country Status (5)

Country Link
US (1) US5204612A (fr)
EP (1) EP0483537B1 (fr)
JP (1) JP2504647B2 (fr)
DE (2) DE4034371C1 (fr)
HK (1) HK59797A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0623865A2 (fr) * 1993-05-07 1994-11-09 Siemens Aktiengesellschaft Dispositif source de courant
WO2003098368A1 (fr) * 2002-05-21 2003-11-27 Toumaz Technology Limited Circuit de reference

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4201155C1 (fr) * 1992-01-17 1993-01-28 Texas Instruments Deutschland Gmbh, 8050 Freising, De
KR960004573B1 (ko) * 1994-02-15 1996-04-09 금성일렉트론주식회사 기동회로를 갖는 기준전압발생회로
FR2721771B1 (fr) * 1994-06-27 1996-09-06 Sgs Thomson Microelectronics Dispositif de mise en veille d'une source de polarisation.
DE19524185B4 (de) * 1995-04-18 2009-01-29 Tridonicatco Gmbh & Co. Kg Gleichrichterschaltung
JPH08293744A (ja) * 1995-04-21 1996-11-05 Mitsubishi Electric Corp 半導体回路
EP0778509B1 (fr) * 1995-12-06 2002-05-02 International Business Machines Corporation Générateur de courant de référence compensé en température avec des résistances à fort coéfficient de température
US5808460A (en) * 1997-09-29 1998-09-15 Texas Instruments Incorporated Rapid power enabling circuit
US5818294A (en) * 1996-07-18 1998-10-06 Advanced Micro Devices, Inc. Temperature insensitive current source
US5854563A (en) * 1996-07-19 1998-12-29 Vlsi Technology, Inc. Process control monitoring system and method therefor
WO1998011660A1 (fr) * 1996-09-11 1998-03-19 Macronix International Co., Ltd. Circuit d'alimentation basse tension
US5877616A (en) * 1996-09-11 1999-03-02 Macronix International Co., Ltd. Low voltage supply circuit for integrated circuit
US5936392A (en) * 1997-05-06 1999-08-10 Vlsi Technology, Inc. Current source, reference voltage generator, method of defining a PTAT current source, and method of providing a temperature compensated reference voltage
KR19990047008A (ko) * 1997-12-02 1999-07-05 구본준 외부조건 변화에 둔감한 기준전압 발생회로
US6014042A (en) * 1998-02-19 2000-01-11 Rambus Incorporated Phase detector using switched capacitors
US6222350B1 (en) * 2000-01-21 2001-04-24 Titan Specialties, Ltd. High temperature voltage regulator circuit
DE10015276A1 (de) * 2000-03-28 2001-10-11 Infineon Technologies Ag Stromerzeugungseinrichtung und Spannungserzeugungseinrichtung
DE10042586B4 (de) * 2000-08-30 2010-09-30 Infineon Technologies Ag Referenzstromquelle mit MOS-Transistoren
DE10065379A1 (de) * 2000-12-27 2002-07-18 Infineon Technologies Ag Stromspiegelschaltung
KR100492095B1 (ko) * 2003-02-24 2005-06-02 삼성전자주식회사 스타트업 회로를 갖는 바이어스회로
DE102004002007B4 (de) * 2004-01-14 2012-08-02 Infineon Technologies Ag Transistoranordnung mit Temperaturkompensation und Verfahren zur Temperaturkompensation
US7673881B2 (en) * 2007-01-29 2010-03-09 Sapo U.S.A. Corp. Target game
JP2010033448A (ja) * 2008-07-30 2010-02-12 Nec Electronics Corp バンドギャップレファレンス回路
FR2973128B1 (fr) * 2011-03-22 2014-01-10 Altis Semiconductor Snc Source de courant de polarisation pour amplificateur operationnel utilisant des paires differentielles cmos

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472675A (en) * 1981-11-06 1984-09-18 Mitsubishi Denki Kabushiki Kaisha Reference voltage generating circuit
JPS6146508A (ja) * 1984-08-11 1986-03-06 Fujitsu Ltd 定電流源安定化回路
US4703249A (en) * 1985-08-13 1987-10-27 Sgs Microelettronica S.P.A. Stabilized current generator with single power supply, particularly for MOS integrated circuits

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380944A (en) * 1976-10-16 1978-07-17 Toshiba Corp Semiconductor circuit
NL8001558A (nl) * 1980-03-17 1981-10-16 Philips Nv Stroomstabilisator opgebouwd met veldeffekttransistor van het verrijkingstype.
JPS57186564A (en) * 1981-05-12 1982-11-17 Lucas Industries Ltd Antiskid braking system for car
JPH0810415B2 (ja) * 1984-12-04 1996-01-31 日本電気株式会社 基準電圧源
US4706013A (en) * 1986-11-20 1987-11-10 Industrial Technology Research Institute Matching current source
JPS63237609A (ja) * 1987-03-26 1988-10-04 Toshiba Corp 電圧制御型発振回路
GB2213011B (en) * 1987-09-16 1991-09-25 Philips Electronic Associated A method of and a circuit arrangement for processing sampled analogue electricals
GB2225885A (en) * 1988-12-08 1990-06-13 Philips Electronic Associated Integrator circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472675A (en) * 1981-11-06 1984-09-18 Mitsubishi Denki Kabushiki Kaisha Reference voltage generating circuit
JPS6146508A (ja) * 1984-08-11 1986-03-06 Fujitsu Ltd 定電流源安定化回路
US4703249A (en) * 1985-08-13 1987-10-27 Sgs Microelettronica S.P.A. Stabilized current generator with single power supply, particularly for MOS integrated circuits

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ELEKTOR ELECTRONICS. Nr. 10, Oktober 1980, CANTERBURY GB Seiten 1012 - 1016; 'Up-to-Date Filters In A Single IC, Switched Capacitors' *
IEEE JOURNAL OF SOLID-STATE CIRCUITS. Bd. SC-12, Nr. 3, Juni 1977, NEW YORK US Seiten 224 - 231; ERIC VITTOZ & JEAN FELLRATH: 'CMOS Analog Integrated Circuits Based On Weak Inversion Operation' *
JOURNAL OF THE AUDIO ENGINEERING SOCIETY. Bd. 27, Nr. 12, Dezember 1979, NEW YORK US Seiten 982 - 988; R.R. BUSS & D.B. COX: 'Practical Solid-State Integrated Filters' *
PATENT ABSTRACTS OF JAPAN vol. 10, no. 206 (P-478)(2262) 18. Juli 1986 & JP-A-61 046 508 ( FUJITSU LTD ) 6. März 1986 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0623865A2 (fr) * 1993-05-07 1994-11-09 Siemens Aktiengesellschaft Dispositif source de courant
EP0623865A3 (fr) * 1993-05-07 1995-01-11 Siemens Ag Dispositif source de courant.
WO2003098368A1 (fr) * 2002-05-21 2003-11-27 Toumaz Technology Limited Circuit de reference
US7242241B2 (en) 2002-05-21 2007-07-10 Dna Electronics Limited Reference circuit

Also Published As

Publication number Publication date
EP0483537B1 (fr) 1996-06-05
US5204612A (en) 1993-04-20
JPH05189071A (ja) 1993-07-30
EP0483537A3 (en) 1992-11-25
JP2504647B2 (ja) 1996-06-05
HK59797A (en) 1997-05-16
DE4034371C1 (fr) 1991-10-31
DE59107888D1 (de) 1996-07-11

Similar Documents

Publication Publication Date Title
EP0483537B1 (fr) Circuit de source de courant
DE19959180C2 (de) Differentialverstärker
DE69221109T2 (de) Digital gesteuertes CMOS-Verzögerungsgatter
DE3327260A1 (de) Schmitt-trigger
DE2641860A1 (de) Integrierte stromversorgungsschaltung
DE2104043A1 (de) Operationsverstärker
DE2855303A1 (de) Linearer verstaerker
DE3640368C2 (de) Spannungsverstärkerschaltung mit niedrigem Offset
DE102004027298B4 (de) Auf dem Chip ausgeführter Hochpassfilter mit großer Zeitkonstanten
DE69310162T2 (de) Pegelumsetzungsschaltung
EP0130587B1 (fr) Convertisseur du niveau d'un signal d'entrée pour un circuit numérique MOS
DE69403739T2 (de) Spannung-Strom-Umsetzter
DE2745302C2 (de) Schaltungsanordnung zur Kontrolle der Versorgungsspannung für vorzugsweise integrierte Schaltkreise
DE2250625B2 (de) Schaltungsanordnung zur Konstanthaltung eines an eine Last gelieferten Stromes
DE69707940T2 (de) Ruhestromeinstellung für Verstärkerausgangsstufe
DE69522196T2 (de) Pufferschaltung und Vorspannungsschaltung
DE2635574C3 (de) Stromspiegelschaltung
DE4129334A1 (de) Praezisions-mos-widerstand
DE2440937C3 (de) Differenzverstärker mit zwei MOS-Transistoren
DE3405809C2 (de) Ausgangsstufe
DE4344447A1 (de) Konstantstromquelle
DE69403559T2 (de) Differentielle Laststufe mit stufenweise veränderlicher Impedanz, und getakteter Komparator mit einer solchen Laststufe
DE2657281C3 (de) MIS-Inverterschaltung
EP0822656B1 (fr) Montage de circuit avec un amplificateur opérationnel
DE69227685T2 (de) Spannungsvergleichschaltung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): CH DE FR GB IT LI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): CH DE FR GB IT LI

17P Request for examination filed

Effective date: 19930119

17Q First examination report despatched

Effective date: 19940712

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: TEMIC TELEFUNKEN MICROELECTRONIC GMBH

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): CH DE FR GB IT LI

ITF It: translation for a ep patent filed

Owner name: DE DOMINICIS & MAYER S.R.L.

REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: KIRKER & CIE SA

REF Corresponds to:

Ref document number: 59107888

Country of ref document: DE

Date of ref document: 19960711

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19960626

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: CH

Ref legal event code: PUE

Owner name: TEMIC TELEFUNKEN MICROELECTRONIC GMBH TRANSFER- TE

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010914

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20010917

Year of fee payment: 11

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021004

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021031

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021031

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20021004

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20031009

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050630

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20051004

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20081022

Year of fee payment: 18

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100501