DE69513250D1 - Verfahren und Gerät zur Prüfung integrierter Schaltungen - Google Patents

Verfahren und Gerät zur Prüfung integrierter Schaltungen

Info

Publication number
DE69513250D1
DE69513250D1 DE69513250T DE69513250T DE69513250D1 DE 69513250 D1 DE69513250 D1 DE 69513250D1 DE 69513250 T DE69513250 T DE 69513250T DE 69513250 T DE69513250 T DE 69513250T DE 69513250 D1 DE69513250 D1 DE 69513250D1
Authority
DE
Germany
Prior art keywords
integrated circuits
testing integrated
testing
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69513250T
Other languages
English (en)
Other versions
DE69513250T2 (de
Inventor
Robert Beat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Publication of DE69513250D1 publication Critical patent/DE69513250D1/de
Application granted granted Critical
Publication of DE69513250T2 publication Critical patent/DE69513250T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69513250T 1994-08-26 1995-08-21 Verfahren und Gerät zur Prüfung integrierter Schaltungen Expired - Fee Related DE69513250T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9417297A GB9417297D0 (en) 1994-08-26 1994-08-26 Method and apparatus for testing an integrated circuit device

Publications (2)

Publication Number Publication Date
DE69513250D1 true DE69513250D1 (de) 1999-12-16
DE69513250T2 DE69513250T2 (de) 2000-02-17

Family

ID=10760464

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69513250T Expired - Fee Related DE69513250T2 (de) 1994-08-26 1995-08-21 Verfahren und Gerät zur Prüfung integrierter Schaltungen

Country Status (5)

Country Link
US (1) US6052806A (de)
EP (1) EP0698848B1 (de)
JP (1) JP2898230B2 (de)
DE (1) DE69513250T2 (de)
GB (1) GB9417297D0 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6581019B1 (en) * 2000-03-20 2003-06-17 Koninklijke Philips Electronics N.V. Computer-system-on-a-chip with test-mode addressing of normally off-bus input/output ports
JP4212257B2 (ja) * 2001-04-26 2009-01-21 株式会社東芝 半導体集積回路
US7007157B2 (en) * 2001-10-30 2006-02-28 Microsoft Corporation Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic
US7065683B1 (en) 2001-12-05 2006-06-20 Lsi Logic Corporation Long path at-speed testing
US8151149B2 (en) * 2009-06-29 2012-04-03 Hynix Semiconductor Inc. Semiconductor memory apparatus and method of testing the same
US11410713B2 (en) * 2020-04-06 2022-08-09 Micron Technology, Inc. Apparatuses and methods for detecting illegal commands and command sequences

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343141A (en) * 1964-12-23 1967-09-19 Ibm Bypassing of processor sequence controls for diagnostic tests
GB1131085A (en) * 1966-03-25 1968-10-23 Secr Defence Improvements in or relating to the testing and repair of electronic digital computers
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
JPS5352029A (en) * 1976-10-22 1978-05-12 Fujitsu Ltd Arithmetic circuit unit
US4481627A (en) * 1981-10-30 1984-11-06 Honeywell Information Systems Inc. Embedded memory testing method and apparatus
US4575792A (en) * 1982-03-31 1986-03-11 Honeywell Information Systems Inc. Shared interface apparatus for testing the memory sections of a cache unit
US4527234A (en) * 1982-08-02 1985-07-02 Texas Instruments Incorporated Emulator device including a semiconductor substrate having the emulated device embodied in the same semiconductor substrate
EP0253161B1 (de) * 1986-06-25 1991-10-16 Nec Corporation Prüfschaltung für eine Speichereinrichtung mit willkürlichem Zugriff
JPS63295979A (ja) * 1987-05-27 1988-12-02 Nec Corp 電子回路パッケ−ジ自己診断装置
JPS643744A (en) * 1987-06-26 1989-01-09 Hitachi Ltd Lsi test method
JPH0727011B2 (ja) * 1988-03-18 1995-03-29 日本電気株式会社 大規模集積回路
JP2612618B2 (ja) * 1989-10-13 1997-05-21 富士通株式会社 半導体集積回路装置
JPH03239974A (ja) * 1990-02-19 1991-10-25 Fujitsu Ltd ループスキャンパスを持った論理回路の試験方式
JP2702259B2 (ja) * 1990-02-27 1998-01-21 三菱電機株式会社 半導体集積回路装置
JPH04125477A (ja) * 1990-09-17 1992-04-24 Hitachi Ltd 半導体集積回路装置
TW200603B (en) * 1991-04-11 1993-02-21 Hitachi Seisakusyo Kk Semiconductor memory device
JP2762833B2 (ja) * 1992-02-27 1998-06-04 日本電気株式会社 ダイナミック型ランダムアクセスメモリ装置
US5459733A (en) * 1992-03-20 1995-10-17 National Semiconductor Corporation Input/output checker for a memory array
JPH0643221A (ja) * 1992-07-27 1994-02-18 Sharp Corp 半導体集積回路
US5410544A (en) * 1993-06-30 1995-04-25 Intel Corporation External tester control for flash memory
US5623620A (en) * 1993-06-30 1997-04-22 Intel Corporation Special test modes for a page buffer shared resource in a memory device
US5509134A (en) * 1993-06-30 1996-04-16 Intel Corporation Method and apparatus for execution of operations in a flash memory array
JP3919213B2 (ja) * 1993-09-30 2007-05-23 マクロニクス インターナショナル カンパニイ リミテッド 不揮発性状態書込みを備えた自動テスト回路
US5440516A (en) * 1994-01-27 1995-08-08 Sgs-Thomson Microelectronics, Inc. Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
FR2722907B1 (fr) * 1994-07-20 1996-09-06 Sgs Thomson Microelectronics Memoire integree programmable comportant des moyens d'emulation
US5577050A (en) * 1994-12-28 1996-11-19 Lsi Logic Corporation Method and apparatus for configurable build-in self-repairing of ASIC memories design

Also Published As

Publication number Publication date
DE69513250T2 (de) 2000-02-17
JPH08194035A (ja) 1996-07-30
JP2898230B2 (ja) 1999-05-31
US6052806A (en) 2000-04-18
EP0698848A1 (de) 1996-02-28
GB9417297D0 (en) 1994-10-19
EP0698848B1 (de) 1999-11-10

Similar Documents

Publication Publication Date Title
DE69734379D1 (de) Vorrichtung zur Prüfung von integrierten Schaltungen
DE69629098D1 (de) Verfahren und Vorrichtung zur Belastungsprüfung
DE69535165D1 (de) Verfahren und Vorrichtung zur Bohrlochuntersuchung
DE69726668D1 (de) Verfahren und Vorrichtung zur Prüfung einer Speicherschaltung in einer Halbleitereinrichtung
DE19781229T1 (de) Elektrochemische Testvorrichtung und diesbezügliche Verfahren
DE69632325D1 (de) Verfahren und gerät zur spannungsprüfung
DE69708255T2 (de) Diagnosesystem und Verfahren bei einer integrierten Schaltung
DE69705813D1 (de) Diagnosesystem und Verfahren bei einer integrierten Halbleiterschaltung
DE69716088T2 (de) Verfahren und gerät zur anzeige eines autostereogramms
DE69532631D1 (de) Einrichtung und verfahren zur datenausgabe
DE19980623T1 (de) Vorrichtung und Verfahren zur Prüfung auf Undichtigkeiten
DE69737845D1 (de) Gerät und Verfahren zur Bohrlochmessung
DE69630224D1 (de) Verfahren und einrichtung zur bestückung elektronischer bauteile
DE69526347T2 (de) Mehrschichtuge testvorrichtungen und verfahren zur fructosaminbestimmung
DE69619415T2 (de) Verfahren zur Leckprüfung von Rohren und Gerät zur Leckprüfung
DE69717216T2 (de) Schaltplatinenprüfvorrichtung und Verfahren dafür
DE69720157T2 (de) System und Verfahren zur Prüfung elektronischer Geräte
DE69932456D1 (de) VERFAHREN UND VORRICHTUNG ZUR KüHLUNG VON INTEGRIERTEN SCHALTUNGEN, DIE RüCKSEITIG OPTISCH GEPRüFT WERDEN
DE69836805D1 (de) Gerät und verfahren zur bilderzeugung
DE69606988D1 (de) Verfahren und vorrichtung zur parallelen automatischen prüfung von elektronischen schaltungen
DE69830967D1 (de) Verfahren und System zur Prüfung einer integrierten Schaltung
DE69830975D1 (de) Gerät und Verfahren zur Potential-messung
DE69506585D1 (de) Verfahren und gerät zur prüfung von halbleiterplatten
DE69724737D1 (de) Verfahren und Vorrichtung zur Prüfung von Speicherschaltungen
DE69513250T2 (de) Verfahren und Gerät zur Prüfung integrierter Schaltungen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee