DE69128368T2 - Verfahren zur Herstellung eines Layouts für eine Halbleiterschaltungsanordnung - Google Patents

Verfahren zur Herstellung eines Layouts für eine Halbleiterschaltungsanordnung

Info

Publication number
DE69128368T2
DE69128368T2 DE69128368T DE69128368T DE69128368T2 DE 69128368 T2 DE69128368 T2 DE 69128368T2 DE 69128368 T DE69128368 T DE 69128368T DE 69128368 T DE69128368 T DE 69128368T DE 69128368 T2 DE69128368 T2 DE 69128368T2
Authority
DE
Germany
Prior art keywords
layout
producing
circuit arrangement
semiconductor circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128368T
Other languages
English (en)
Other versions
DE69128368D1 (de
Inventor
Makoto Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of DE69128368D1 publication Critical patent/DE69128368D1/de
Application granted granted Critical
Publication of DE69128368T2 publication Critical patent/DE69128368T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69128368T 1990-02-21 1991-02-21 Verfahren zur Herstellung eines Layouts für eine Halbleiterschaltungsanordnung Expired - Fee Related DE69128368T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4142590 1990-02-21

Publications (2)

Publication Number Publication Date
DE69128368D1 DE69128368D1 (de) 1998-01-22
DE69128368T2 true DE69128368T2 (de) 1998-04-16

Family

ID=12608009

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128368T Expired - Fee Related DE69128368T2 (de) 1990-02-21 1991-02-21 Verfahren zur Herstellung eines Layouts für eine Halbleiterschaltungsanordnung

Country Status (4)

Country Link
US (1) US5212653A (de)
EP (1) EP0443857B1 (de)
JP (1) JP2746762B2 (de)
DE (1) DE69128368T2 (de)

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JP2509755B2 (ja) * 1990-11-22 1996-06-26 株式会社東芝 半導体集積回路製造方法
US5566078A (en) * 1993-05-26 1996-10-15 Lsi Logic Corporation Integrated circuit cell placement using optimization-driven clustering
US5440497A (en) * 1993-06-29 1995-08-08 Mitsubishi Semiconductor America, Inc. Method of and system for laying out bus cells on an integrated circuit chip
US5812435A (en) * 1993-09-21 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Shape simulation method allowing simulation of processed shape during steps of manufacturing a semiconductor device in a short period of time
US5675501A (en) * 1994-03-15 1997-10-07 Kabushiki Kaisha Toshiba Method of designing semiconductor integrated circuit apparatus having no dead space
US5450332A (en) * 1994-06-24 1995-09-12 The United States Of America As Represented By The National Security Agency Method of creating a mebes pattern-generation file for use in the manufacture of integrated-circuit masks
US5452215A (en) * 1994-08-24 1995-09-19 Ibm Business Machines Corporation System and method for designing a finite state machine to reduce power dissipation
US5734583A (en) * 1994-09-30 1998-03-31 Yozan Inc. Capacitance forming method
US5633807A (en) * 1995-05-01 1997-05-27 Lucent Technologies Inc. System and method for generating mask layouts
US5764532A (en) * 1995-07-05 1998-06-09 International Business Machines Corporation Automated method and system for designing an optimized integrated circuit
JP4004105B2 (ja) * 1997-07-24 2007-11-07 富士通株式会社 電源回路図の設計システム
US6060760A (en) * 1997-08-13 2000-05-09 Tritech Microelectronics, Ltd. Optimal resistor network layout
US6769098B2 (en) * 2000-02-29 2004-07-27 Matsushita Electric Industrial Co., Ltd. Method of physical design for integrated circuit
US7844437B1 (en) * 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US7222321B2 (en) * 2005-05-10 2007-05-22 Anaglobe Technology, Inc. System and method for manipulating an integrated circuit layout
JP4771831B2 (ja) * 2006-03-02 2011-09-14 富士通株式会社 図形表示プログラム及び図形表示方法
US8386976B2 (en) * 2007-02-15 2013-02-26 United Microelectronics Corp. Method for producing layout of semiconductor integrated circuit with radio frequency devices
US8692608B2 (en) 2011-09-19 2014-04-08 United Microelectronics Corp. Charge pump system capable of stabilizing an output voltage
US9030221B2 (en) 2011-09-20 2015-05-12 United Microelectronics Corporation Circuit structure of test-key and test method thereof
US8395455B1 (en) 2011-10-14 2013-03-12 United Microelectronics Corp. Ring oscillator
US8421509B1 (en) 2011-10-25 2013-04-16 United Microelectronics Corp. Charge pump circuit with low clock feed-through
US8588020B2 (en) 2011-11-16 2013-11-19 United Microelectronics Corporation Sense amplifier and method for determining values of voltages on bit-line pair
US8493806B1 (en) 2012-01-03 2013-07-23 United Microelectronics Corporation Sense-amplifier circuit of memory and calibrating method thereof
US8970197B2 (en) 2012-08-03 2015-03-03 United Microelectronics Corporation Voltage regulating circuit configured to have output voltage thereof modulated digitally
US8724404B2 (en) 2012-10-15 2014-05-13 United Microelectronics Corp. Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array
US8669897B1 (en) 2012-11-05 2014-03-11 United Microelectronics Corp. Asynchronous successive approximation register analog-to-digital converter and operating method thereof
US8711598B1 (en) 2012-11-21 2014-04-29 United Microelectronics Corp. Memory cell and memory cell array using the same
US8873295B2 (en) 2012-11-27 2014-10-28 United Microelectronics Corporation Memory and operation method thereof
US8643521B1 (en) 2012-11-28 2014-02-04 United Microelectronics Corp. Digital-to-analog converter with greater output resistance
US8953401B2 (en) 2012-12-07 2015-02-10 United Microelectronics Corp. Memory device and method for driving memory array thereof
US9030886B2 (en) 2012-12-07 2015-05-12 United Microelectronics Corp. Memory device and driving method thereof
US8917109B2 (en) 2013-04-03 2014-12-23 United Microelectronics Corporation Method and device for pulse width estimation
US9105355B2 (en) 2013-07-04 2015-08-11 United Microelectronics Corporation Memory cell array operated with multiple operation voltage
US8947911B1 (en) 2013-11-07 2015-02-03 United Microelectronics Corp. Method and circuit for optimizing bit line power consumption
US8866536B1 (en) 2013-11-14 2014-10-21 United Microelectronics Corp. Process monitoring circuit and method
US9143143B2 (en) 2014-01-13 2015-09-22 United Microelectronics Corp. VCO restart up circuit and method thereof
JP2015184957A (ja) * 2014-03-25 2015-10-22 株式会社ジーダット フロアプラン設計装置、方法、プログラム及び記録媒体
JP2015210579A (ja) * 2014-04-24 2015-11-24 株式会社ジーダット フロアプラン設計装置、方法、プログラム及び記録媒体

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Publication number Priority date Publication date Assignee Title
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
JPS59154055A (ja) * 1983-02-22 1984-09-03 Hitachi Ltd 論理回路基板上の素子配置方法
US4694403A (en) * 1983-08-25 1987-09-15 Nec Corporation Equalized capacitance wiring method for LSI circuits
JPS6156435A (ja) * 1984-07-25 1986-03-22 Fujitsu Ltd 半導体集積回路装置に於ける配線長予測方法
JPH0763074B2 (ja) * 1986-02-25 1995-07-05 株式会社東芝 半導体論理集積回路の論理セル配置方法
EP0271596B1 (de) * 1986-12-17 1995-05-17 International Business Machines Corporation VLSI-Chip und Verfahren zur Herstellung
JPS63278249A (ja) * 1986-12-26 1988-11-15 Toshiba Corp 半導体集積回路装置の配線方法
US4908772A (en) * 1987-03-30 1990-03-13 Bell Telephone Laboratories Integrated circuits with component placement by rectilinear partitioning
JP2535976B2 (ja) * 1987-11-17 1996-09-18 株式会社日立製作所 形態接続構成自動作成システム
JP2672655B2 (ja) 1989-06-14 1997-11-05 松下電子工業株式会社 半導体集積回路の製造方法

Also Published As

Publication number Publication date
EP0443857A3 (en) 1993-06-30
DE69128368D1 (de) 1998-01-22
JPH04211154A (ja) 1992-08-03
EP0443857B1 (de) 1997-12-10
JP2746762B2 (ja) 1998-05-06
US5212653A (en) 1993-05-18
EP0443857A2 (de) 1991-08-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA,

8339 Ceased/non-payment of the annual fee