DE60212271D1 - Eingebauter Selbsttest mit eingebautem Speicher und Prozessor in einer ASIC Vorrichtung - Google Patents

Eingebauter Selbsttest mit eingebautem Speicher und Prozessor in einer ASIC Vorrichtung

Info

Publication number
DE60212271D1
DE60212271D1 DE60212271T DE60212271T DE60212271D1 DE 60212271 D1 DE60212271 D1 DE 60212271D1 DE 60212271 T DE60212271 T DE 60212271T DE 60212271 T DE60212271 T DE 60212271T DE 60212271 D1 DE60212271 D1 DE 60212271D1
Authority
DE
Germany
Prior art keywords
built
self
processor
test
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60212271T
Other languages
English (en)
Other versions
DE60212271T2 (de
Inventor
D Taylor
D Montierth
D Bodily
Gary Zimmermann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marvell International Technology Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Application granted granted Critical
Publication of DE60212271D1 publication Critical patent/DE60212271D1/de
Publication of DE60212271T2 publication Critical patent/DE60212271T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1816—Testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE60212271T 2001-07-30 2002-04-15 Eingebauter Selbsttest mit eingebautem Speicher und Prozessor in einer ASIC Vorrichtung Expired - Lifetime DE60212271T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/917,972 US7418642B2 (en) 2001-07-30 2001-07-30 Built-in-self-test using embedded memory and processor in an application specific integrated circuit
US917972 2001-07-30

Publications (2)

Publication Number Publication Date
DE60212271D1 true DE60212271D1 (de) 2006-07-27
DE60212271T2 DE60212271T2 (de) 2007-07-19

Family

ID=25439587

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60212271T Expired - Lifetime DE60212271T2 (de) 2001-07-30 2002-04-15 Eingebauter Selbsttest mit eingebautem Speicher und Prozessor in einer ASIC Vorrichtung

Country Status (7)

Country Link
US (6) US7418642B2 (de)
EP (1) EP1282041B1 (de)
JP (1) JP2003114260A (de)
KR (1) KR100932562B1 (de)
DE (1) DE60212271T2 (de)
SG (1) SG94870A1 (de)
TW (1) TWI276107B (de)

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US7975094B2 (en) 2004-04-15 2011-07-05 Marvell International Technology Ltd. Programmable I/O interface
US8621304B2 (en) * 2004-10-07 2013-12-31 Hewlett-Packard Development Company, L.P. Built-in self-test system and method for an integrated circuit
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TWI387973B (zh) * 2008-10-30 2013-03-01 Silicon Motion Inc 資料儲存裝置、資料儲存控制器及相關自動化測試的方法
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US8850277B2 (en) * 2011-07-15 2014-09-30 Synopsys, Inc. Detecting random telegraph noise induced failures in an electronic memory
CN102890970B (zh) * 2011-07-21 2017-04-19 广东新岸线计算机***芯片有限公司 一种pop封装的soc芯片dram输入/输出测试方法和装置
US9117552B2 (en) * 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US9024657B2 (en) 2012-10-11 2015-05-05 Easic Corporation Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller
US8677306B1 (en) * 2012-10-11 2014-03-18 Easic Corporation Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC
US9384108B2 (en) * 2012-12-04 2016-07-05 International Business Machines Corporation Functional built-in self test for a chip
US20150026528A1 (en) * 2013-07-16 2015-01-22 Manuel A. d'Abreu Controller based memory evaluation
US10126362B2 (en) 2014-12-15 2018-11-13 International Business Machines Corporation Controlling a test run on a device under test without controlling the test equipment testing the device under test
US9417952B2 (en) 2014-12-18 2016-08-16 Freescale Semiconductor, Inc. Direct memory access (DMA) unit with error detection
US9690681B1 (en) * 2015-09-03 2017-06-27 Cadence Design Systems, Inc. Method and system for automatically generating executable system-level tests
CN106646191A (zh) * 2016-11-25 2017-05-10 天津津航计算技术研究所 针对SiP内嵌存储器的功能测试方法
US10490291B1 (en) 2018-04-24 2019-11-26 The United States Of America, As Represented By The Secretary Of The Navy Memory check ASIC for fuzes and safety and arming devices
US10930364B2 (en) 2018-11-16 2021-02-23 International Business Machines Corporation Iterative functional test exerciser reload and execution
DE102019207868A1 (de) * 2019-05-29 2020-12-03 Continental Teves Ag & Co. Ohg Modul und Verfahren zur Initialisierung und Kalibrierung eines Produkts während dessen Herstellung
DE102020121109A1 (de) * 2019-09-20 2021-03-25 Samsung Electronics Co., Ltd. Speicher-controller, speichervorrichtungen und betriebsverfahren der speichervorrichtungen
KR102416994B1 (ko) * 2020-10-23 2022-07-05 연세대학교 산학협력단 리던던시 분석 방법 및 리던던시 분석 장치

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Also Published As

Publication number Publication date
SG94870A1 (en) 2003-03-18
EP1282041A3 (de) 2003-10-22
TWI276107B (en) 2007-03-11
US8566660B2 (en) 2013-10-22
US8046652B2 (en) 2011-10-25
DE60212271T2 (de) 2007-07-19
JP2003114260A (ja) 2003-04-18
EP1282041B1 (de) 2006-06-14
KR20030011650A (ko) 2003-02-11
US20130080835A1 (en) 2013-03-28
US7890828B2 (en) 2011-02-15
US20120036396A1 (en) 2012-02-09
US20090013229A1 (en) 2009-01-08
EP1282041A2 (de) 2003-02-05
US8874983B2 (en) 2014-10-28
US20030023914A1 (en) 2003-01-30
KR100932562B1 (ko) 2009-12-17
US20140068333A1 (en) 2014-03-06
US7418642B2 (en) 2008-08-26
US8321731B2 (en) 2012-11-27
US20110138241A1 (en) 2011-06-09

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE., SG

8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: DILG HAEUSLER SCHINDELMANN PATENTANWALTSGESELLSCHA

8328 Change in the person/name/address of the agent

Representative=s name: DILG HAEUSLER SCHINDELMANN PATENTANWALTSGESELLSCHA

8327 Change in the person/name/address of the patent owner

Owner name: MARVELL INTERNATIONAL TECHNOLOGY LTD., HAMILTO, BM

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,