DE2954543C2 - - Google Patents
Info
- Publication number
- DE2954543C2 DE2954543C2 DE2954543A DE2954543A DE2954543C2 DE 2954543 C2 DE2954543 C2 DE 2954543C2 DE 2954543 A DE2954543 A DE 2954543A DE 2954543 A DE2954543 A DE 2954543A DE 2954543 C2 DE2954543 C2 DE 2954543C2
- Authority
- DE
- Germany
- Prior art keywords
- polycrystalline
- semiconductor layer
- type
- impurity
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 2
- 239000002019 doping agent Substances 0.000 description 11
- 230000000873 masking effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 108090000623 proteins and genes Proteins 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018514—Interface arrangements with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0231—Astable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45394—Indexing scheme relating to differential amplifiers the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Electromagnetism (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Control Of Electrical Variables (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
Die Erfindung betrifft ein Verfahren zur Herstellung von
zwei Feldeffekttransistoren mit isoliertem Gate (IGFET) mit
unterschiedlichen Schwellenspannungen nach dem Oberbegriff des
Patentanspruches, wie es aus der DE-OS 23 38 279 bekannt ist.
In vielen elektrischen Schaltungen ist es notwendig,
Bezugsspannungen vorzugeben. Als physikalische Größe für eine
solche Bezugsspannung ist vielfach die Durchbruchsspannung bzw.
Zenerspannung einer Diode gewählt worden; es ist ebenso aber
auch möglich, die Schwellenspannung Vth eines Isolierschicht-
Feldeffekttransistors dazu einzusetzen.
Aus der DE-OS 23 38 239 ist eine integrierte Halbleiter
schaltung mit Transistoren unterschiedlicher Schwellenspannung
und ein Verfahren zu ihrer Herstellung bekannt. Dabei werden
die Schwellenspannungen der Feldeffekttransistoren auf ver
schiedene Werte eingestellt, indem die aus Halbleitermaterial
bestehenden Gate-Elektroden der beiden IGFET's auf unterschied
lichen Leitungstyp dotiert werden. Zur Ausbildung solcher Gate-
Elektroden wird zunächst die eine Gate-Elektrode mit dem einen,
beispielsweise P-Dotierstoff dotiert, wobei die andere Gate-
Elektrode durch eine Maskierungsschicht abgedeckt ist.
Anschließend wird die zuvor dotierte Gate-Elektrode mit einer
Maskierungsschicht abgedeckt, die andere Gate-Elektrode freige
legt und mit dem anderen, beispielsweise N-Dotierstoff dotiert.
Ein ähnliches Verfahren ist aus der DE-OS 21 42 050
bekannt. Daraus werden ebenfalls Maskierungsschichten für die
selektive Ausbildung unterschiedlich dotierter Gate-Elektroden
eingesetzt.
Die bekannten Verfahren haben den Nachteil, daß relativ
aufwendige Maskierungsschritte zur Herstellung von IGFET's
unterschiedlicher Schwellspannung notwendig sind.
Aufgabe der Erfindung ist dementsprechend, ein Verfahren
zur Herstellung von zwei IGFET's mit unterschiedlichen Schwell
spannungen der bekannten Art anzugeben, das mit relativ wenig
Maskierungsschritten ausführbar ist.
Diese Aufgabe wird mit einem Verfahren nach dem Oberbe
griff des Patentanspruches 1 gelöst, das erfindungsgemäß die im
Kennzeichenteil angegebenen Verfahrensschritte vorsieht.
Im folgenden wird die Erfindung anhand des in den Figuren
dargestellten Ausführungsbeispiels beschrieben und näher erläu
tert.
In den Fig. a) und b) sind die wesentlichen Verfahrens
merkmale schematisch dargestellt.
Ein N-Siliciumkörper 1 mit einer relativ niedrigen Dotier
stoffdichte von z. B. weniger als 5×1016 Atome/cm3 wird oxi
diert, so daß man einen dicken Oxidfilm 2 für die Isolation
erzeugt. Nach Herstellung eines Gate-Oxidfilmes 3 in Vertiefun
gen des Oxidfilmes 2 wird ein eigenleitender polykristalliner
Siliciumfilm 6 bzw. 6′ mit Hilfe eines chemischen Abscheidever
fahrens aufgebracht. Anschließend wird ein Maskenoxidfilm 7 mit
Hilfe eines chemischen Verfahrens auf einer vorgegebenen Fläche
erzeugt. Unter Benutzung des Oxidfilms 7 als Maske wird der
polykristalline Siliciumfilm 6′ mit N-Störstoff, beispielsweise
mit Phosphor oder mit Arsen, selektiv dotiert, wobei die
Dotierstoffdichte hoch ist und beispielsweise mehr als 5×1016
Atome/cm3 beträgt. Auf diese Weise entsteht der polykristalline
N-Siliciumfilm 6′.
Nach dem Entfernen des Maskenoxidfilmes 7 wird mit Hilfe
eines Photoätzverfahrens eine Gate-Elektrode aus polykristalli
nem Silicium hergestellt; durch thermisches Eindiffundieren
eines P-Dotierstoffes, beispielsweise von Bor, werden Source-
und Drain-Gebiete 4 und 5 hergestellt, deren Dotierstoff-Kon
zentration gering ist und beispielsweise weniger als 3,3×1018
Atome/cm3 beträgt. Dabei wird die Dichte des N-Dotierstoffes
für die N-Dotierung des polykristallinen Filmes 6′ so gewählt,
daß sie um mindestens das 1,5fache höher ist als die Dichte
des P-Dotierstoffs, mit dem der polykristalline Siliciumfilm 6′
danach dotiert wird. Bei dem nachfolgenden P-Dotierschritt wird
also nur soviel P-Dotierstoff eindiffundiert, daß die N-Leitfä
higkeit der polykristallinen Silicium-Gate-Elektrode 6′ erhal
ten bleibt. Mit dieser Auswahl der Dotierstoff-Konzentration
ist es möglich, daß trotz des nachfolgenden P-Diffusionsschrit
tes, bei dem P-Dotierstoff sowohl in die Silicium-Gate-Elek
trode 6′ des OGFET Q 1 wie auch in die Silicium-Gate-Elektrode 6
des zweiten IGFET Q 2 eingebracht wird, die Gate-Elektrode 6′
des ersten IGFET Q 1 den N-Leitungstyp beibehält. Bei diesem
Verfahren ist nur ein Maskierungsschritt notwendig, es wird
nämlich nur die Oxidmaske 7 während des ersten N-Dotierschrit
tes benötigt, um das Gebiet des zweiten IGFET Q 2 abzudecken.
Claims (2)
- Verfahren zum Herstellen einer intergrierten Halbleitervor richtung mit zwei IGFET's (Q 1, Q 2) mit Gate-Elektroden aus Halbleitermaterial, die sich voneinander im Leitungstyp unter scheiden, mit folgenden Schritten:
- a) Ausbilden eines Gate-Isolierfilms (3) und einer poly kristallinen, eigenleitenden Halbleiterschicht (6, 6′) auf einem Substrat (1) des ersten Leitungstyps,
- b) Aufbringen einer Maskenschicht (7) auf vorbestimmten Teilen der polykristallinen eigenleitenden Halbleiterschicht
- c) Einführen eines Störstoffs des ersten Leitungstyps in den Teil der polykristallinen eigenleitenden Halbleiterschicht, der nicht von der Maskenschicht (7) bedeckt ist,
- d) Entfernen von Teilen der polykristallinen Halbleiter schicht zum Bilden eines polykristallinen Halbleiterschicht teils vom ersten Leitungstyp und eines polykristallinen eigen leitenden Halbleiterschichtteils,
- e) Einführen eines Störstoffs vom zweiten Leitungstyp in ausgewählte Teile des Substrats zum Bilden von Source- und Drainbereichen (4, 5) und zur Dotierung des polykristallinen eigenleitenden Halbleiterschichtteils,
- dadurch gekennzeichnet, daß
- f) als erster Leitungstyp der n-Typ und zweiter Leitungstyp der p-Typ verwendet wird,
- g) die Dichte des Störstoffs vom ersten (n)-Leitungstyp um mindestens das 1,5fache höher ist als die Dichte des Stör stoffs vom zweiten (p)-Typ, und daß
- h) im Verfahrensschritt e) der Störstof vom zweiten (p)- Leitungstyp gleichzeitig in den polykristallinen Halbleiter schichtteil vom ersten (n)-Leitungstyp und in den polykristal linen eigenleitenden Halbleiterschichtteil eingeführt wird, um die Gate-Elektroden der beiden IGFET's (Q 1, Q 2) zu bilden.
Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2544478A JPS54119653A (en) | 1978-03-08 | 1978-03-08 | Constant voltage generating circuit |
JP3554578A JPS54129348A (en) | 1978-03-29 | 1978-03-29 | Constant voltage output circuit |
JP3924278A JPS54132753A (en) | 1978-04-05 | 1978-04-05 | Referential voltage generator and its application |
JP11172278A JPS5539411A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generator |
JP11172478A JPS5539412A (en) | 1978-09-13 | 1978-09-13 | Insulating gate field effect transistor integrated circuit and its manufacture |
JP11171978A JPS5539607A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
JP11171878A JPS5539606A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
JP11171778A JPS5539605A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
JP11172378A JPS5538677A (en) | 1978-09-13 | 1978-09-13 | Semiconductor memory with function of detecting power failure |
JP11172078A JPS5539608A (en) | 1978-09-13 | 1978-09-13 | Reference voltage generation device |
JP11172578A JPS5539413A (en) | 1978-09-13 | 1978-09-13 | Schmitt trigger circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
DE2954543C2 true DE2954543C2 (de) | 1990-04-12 |
Family
ID=27581900
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19792906527 Ceased DE2906527A1 (de) | 1978-03-08 | 1979-02-20 | Bezugsspannungsgenerator |
DE2954543A Expired - Lifetime DE2954543C2 (de) | 1978-03-08 | 1979-02-20 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19792906527 Ceased DE2906527A1 (de) | 1978-03-08 | 1979-02-20 | Bezugsspannungsgenerator |
Country Status (10)
Country | Link |
---|---|
CA (1) | CA1149081A (de) |
CH (2) | CH657712A5 (de) |
DE (2) | DE2906527A1 (de) |
FR (1) | FR2447036B1 (de) |
GB (1) | GB2016801B (de) |
HK (4) | HK8084A (de) |
IT (1) | IT1111987B (de) |
MY (4) | MY8400375A (de) |
NL (1) | NL7901335A (de) |
SG (1) | SG41784G (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2494519A1 (fr) * | 1980-11-14 | 1982-05-21 | Efcis | Generateur de courant integre en technologie cmos |
US4347476A (en) * | 1980-12-04 | 1982-08-31 | Rockwell International Corporation | Voltage-temperature insensitive on-chip reference voltage source compatible with VLSI manufacturing techniques |
JPS58221418A (ja) * | 1982-06-18 | 1983-12-23 | Hitachi Ltd | 基準電圧発生装置 |
JPS5940393A (ja) * | 1982-08-31 | 1984-03-06 | Nec Corp | メモリ回路 |
IT1179823B (it) * | 1984-11-22 | 1987-09-16 | Cselt Centro Studi Lab Telecom | Generatore di tensione differenziale di rifferimento per circuiti integrati ad alimentazione singola in tecnologia nmos |
FR2628547B1 (fr) * | 1988-03-09 | 1990-12-28 | Sgs Thomson Microelectronics | Generateur stabilise de fourniture de tension de seuil de transistor mos |
GB2291512B (en) * | 1991-11-15 | 1996-12-11 | Nec Corp | Reference voltage generating circuit to be used for a constant voltage circuit formed of fets |
DE69213213T2 (de) * | 1992-04-16 | 1997-01-23 | Sgs Thomson Microelectronics | Genauer MOS-Schwellenspannungsgenerator |
US5468666A (en) * | 1993-04-29 | 1995-11-21 | Texas Instruments Incorporated | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip |
EP1102319B1 (de) | 1999-11-19 | 2010-05-26 | STMicroelectronics Srl | Herstellungsverfahren für elektronische Bauelemente mit Hochspannungs-MOS- und EEPROM-Transistoren |
US8385147B2 (en) * | 2010-03-30 | 2013-02-26 | Silicon Storage Technology, Inc. | Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features |
CN110707151B (zh) * | 2019-11-13 | 2023-04-07 | 江苏丽隽功率半导体有限公司 | 一种静电感应晶闸管及其制作方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2142050A1 (de) * | 1970-08-21 | 1972-03-30 | Motorola Inc | Halbleiteranordnung, vorzugsweise Feldeffekttransistor |
DE2338239A1 (de) * | 1972-09-22 | 1974-03-28 | Hitachi Ltd | Integrierte halbleiterschaltung |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3673471A (en) * | 1970-10-08 | 1972-06-27 | Fairchild Camera Instr Co | Doped semiconductor electrodes for mos type devices |
DE2050320A1 (de) * | 1970-10-13 | 1972-04-20 | Siemens Ag | Halbleiteranordnung |
US3995177A (en) * | 1973-01-02 | 1976-11-30 | Fairchild Camera And Instrument Corporation | Electronic watch |
US3975648A (en) * | 1975-06-16 | 1976-08-17 | Hewlett-Packard Company | Flat-band voltage reference |
US4100437A (en) * | 1976-07-29 | 1978-07-11 | Intel Corporation | MOS reference voltage circuit |
-
1979
- 1979-02-19 CH CH1621/79A patent/CH657712A5/de not_active IP Right Cessation
- 1979-02-20 IT IT20368/79A patent/IT1111987B/it active
- 1979-02-20 DE DE19792906527 patent/DE2906527A1/de not_active Ceased
- 1979-02-20 DE DE2954543A patent/DE2954543C2/de not_active Expired - Lifetime
- 1979-02-20 FR FR7904226A patent/FR2447036B1/fr not_active Expired
- 1979-02-20 NL NL7901335A patent/NL7901335A/xx not_active Application Discontinuation
- 1979-02-20 CA CA000321955A patent/CA1149081A/en not_active Expired
- 1979-03-06 GB GB7907817A patent/GB2016801B/en not_active Expired
-
1984
- 1984-01-24 HK HK80/84A patent/HK8084A/xx not_active IP Right Cessation
- 1984-06-04 SG SG417/84A patent/SG41784G/en unknown
- 1984-12-31 MY MY1984375A patent/MY8400375A/xx unknown
-
1985
- 1985-02-19 CH CH1928/85A patent/CH672391B5/de unknown
- 1985-05-09 HK HK364/85A patent/HK36485A/xx not_active IP Right Cessation
- 1985-05-09 HK HK363/85A patent/HK36385A/xx not_active IP Right Cessation
- 1985-05-09 HK HK351/85A patent/HK35185A/xx unknown
- 1985-12-30 MY MY672/85A patent/MY8500672A/xx unknown
- 1985-12-30 MY MY671/85A patent/MY8500671A/xx unknown
- 1985-12-30 MY MY658/85A patent/MY8500658A/xx unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2142050A1 (de) * | 1970-08-21 | 1972-03-30 | Motorola Inc | Halbleiteranordnung, vorzugsweise Feldeffekttransistor |
DE2338239A1 (de) * | 1972-09-22 | 1974-03-28 | Hitachi Ltd | Integrierte halbleiterschaltung |
Non-Patent Citations (2)
Title |
---|
"Electronics", 30.8.1971, S. 38-43 * |
"IEEE J. of Sol. St. Circ.", Bd. SC-13, No. 3, 1978, S. 285-294 * |
Also Published As
Publication number | Publication date |
---|---|
GB2016801A (en) | 1979-09-26 |
CH672391B5 (de) | 1990-05-31 |
HK36385A (en) | 1985-05-17 |
FR2447036A1 (fr) | 1980-08-14 |
GB2016801B (en) | 1983-02-02 |
DE2906527A1 (de) | 1979-10-18 |
FR2447036B1 (fr) | 1986-10-17 |
MY8500672A (en) | 1985-12-31 |
CH657712A5 (de) | 1986-09-15 |
MY8500671A (en) | 1985-12-31 |
MY8400375A (en) | 1984-12-31 |
IT7920368A0 (it) | 1979-02-20 |
IT1111987B (it) | 1986-01-13 |
MY8500658A (en) | 1985-12-31 |
SG41784G (en) | 1985-03-08 |
CA1149081A (en) | 1983-06-28 |
HK36485A (en) | 1985-05-17 |
HK35185A (en) | 1985-05-17 |
HK8084A (en) | 1984-02-01 |
NL7901335A (nl) | 1979-09-11 |
CH672391GA3 (de) | 1989-11-30 |
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