CN203180865U - Time-delay generation circuit with pulse width adjustable - Google Patents
Time-delay generation circuit with pulse width adjustable Download PDFInfo
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- CN203180865U CN203180865U CN 201320171645 CN201320171645U CN203180865U CN 203180865 U CN203180865 U CN 203180865U CN 201320171645 CN201320171645 CN 201320171645 CN 201320171645 U CN201320171645 U CN 201320171645U CN 203180865 U CN203180865 U CN 203180865U
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Abstract
The utility model relates to a time-delay generation circuit with pulse width adjustable, comprising a host and a single-chip microcomputer connected together. The time-delay generation circuit with pulse width adjustable also includes an input level converting circuit, a time-delay circuit and a pulse width adjusting circuit which are connected in sequence, wherein the time-delay circuit is also connected with the single-chip microcomputer, the output of the single-chip microcomputer is also connected with the pulse width adjusting circuit, after signals in the time-delay circuit are output by a first programmable delayer, one signal is output and connected to a second programmable delayer of the pulse width adjusting circuit, the other signal is connected to a third programmable delayer of the pulse width adjusting circuit through a first NOT gate, the second programmable delayer and the third programmable delayer are simultaneously connected to the NAND gate in the pulse width adjusting circuit through output, and output is achieved through a second NOT gate. According to the time-delay generation circuit with pulse width adjustable, pulse width is flexibly adjusted, large scope of time delay is obtained in an ultra-high speed digital framing camera, pulse width is accurately adjusted, image shooting at a nanosecond grade interval and nanosecond grade exposure time are achieved.
Description
Technical field
The utility model relates to the circuit structure of precision time delay, is the adjustable time-delay generation circuit of pulse duration concretely.
Background technology
Follow the progress and development of science and technology, high speed camera is widely used in all trades and professions field, and especially the research in natural science field and military field has huge impetus.For example Unite States Standard and technology Consiglio Nazionale Delle Ricerche (IT) T, Piazzale Aido Moro-00185 Rome, Italy adopt ultrahigh speed numeral framing camera to finish the high-rate laser sedimentation experiment of Nd:YAG selection film.Same Fluid Physics Inst., China Engineering Physics Academy also utilizes SpeedCam VISARIO digital camera system at home, has successfully taken the process of bullet flight and the overall process of explosive charge.Therefore to research and the improvement of ultrahigh speed numeral framing camera, will promote science and technology development.
Along with going deep into of all trades and professions research, to more at a high speed, the demand of the more excellent camera of performance is also increasing.Traditional ultrahigh speed camera mainly comprises High-speed Rotating-mirror Camera, optical compensation formula high speed camera and intermittent high-speed camera.Because the design limitations of traditional high speed camera self, cause its performance and novel ultrahigh speed numeral framing camera that big gap is arranged, all can not be equal to it aspect a lot of in dynamic range, spatial resolution, temporal resolution etc., and volume and weight is also bigger, and it is convenient inadequately to operate.
Usually use the pulse delay generator as the shutter control signal of ultrahigh speed numeral framing camera, the shutter system that is made of the pulse delay generator is as the key function part of ultrahigh speed numeral framing camera, and its speed speed depends on interval between pulse duration, pulse and the pulse that triggers shutter release and the indexs such as amplitude of pulse.And existing pulse delay unit exists that time-delay can not be adjusted flexibly, pulse duration is non-adjustable and precision shortcomings such as high stability is not strong.Therefore, propose a kind of thinking that designs clock, and provide a kind of realistic plan through research, producing nanosecond pulse and pulse interval and producing the broad-adjustable pulse signal of nanosecond pulse is to have very much meaning.
The utility model content
The utility model provides a kind of pulse duration adjustable time-delay generation circuit, be used for obtaining large-scale time delay at ultrahigh speed numeral framing camera, accurate regulating impulse width is again realized image taking and the nanosecond time for exposure in the nanosecond time interval.
The time-delay generation circuit that the utility model pulse duration is adjustable, include be connected main frame and single-chip microcomputer, also have the incoming level change-over circuit, delay circuit and the pulse width regulating circuit that are linked in sequence, wherein delay circuit also is connected with single-chip microcomputer, the output of single-chip microcomputer also be connected pulse width regulating circuit and connect; Wherein in the delay circuit by after first programmable delayer output, the output of one road signal is connected to second programmable delayer of pulse width regulating circuit, another road signal is connected to the 3rd programmable delayer of pulse width regulating circuit by first not gate, after second programmable delayer and the 3rd programmable delayer are exported the NAND gate that is connected in the pulse width regulating circuit simultaneously, export through second not gate.
Compare at present to the time-delay generation circuit that comprises main frame and single-chip microcomputer, the utility model has increased incoming level change-over circuit, delay circuit and pulse width regulating circuit.The triggering signal of input changes into through the incoming level change-over circuit and enters delay circuit behind the Transistor-Transistor Logic level (logic level) and delay time, form certain pulse duration by pulse width regulating circuit then, the amount of time-delay is by Single-chip Controlling, main frame links to each other with single-chip microcomputer, external command is input to single-chip microcomputer, simultaneously delay data, pulse width data etc. is input in each programmable delayer.By being used of three programmable delayers and gate, utilize single-chip microcomputer configuration two-stage time-delay linear chain, the first order that first programmable delayer constitutes is overall time-delay, the time delayed signal of output is divided into the two-way time-delay, wherein one tunnel process inverter carries out inverse, regulate the time of delay of two delayers in the second level, the pulse duration that can accurately regulate acquisition.The benefit of doing like this is the maximum performance of the performance of delayer both can be able to be obtained large-scale time delay, again accurate regulating impulse width.
Preferably, pulse width regulating circuit output back connects shaping circuit.Shaping circuit can regular pulse width regulating circuit output level, convert thereof into the output of standard Transistor-Transistor Logic level.
Further, the peripheral circuit that is connected of first programmable delayer, second programmable delayer and the 3rd programmable delayer includes voltage and moves back even circuit and power supply circuits.Peripheral circuit can according to circuit common usual manner arrange, this is a kind of conventional structure in various circuit, does not do detailed description at this.
Further, main frame is by CAN(controller local area network) bus connection single-chip microcomputer.
Further, single-chip microcomputer is by SPI(synchronous serial Peripheral Interface) bus connection delay circuit.
After tested, the time-delay generation circuit that pulse duration of the present utility model is adjustable, can pulse-width adjust flexibly, in ultrahigh speed numeral framing camera, obtain large-scale time delay, and accurate regulating impulse width, realized image taking and the nanosecond time for exposure in the nanosecond time interval.
Below in conjunction with the embodiment of embodiment, foregoing of the present utility model is described in further detail again.But this should be interpreted as that the scope of the above-mentioned theme of the utility model only limits to following example.Do not breaking away under the above-mentioned technological thought situation of the utility model, various replacements or change according to ordinary skill knowledge and customary means are made all should be included in the scope of the present utility model.
Description of drawings
Fig. 1 is the block diagram of the adjustable time-delay generation circuit of the utility model pulse duration.
Fig. 2 is the connection diagram of delay circuit and pulse width regulating circuit among Fig. 1.
Fig. 3 is the Time-Series analysis figure of Fig. 1 delay circuit and pulse width regulating circuit.
Embodiment
The adjustable time-delay generation circuit of pulse duration of the present utility model as shown in Figure 1, include the controller local area network by CAN() main frame and single-chip microcomputer that bus connects, also have the incoming level change-over circuit, delay circuit, pulse width regulating circuit and the shaping circuit that are linked in sequence.Wherein delay circuit is by SPI(synchronous serial Peripheral Interface) bus also is connected with single-chip microcomputer, the output of single-chip microcomputer also be connected the pulse width regulating circuit connection.The triggering signal of input changes into through the incoming level change-over circuit and enters delay circuit behind the Transistor-Transistor Logic level (logic level) and delay time, and forms certain pulse duration by pulse width regulating circuit then, and the amount of time-delay is by Single-chip Controlling.Shaping circuit can regular pulse width regulating circuit output level, convert thereof into the output of standard Transistor-Transistor Logic level.
As shown in Figure 2, after the first programmable delayer U2 output by the DS1021-25 type in the delay circuit, the output of one road signal is connected to the DS1021-25 type second programmable delayer U4 of pulse width regulating circuit, another road signal is connected to DS1021-25 type the 3rd programmable delayer U5 of pulse width regulating circuit by the first not gate U3A, after the 3rd programmable delayer U5 of the second programmable delayer U4 and DS1021-25 type exports the NAND gate U1B that is connected in the pulse width regulating circuit simultaneously, export through the second not gate U3B.DS1021-25 is 8 bit digital programmable delayers, adopts the high-performance bipolar technology, aims at high-speed figure and Analog Circuit Design, and minimum delay precision can reach the 250ps(psec, namely 10
-12Second), positive 5V power supply power supply, the full scale reference time delay is 10ns(nanosecond)～73.75ns.Adopt the XC164CM single-chip microcomputer of Infineon, respectively three DS1021-25 programmable delayers are carried out Serial Control by three spi bus.Amount of delay determines by the data that single-chip microcomputer writes programmable delayer, and the data that write programmable delayer by change realize the change of amount of delay, carry out data setting by CAN bus and main-machine communication.The peripheral circuit that the first programmable delayer U2, the second programmable delayer U4 are connected with the 3rd programmable delayer U5 includes voltage and moves back even circuit and power supply circuits.Peripheral circuit can according to circuit common usual manner arrange, this is a kind of conventional structure in various circuit, does not do detailed description at this.
By being used of three programmable delayers and gate, utilize single-chip microcomputer configuration two-stage time-delay linear chain, the first order that the first programmable delayer U2 constitutes is overall time-delay, the time delayed signal of output is divided into the two-way time-delay, wherein one tunnel process inverter carries out inverse, regulate the time of delay of two delayers in the second level, the pulse duration that can accurately regulate acquisition.The benefit of doing like this is the maximum performance of the performance of delayer both can be able to be obtained large-scale time delay, again accurate regulating impulse width.
Concrete time-delay process is: the triggering signal of outside input by the shaping of incoming level change-over circuit after 1 port of the first programmable delayer U2 of the input time delay circuit time delays that carries out pulse.NAND gate U1B, the second programmable delayer U4 and the 3rd programmable delayer U5 form pulse width regulating circuit, signal after pulse signal is delayed time through the first programmable delayer U2 enters the second programmable delayer U4 and delays time, be that the first not gate U3A of 74ALS04 enters the 3rd programmable delayer U5 after oppositely and delays time by model simultaneously, enter NAND gate U1B through the row NAND operation from the signal of the second programmable delayer U4 and the 3rd programmable delayer U5 output, oppositely exported the back by the second not gate U3B again from the signal of NAND gate U1B output, can carry out the adjustment of pulse duration in this way.
As shown in Figure 3, in the test, waveform a for the input pulse signal through the output signal behind the incoming level change-over circuit, tw1 is the pulse duration of output.Waveform b is the output pulse after delaying time through the first order, and td1 is delay time.Waveform c is that td2 is delay time through the output pulse behind the second programmable delayer U4 of pulse width regulating circuit.Waveform d is oppositely delayed time by the 3rd programmable delayer U5 the back through the first not gate U3A after the first order time-delay output, and td3 is delay time.The pulse of waveform c and waveform d output carry out after by NAND gate U1B and the second not gate U3B with computing after output pulse waveform e, the pulse duration tw2 of waveform e is td3-td2, the pulse duration of output pulse can be adjusted like this by the delay time of adjusting td3 and td2, the delay time of output pulse can be adjusted by the delay time of adjusting td2.
Test is learnt, the time-delay generation circuit that pulse duration of the present utility model is adjustable, can pulse-width adjust flexibly, in ultrahigh speed numeral framing camera, obtain large-scale time delay, and accurate regulating impulse width, realized image taking and the nanosecond time for exposure in the nanosecond time interval.
Claims (5)
1. the adjustable time-delay generation circuit of pulse duration, include be connected main frame and single-chip microcomputer, it is characterized by: also have the incoming level change-over circuit, delay circuit and the pulse width regulating circuit that are linked in sequence, wherein delay circuit also is connected with single-chip microcomputer, the output of single-chip microcomputer also be connected pulse width regulating circuit and connect; Wherein in the delay circuit by after first programmable delayer (U2) output, the output of one road signal is connected to second programmable delayer (U4) of pulse width regulating circuit, another road signal is connected to the 3rd programmable delayer (U5) of pulse width regulating circuit by first not gate (U3A), second programmable delayer (U4) is exported through second not gate (U3B) after exporting the NAND gate (U1B) that is connected in the pulse width regulating circuit simultaneously with the 3rd programmable delayer (U5).
2. the adjustable time-delay generation circuit of pulse duration as claimed in claim 1 is characterized by: pulse width regulating circuit output back connection shaping circuit.
3. the adjustable time-delay generation circuit of pulse duration as claimed in claim 1 or 2, it is characterized by: the peripheral circuit that first programmable delayer (U2), second programmable delayer (U4) and the 3rd programmable delayer (U5) are connected includes voltage and moves back even circuit and power supply circuits.
4. the adjustable time-delay generation circuit of pulse duration as claimed in claim 1 or 2 is characterized by: main frame connects single-chip microcomputer by the CAN bus.
5. the adjustable time-delay generation circuit of pulse duration as claimed in claim 1 or 2, it is characterized by: single-chip microcomputer connects delay circuit by spi bus.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320171645 CN203180865U (en) | 2013-04-08 | 2013-04-08 | Time-delay generation circuit with pulse width adjustable |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320171645 CN203180865U (en) | 2013-04-08 | 2013-04-08 | Time-delay generation circuit with pulse width adjustable |
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| CN 201320171645 Expired - Fee Related CN203180865U (en) | 2013-04-08 | 2013-04-08 | Time-delay generation circuit with pulse width adjustable |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124948A (en) * | 2014-07-03 | 2014-10-29 | 濮阳市立圆汽车电器有限公司 | Pulse width modulating circuit |
| CN109905103A (en) * | 2019-02-22 | 2019-06-18 | 西安交通大学 | A kind of stretch circuit combining digital logical operation based on delay |
| CN110618360A (en) * | 2019-10-09 | 2019-12-27 | 国网江苏省电力有限公司电力科学研究院 | Lightning impulse discharge test system of liquid dielectric medium |
| CN116707496A (en) * | 2023-08-01 | 2023-09-05 | 青岛本原微电子有限公司 | High-resolution pulse signal processing circuit |
-
2013
- 2013-04-08 CN CN 201320171645 patent/CN203180865U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124948A (en) * | 2014-07-03 | 2014-10-29 | 濮阳市立圆汽车电器有限公司 | Pulse width modulating circuit |
| CN104124948B (en) * | 2014-07-03 | 2017-01-18 | 濮阳市立圆汽车电器有限公司 | Pulse width modulating circuit |
| CN109905103A (en) * | 2019-02-22 | 2019-06-18 | 西安交通大学 | A kind of stretch circuit combining digital logical operation based on delay |
| CN110618360A (en) * | 2019-10-09 | 2019-12-27 | 国网江苏省电力有限公司电力科学研究院 | Lightning impulse discharge test system of liquid dielectric medium |
| CN116707496A (en) * | 2023-08-01 | 2023-09-05 | 青岛本原微电子有限公司 | High-resolution pulse signal processing circuit |
| CN116707496B (en) * | 2023-08-01 | 2023-10-13 | 青岛本原微电子有限公司 | High-resolution pulse signal processing circuit |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130904 Termination date: 20150408 |
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| EXPY | Termination of patent right or utility model |