CN109800192A - Electronic equipment, fpga chip and its interface circuit - Google Patents
Electronic equipment, fpga chip and its interface circuit Download PDFInfo
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- CN109800192A CN109800192A CN201910044803.XA CN201910044803A CN109800192A CN 109800192 A CN109800192 A CN 109800192A CN 201910044803 A CN201910044803 A CN 201910044803A CN 109800192 A CN109800192 A CN 109800192A
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Abstract
The invention belongs to technical field of integrated circuits, provide a kind of electronic equipment, fpga chip and its interface circuit.In the present invention, by using include clock module, initialization module, data path module, command/address control access module and input and output logic module interface circuit, so that the reading and writing data between FPGA and DDR SDRAM is completed in the modules cooperation in the interface circuit, so that data bridge of the interface circuit as FPGA and DDR SDRAM between the two, it may make that both FPGA and DDR SDRAM are effectively combined, improve the applicability of both FPGA and DDR SDRAM combination.
Description
Technical field
The invention belongs to IC design technical field more particularly to a kind of electronic equipment, fpga chip and its interface
Circuit.
Background technique
Currently, with the development of integrated circuit, one side field programmable gate array (Field-Programmable
Gate Array, FPGA) as one of specific integrated circuit field semi-custom circuit, because its is restructural, logical resource is rich
Rich, the features such as input/output interface is flexible, is widely used in various fields.Another aspect Double Data Rate (Double Data
Rate, DDR) synchronous DRAM (Synchronous Dynamic Random Access Memory, SDRAM) because
Its high data rate is equally used widely in many fields.The spy of the characteristics of based on FPGA and DDR SDRAM
Point, the combination of the two can be widely applied to the multiple fields such as image/video sequential control system, industrial control system.
Since DDR SDRAM has stringent timing requirements, logic control is complex, so that DDR
SDRAM needs special interface circuit to realize the read-write operation of data, that is, is required to transmit the Memory Controller Hub of FPGA
The signals such as the order, address, the data that come over are sent to DDR SDRAM according to the format and electrical characteristic of DDR defined, and connect
Receive the reading data of DDR SDRAM.
Currently, in order to ensure it is accurate, steadily DDR SDRAM is written and read, the prior art mainly by using
Data decimation pulse DQS stone in FPGA is realized.Although however, DQS stone can be adjusted clock phase, and then making
The centre that DQS signal edge is in DDR SDRAM data is obtained, to guarantee that data stabilization is transmitted, but for certain without embedded
For the FPGA device of DQS stone, will be unable to generate offset phase signal is synchronous and sampled signal, so will so that FPGA and
Both DDR SDRAM are unable to get effective combination, thereby reduce the applicability of both FPGA and DDR SDRAM combination.
Therefore, it is necessary to a kind of technical solution is provided, to solve the above technical problems.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of electronic equipment, fpga chip and its interface circuit, conduct
The data bridge of FPGA and DDR SDRAM between the two improves so that both FPGA and DDR SDRAM are effectively combined
The applicability that both FPGA and DDR SDRAM are combined.
The first aspect of the embodiment of the present invention provides a kind of interface circuit, for the double-speed for fpga chip and outside
Communication interface is provided between rate memory, the interface circuit includes:
Clock module, for generating high speed write offset clocks signals, high fast reading offset clocks signals and low-speed clock letter
Number；
Initialization module is connect with the clock module and the double rate memory, in the low speed
It works, and after the double rate memory powers on, the double rate memory is carried out initial under the action of clock signal
Change setting；
Memory Controller Hub and input and output in data path module, with the clock module, the fpga chip are patrolled
Module connection is collected, for working under the action of the low-speed clock signal, and when the Memory Controller Hub in the fpga chip
When carrying out data writing operation to the double rate memory, receive the Memory Controller Hub transmission in the fpga chip writes number
According to and data enable signal, and write data and the data enable signal are sent to input and output logic module；Work as institute
When stating the Memory Controller Hub in fpga chip and carrying out reading data manipulation to the double rate memory, the data path module
The data that the input and output logic module is read from the double rate memory are received, and the data of reading are sent to
Memory Controller Hub in the fpga chip；
Memory Controller Hub and institute in command/address control access module, with the clock module, the fpga chip
The connection of input and output logic module is stated, for working under the action of the low-speed clock signal, and receives the fpga chip
In the read/write command that sends of Memory Controller Hub and address signal, and the read/write command and address signal be sent to described
Input and output logic module；
The input and output logic module, connect with the clock module and the double rate memory, is used for
It works under the action of the low-speed clock signal, and under the action of the high speed write offset clocks signals, according to the data
Enable signal, the write order and the address signal write the data of writing that the Memory Controller Hub in the fpga chip is sent
Enter the double rate memory, and under the action of the high fast reading offset clocks signals, is believed according to read command and address
Number by the data stored in the double rate memory read.
The second aspect of the embodiment of the present invention provides a kind of fpga chip, and the fpga chip includes above-mentioned interface electricity
Road.
The third aspect of the embodiment of the present invention provides a kind of electronic equipment, and the electronic equipment includes above-mentioned FPGA core
Piece.
Existing beneficial effect is the embodiment of the present invention compared with prior art: the present invention is by using including clock mould
Block, initialization module, data path module, command/address control access module and input and output logic module interface electricity
Road, so that the reading and writing data between FPGA and DDR SDRAM is completed in the modules cooperation in the interface circuit, so that should
Data bridge of the interface circuit as FPGA and DDR SDRAM between the two, may make that both FPGA and DDR SDRAM are had
Effect combines, and improves the applicability of both FPGA and DDR SDRAM combination.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the modular structure schematic diagram of interface circuit provided by one embodiment of the invention；
Fig. 2 is the modular structure schematic diagram of interface circuit provided by another embodiment of the present invention.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, to understand thoroughly the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention also may be implemented in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, in case unnecessary details interferes description of the invention.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
In order to illustrate technical solutions according to the invention, the following is a description of specific embodiments:
Fig. 1 shows the modular structure of interface circuit 1 provided by one embodiment of the invention, for ease of description, only shows
Go out part related to the present embodiment, details are as follows:
As shown in Figure 1, interface circuit 1 provided by the embodiment of the present invention is used for as fpga chip 4 and external Double Data Rate
Communication interface is provided between memory DDR SDRAM 2, and the interface circuit 1 includes: clock module 10, initialization module
11, data path module 12, command/address control access module 13 and input and output logic module 14.
Wherein, clock module 10, for generating high speed write offset clocks signals, high fast reading offset clocks signals and low speed
Clock signal；
Initialization module 11 is connect, in low-speed clock signal with clock module 12 and double rate memory 2
The lower work of effect, and after double rate memory 2 powers on, Initialize installation is carried out to double rate memory 2；
Memory Controller Hub 3 and input and output logic in data path module 12, with clock module 10, fpga chip 4
Module 14 connects, for working under the action of low-speed clock signal, and when the Memory Controller Hub 3 in fpga chip 4 is to double
When rate memory 2 carries out data writing operation, receiving write data and data that the Memory Controller Hub 3 in fpga chip 4 is sent makes
Can signal, and data will be write and data enable signal is sent to input and output logic module 14；When the memory control in fpga chip 4
When device 3 processed carries out reading data manipulation to double rate memory 2, data path module 12 receive input and output logic module 14 from
The data read in double rate memory 2, and the data of reading are sent to the Memory Controller Hub 3 in fpga chip 4；
Memory Controller Hub 3 and input in command/address control access module 13, with clock module 10, fpga chip 4
It exports logic module 14 to connect, for working under the action of low-speed clock signal, and receives the controller 3 in fpga chip 4
The read/write command and address signal of transmission, and read/write command and address signal are sent to input and output logic module 14；
Input and output logic module 14 is connect with clock module 10 and double rate memory 2, in low-speed clock
It works under the action of signal, and under the action of high speed write offset clocks signals, according to data enable signal, write order and ground
Location signal writes data write-in double rate memory 2 for what the Memory Controller Hub 3 in fpga chip 4 was sent, and in high fast reading
Under the action of offset clocks signals, the data stored in double rate memory 2 are read according to read command and address signal.
When it is implemented, the Memory Controller Hub 3 in fpga chip 4 send write data, read data, various orders, signal
It is that the demand designed when fpga chip 4 is accordingly arranged according to user carries out Deng, i.e. memory control in fpga chip 4
Data that device 3 processed was sent write, read data, various orders, signal are that the function of being implemented according to fpga chip 4 carries out；This
Outside, it should be noted that in the present embodiment, initialization module 11, data path module 12 in interface circuit 1, order/ground
It is interconnected two-by-two between 14 4 modules of location control access module 13 and input and output logic module, only to part in Fig. 1
Connection relationship is illustrated.
It should be noted that in embodiments of the present invention, DDR SDRAM is in synchronous DRAM
It is developed on the basis of (Synchronous Dynamic Random Access Memory, SDRAM).Specifically, SDRAM
Transmission primaries data within a clock cycle, and while transmitting data, was carried out data transmission in the rising stage of clock,
And DDR SDRAM is then that data twice are transmitted in a clock cycle, it can respectively be transmitted in the rising stage of clock and decline phase
Data, because of referred to herein as Double Data Rate synchronous DRAM.
In the present embodiment, the present invention is by using including clock module 10, initialization module 11, data path module
12, the interface circuit 1 of command/address control access module 13 and input and output logic module 14, so that the interface circuit 1 can
It is properly received the order of Memory Controller Hub 3 in fpga chip 4, and the letter for meeting timing and sequence requirement is provided to DDR SDRAM
Number, and then will realize the reading and writing data between fpga chip and DDR SDRAM, solve the FPGA device in no DQS stone
On the problem of DDR SDRAM still can be used, while reducing design scale, reduce costs, and facilitate scheduling and planning,
FPGA product is effectively improved in the market competitiveness of multiple fields.
Further, as one embodiment of the present invention, as shown in Fig. 2, clock module 10 includes phaselocked loop 100, divides
Frequency device 101 and clock start and stop device 102.
Wherein, phaselocked loop 100 are connect with input and output logic module 14, for generate high fast reading offset clocks signals and
High speed write offset clocks signals；
Frequency divider 101, with phaselocked loop 100, initialization module 11, data path module 12, command/address control access mould
Block 13 and input and output logic module 14 connect, for according to high fast reading offset clocks signals or high speed write offset clocks signals
Generate corresponding low-speed clock signal；
Clock start and stop device 102, connect with frequency divider 101, for control frequency divider 101 export low-speed clock signal when
Between.
When it is implemented, when phaselocked loop 100 generates high speed according to the external original low-speed clock signal for providing equipment offer
Clock signal, which is divided into the low-speed clock signal of same clock domain by frequency divider 101, and the low-speed clock is believed
Number it is sent to initialization module 11, data path module 12, command/address control access module 13 and input and output logic mould
Block 14, so that initialization module 11, data path module 12, command/address control access module 13 and input and output logic
Module 14 synchronizes sex work, and clock start and stop device 102 is then under the control of external synchronization module or synchronizer, when being responsible for
The exact time that clock is released is in turn to be used for synchronization system, while other submodules also use this low-speed clock to believe as clock
Number ensure the synchronism of system.
It should be noted that in embodiments of the present invention, when interface circuit 1 works in write data mode, phaselocked loop 100
According to the external original low-speed clock signal generation high speed write offset clocks signals for providing equipment and providing, and frequency divider 101 then will
High speed write offset clocks signals frequency dividing is in the first low-speed clock signal with clock domain；When interface circuit 1 works in reading data
When mode, phaselocked loop 100 generates high fast reading offset clocks signals according to the external original low-speed clock signal for providing equipment offer,
And frequency divider 101 is then by the high fast reading offset clocks signals frequency dividing in the second low-speed clock signal with clock domain.
In the present embodiment, by using the clock mould including phaselocked loop 100, frequency divider 101 and clock start and stop device 102
Block 10, so that phaselocked loop 100 can produce the high-speed clock signal during reading and writing data, frequency divider 101 is according to the high-frequency clock
Signal generates defeated for controlling initialization module 11, data path module 12, command/address control access module 13 and input
The clock signal that logic module 14 works asynchronously out is avoided and is connect so that the modules in the interface circuit 1 can work asynchronously
Mouth circuit 1 can not carry out correct reading and writing data because the work of its internal module is asynchronous.
Further, initial module 11 is when carrying out Initialize installation to double rate memory 2, the Initialize installation packet
It includes but is not limited to reset, clock is enabled and the setting such as register configuration.
Further, as one embodiment of the present invention, interface circuit 1 provided by the present embodiment can also be in logarithm
According to reading calibration is carried out before being read, i.e., input and output logic module 14 is under the action of high speed write offset clocks signals, root
Fixed data is written to the preset address of double rate memory 2 according to write order, and in the effect of high fast reading offset clocks signals
Under, fixed data is read according to read command, and Double Data Rate is deposited according to the fixed data of write-in and the fixed data of reading
Reservoir 2 carries out reading calibration；It should be noted that preset address and fixed data can be designed according to user and be configured, herein not
Do concrete restriction.
When it is implemented, before carrying out read operation to the data in double speed multiplying power memory 2, input and output logic mould
Fixed number is written to the address A of double rate memory 2 under the action of high speed write offset clocks signals, according to write order in block 14
According to B, and under the action of high fast reading offset clocks signals, fixed data B is read according to read command.By the fixed data
After B is read, the fixed data B of reading is compared by input and output logic module 14 with the fixed data B of write-in, if the two phase
Together, then show that data read procedure is errorless, if the two has deviation, export corresponding message, to realize the school to reading data course
It is quasi-.
In the present embodiment, interface circuit 1 provided by the invention can be mentioned by reading calibration before reading to data
Before know that reading data course with the presence or absence of failure, and then can make corresponding rescue measure in time, avoid depositing because of reading data course
Cause effectively be combined between fpga chip and double rate memory in problem.
It further, include deserializer in input and output logic module 14 as one embodiment of the present invention, it should
The high-frequency clock port of deserializer is connect with clock module 10, when input and output logic module 14 is by double rate memory
When the data stored in 2 are read, deserializer carries out center point sampling to the data of reading, and then guarantees data readout
The accuracy of middle sampling, so that it is guaranteed that data are read accurately.
It further, include parallel-to-serial converter in input and output logic module 14 as one embodiment of the present invention, and
The high-frequency clock port of string converter is connect with clock module 10, when input and output logic module 14 will be in fpga chip 4
When what memory controller 3 was sent writes data write-in double rate memory 2, parallel-to-serial converter deviates the data and high speed write of write-in
Clock signal synchronizes processing.
It should be noted that in the present embodiment, deserializer and parallel-to-serial converter respectively with existing serioparallel exchange
Device is identical with working principle with the circuit structure of parallel-to-serial converter, specifically refers to the prior art, details are not described herein again.
Further, as one embodiment of the present invention, data path module 12 is also used to when interior in fpga chip 4
When memory controller 3 carries out data writing operation to double rate memory 2, the transmission of Memory Controller Hub 3 received in fpga chip 4 is write
Delay parameter, and caching process is carried out to data are write according to delay parameter is write.
Further, as one embodiment of the present invention, data path module 12 is also used to the memory in fpga chip 4
When controller 3 carries out reading data manipulation to double rate memory 2, receives the reading that input and output logic module 14 is sent and be delayed and join
Number, and caching process is carried out to the data of reading according to delay parameter is read.
The working principle of interface circuit 1 provided by the present invention is illustrated by taking circuit shown in Fig. 2 as an example below,
Details are as follows:
As shown in Fig. 2, needing to be counted in fpga chip with double speed multiplying power memory 2 in some application scenarios
When according to read-write communication, the phaselocked loop 100 in clock module 10 generates high fast reading offset clocks according to externally input clock signal
The high-speed clock signal of signal and high speed write offset clocks signals, the frequency divider 101 in clock module 10 believe the high-frequency clock
It number is divided, to generate corresponding low-speed clock signal, and the low-speed clock signal is sent to initialization module 11, data
Channel module 12, command/address control access module 13 and input and output logic module 14, so that initialization module 11, number
According to channel module 12, command/address control access module 13 and input and output logic module 14 according to the low-speed clock signal
Work is synchronized, while the high fast reading offset clocks signals and high speed write offset clocks signals are sent to input and output logic
Module 14.
When initialization module 11 works under the action of the low-speed clock signal that clock module 10 provides, initialization module
11 main function is to carry out initial configuration to double speed multiplying power memory 2.When the Memory Controller Hub in fpga chip 4 is according to tool
The memory when order that user designs in body application scenarios needs to write data into double rate memory 2, in fpga chip 4
Controller 3, which will be sent, to be write data accordingly and writes data enable signal to data path module 12, and data path module 12 then will
This, which is write data and writes data enable signal, is sent to input and output logic module 14；Meanwhile the Memory Controller Hub in fpga chip 4
3 will also send corresponding write order and data writing address signal to command/address control access module 13, command/address
The write order and data writing address signal are then sent to input and output logic module 14 by control access module 13；It is defeated when inputting
When logic module 14 works under the low-speed clock signal that clock module 10 is sent out, input and output logic module 14 will be in high speed
Under the action of writing offset clocks signals, according to data enable signal, write order and data writing address signal by fpga chip 4
In the appropriate address for writing data write-in double rate memory 2 that sends of Memory Controller Hub 3 in, to realize fpga chip and double
Communication is written in data between times rate memory 2.
When the Memory Controller Hub in fpga chip 4 is needed according to the order that user in concrete application scene designs from double-speed
When reading data in rate memory 2, the Memory Controller Hub 3 in fpga chip 4 will send corresponding read command and data are read
Address signal to command/address control access module 13, command/address control access module 13 then reads the read command and data
Address signal is sent to input and output logic module 14 out, and input and output logic module 14 is receiving the read command and data reading
Out after address signal, the data that appropriate address in double rate memory 2 is stored are read, and are sent out by data path module 12
The Memory Controller Hub 3 in fpga chip 4 is given, to realize that it is logical that the data between fpga chip and double rate memory 2 are read
Letter.
In the present embodiment, interface circuit 1 provided by the invention provides Memory Controller Hub 3 and the outside of fpga chip 4
Physical layer definition and interface between DDR SDRAM 2, by the life for receiving the Memory Controller Hub 3 in fpga chip 4
It enables, and is provided to DDR SDRAM 2 and meet the signal of timing and sequence requirement, so that FPGA device is not being limited by model
In the case of, it can be combined with DDR SDRAM 2, and structure is simple, low cost, logic small scale, debugging facilitate
While achieve the purpose that high-speed transfer so that the combination of both fpga chip and DDR SDRAM can be applied to more
Occasion so that in the application scenarios that DDR SDRAM particle and fpga chip are used in combination, specific apparent advantage.
Further, the present invention also provides a kind of fpga chip 4, which includes interface circuit 1 and Memory control
Device 3.It should be noted that by fpga chip 4 provided by the embodiment of the present invention interface circuit 1 and Fig. 1 to Fig. 2
Interface circuit 1 is identical, therefore, the concrete operating principle of the interface circuit 1 in fpga chip 4 provided by the embodiment of the present invention,
It can refer to the detailed description previously with regard to Fig. 1 and Fig. 2, details are not described herein again.
Further, the present invention also provides a kind of electronic equipment, which includes fpga chip.It needs to illustrate
It is, by interface circuit included by the fpga chip 4 in electronic equipment provided by the embodiment of the present invention and Fig. 1 and Fig. 2 institute
The interface circuit 1 shown is identical, therefore, the specific works of the fpga chip 4 in electronic equipment provided by the embodiment of the present invention
Principle can refer to the detailed description previously with regard to Fig. 1 and Fig. 2, and details are not described herein again.
In the present invention, it is controlled by using including clock module, initialization module, data path module, command/address
The interface circuit of channel module and input and output logic module, so that FPGA is completed in the modules cooperation in the interface circuit
Reading and writing data between DDR SDRAM, so that data of the interface circuit as FPGA and DDR SDRAM between the two
Bridge may make that both FPGA and DDR SDRAM are effectively combined, and improve the suitable of both FPGA and DDR SDRAM combination
The property used.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of interface circuit, special for providing communication interface between fpga chip and the double rate memory of outside
Sign is that the interface circuit includes:
Clock module, for generating high speed write offset clocks signals, high fast reading offset clocks signals and low-speed clock signal；
Initialization module is connect with the clock module and the double rate memory, for believing in the low-speed clock
It works under the action of number, and after the double rate memory powers on, initialization is carried out to the double rate memory and is set
It sets；
Memory Controller Hub and input and output logic mould in data path module, with the clock module, the fpga chip
Block connection, for working under the action of the low-speed clock signal, and when the Memory Controller Hub in the fpga chip is to institute
When stating double rate memory and carrying out data writing operation, receive that Memory Controller Hub in the fpga chip sends write data and
Data enable signal, and write data and the data enable signal are sent to input and output logic module；When described
When Memory Controller Hub in fpga chip carries out reading data manipulation to the double rate memory, the data path module is connect
The data that the input and output logic module is read from the double rate memory are received, and the data of reading are sent to institute
State the Memory Controller Hub in fpga chip；
Memory Controller Hub in command/address control access module, with the clock module, the fpga chip and described defeated
Enter to export logic module connection, for working under the action of the low-speed clock signal, and receives in the fpga chip
The read/write command and address signal that Memory Controller Hub is sent, and the read/write command and address signal are sent to the input
Export logic module；
The input and output logic module, connect with the clock module and the double rate memory, for described
It works under the action of low-speed clock signal, and under the action of the high speed write offset clocks signals, it is enabled according to the data
Signal, the write order and the address signal write data write-in institute for what the Memory Controller Hub in the fpga chip was sent
Double rate memory is stated, and under the action of the high fast reading offset clocks signals, it will according to read command and address signal
The data stored in the double rate memory are read.
2. interface circuit according to claim 1, which is characterized in that the clock module includes:
Phaselocked loop is connect with the input and output logic module, for generating the high fast reading offset clocks signals and the height
Literary sketch offset clocks signals；
Frequency divider, with the phaselocked loop, the initialization module, the data path module, the command/address control access
Module and input and output logic module connection, for inclined according to the high fast reading offset clocks signals or the high speed write
Shift clock signal generates corresponding low-speed clock signal；
Clock start and stop device, connect with the frequency divider, and the time of the low-speed clock signal is exported for controlling the frequency divider.
3. interface circuit according to claim 1 or 2, which is characterized in that the initialization module is to the Double Data Rate
The Initialize installation that memory carries out includes reset, clock enables and register configuration.
4. interface circuit according to claim 3, which is characterized in that the input and output logic module is in the high speed write
Under the action of offset clocks signals, fixed number is written to the preset address of the double rate memory according to the write order
According to, and under the action of the high fast reading offset clocks signals, the fixed data is read according to the read command, and according to
The fixed data of write-in and the fixed data of reading carry out reading calibration to the double rate memory.
5. interface circuit according to claim 1, which is characterized in that include going here and there and turning in the input and output logic module
The high-frequency clock port of parallel operation, the deserializer is connect with the clock module, when the input and output logic module will
When the data stored in the double rate memory are read, the deserializer carries out central point to the data of reading and adopts
Sample.
6. interface circuit according to claim 1, which is characterized in that include in the input and output logic module and go here and there turn
The high-frequency clock port of parallel operation, the parallel-to-serial converter is connect with the clock module, when the input and output logic module will
When what the Memory Controller Hub in the fpga chip was sent writes the data write-in double rate memory, the parallel-to-serial converter
Processing is synchronized to the data and the high speed write offset clocks signals of write-in.
7. interface circuit according to claim 1, which is characterized in that the data path module is also used to as the FPGA
When Memory Controller Hub in chip carries out data writing operation to the double rate memory, receive interior in the fpga chip
Delay parameter is write in memory controller transmission, and according to the delay parameter of writing to write data progress caching process.
8. interface circuit according to claim 1, which is characterized in that the data path module is also used to the FPGA core
When Memory Controller Hub in piece carries out reading data manipulation to the double rate memory, the input and output logic module is received
The reading delay parameter of transmission, and caching process is carried out according to data of the reading delay parameter to reading.
9. a kind of fpga chip, which is characterized in that the FPGA device includes interface as claimed in any one of claims 1 to 8
Circuit.
10. a kind of electronic equipment, which is characterized in that the electronic equipment includes fpga chip as claimed in claim 9.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347621A (en) * | 2019-06-24 | 2019-10-18 | 广东高云半导体科技股份有限公司 | The FPGA and storage system being connect with PSRAM memory |
| CN110727637A (en) * | 2019-12-18 | 2020-01-24 | 广东高云半导体科技股份有限公司 | FPGA chip and electronic equipment |
| CN112017702A (en) * | 2019-05-31 | 2020-12-01 | 龙芯中科技术有限公司 | Memory interface circuit, PHY chip and processor |
| CN114003526A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Method and circuit for accessing write data path of on-chip memory control unit |
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