CN205195677U - Take clock circuit of failure detection mechanism - Google Patents

Abstract

The utility model discloses a take clock circuit of failure detection mechanism, including a capacitor charging and discharging circuit, the 2nd capacitor charging and discharging circuit, first comparator, second comparator, reference voltage input, a control of charge and discharge circuit, the 2nd control of charge and discharge circuit, inefficacy detection circuitry, third NOR gate and second NAND gate. The utility model discloses a clock circuit need not can produce clock pulse with the help of the peripheral circuit, and the practicality is strong, the utility model discloses a two way control of charge and discharge circuit accurate controls, two way capacitor charging and discharging circuit are work in turn, can obtain accurate clock waveform, increase inefficacy detection circuitry assurance circuit is normally worked, has improved the stability of clock circuit. The utility model relates to a field that but, take clock circuit of failure detection mechanism wide application in application clock crystal oscillator circuit such as microcontroller, data signal communication and processing.

Description

A kind of clock circuit with failure detection mechanisms

Technical field

The utility model relates to the field that clock crystal oscillator circuit is used in microcontroller, digital signal communication and process etc., especially a kind of clock circuit with failure detection mechanisms.

Background technology

In the digital information epoch now, increasing microcontroller and microprocessing are used in the middle of our live and work.Large to the controller on aerospace craft, the little main control chip to a Domestic electric rice cooker, these all can use Digital Signals treatment technology and microcontroller chip, and just can not lack clock crystal oscillator circuit as carrier and support to the process of signal.

In the digital control technology early stage of development, clock can adopt the various ways such as crystal oscillator, ring oscillator, C vibration.And crystal oscillator and LC vibration etc. need to realize by peripheral components more; Ring oscillator also needs phase-locked loop to keep the accuracy of clock; Utilize the charge characteristic of electric capacity, and control its charging voltage and obtain the method for corresponding clock cycle, in this way, when applying cmos and designing clock oscillator, common problem is exactly that accuracy is low and occur that inefficacy causes circuit cisco unity malfunction to profit.

Utility model content

In order to solve the problems of the technologies described above, the purpose of this utility model is to provide a kind of clock circuit with failure detection mechanisms.

The technical scheme that the utility model adopts is: a kind of clock circuit with failure detection mechanisms, comprise the first capacitor charge and discharge circuit, second capacitor charge and discharge circuit, first comparator, second comparator, reference voltage input, first charge-discharge control circuit, second charge-discharge control circuit, failure detection circuit, first logic judgment module and the second logic judgment module, the output of described first capacitor charge and discharge circuit is connected with the first input end of the first comparator, the output of described second capacitor charge and discharge circuit is connected with the first input end of the second comparator, described reference voltage input is connected with the second input of the first comparator and the second input of the second comparator respectively, the output of described first comparator is connected with the first input end of the first charge-discharge control circuit, the output of described second comparator is connected with the first input end of the second charge-discharge control circuit, first output of described first charge-discharge control circuit is connected with the second input of the second charge-discharge control circuit, first output of described second charge-discharge control circuit is connected with the second input of the first charge-discharge control circuit, second output of described first charge-discharge control circuit is connected with the first input end of failure detection circuit, second output of described second charge-discharge control circuit is connected with the second input of failure detection circuit, first output of described failure detection circuit is connected with the second input of the first logic judgment module, first output of described first charge-discharge control circuit is connected with the first input end of the first logic judgment module, the output of described first logic judgment module is connected with the input of the second capacitor charge and discharge circuit, second output of described failure detection circuit is connected with the first input end of the second logic judgment module, first output of described second charge-discharge control circuit is connected with the second input of the second logic judgment module, the output of described second logic judgment module is connected with the input of the first capacitor charge and discharge circuit.

Further, described first logic judgment module is the 3rd NOR gate, and described second logic judgment module is the second NAND gate.

Further, described failure detection circuit comprises the first NOR gate, first buffer, first not gate, first NAND gate and the second NOR gate, the first input end of described first NOR gate is the first input end of failure detection circuit, second input of described first NOR gate is the second input of failure detection circuit, the output of described first NOR gate is connected with the input of the first buffer, the output of described first buffer is connected with the input of the first not gate, the output of described first not gate is connected with the second input of the first NAND gate, the first input end of described first NAND gate is the first Enable Pin, the output of described first NAND gate is the first output of failure detection circuit, the output of described first buffer is connected with the first input end of the second NOR gate, second input of described second NOR gate is the second Enable Pin, the output of described second NOR gate is the second output of failure detection circuit.

Further, described first capacitor charge and discharge circuit comprises a PMOSFET, first resistance, one NMOSFET and the first electric capacity, the source electrode of a described PMOSFET is connected with one end of the first resistance, the drain electrode of a described PMOSFET connects power supply, the other end of described first resistance is connected with one end of the first electric capacity, the other end of described first resistance is connected with the drain electrode of a NMOSFET, the other end ground connection of described first electric capacity, the source electrode of a described NMOSFET is connected with the other end of the first electric capacity, the grid of a described NMOSFET is connected with the grid of a PMOSFET, the grid of a described PMOSFET is the input of the first capacitor charge and discharge circuit, the other end of described first resistance is the output of the first capacitor charge and discharge circuit, described second capacitor charge and discharge circuit comprises the 2nd PMOSFET, second resistance, 2nd NMOSFET and the second electric capacity, the circuit of described second capacitor charge and discharge circuit connects and to be connected with the circuit of the first capacitor charge and discharge circuit, the grid of described 2nd PMOSFET is the input of the second capacitor charge and discharge circuit, the other end of described second resistance is the output of the second capacitor charge and discharge circuit.

Further, described first charge-discharge control circuit comprises the 3rd PMOSFET, 4th PMOSFET, 5th PMOSFET, 6th PMOSFET, second not gate, second buffer, 3rd not gate, 3rd NMOSFET, 4th NMOSFET, 5th NMOSFET, 6th NMOSFET, the drain electrode of described 3rd PMOSFET connects power supply, the grid of described 3rd PMOSFET is connected with the source electrode of the 5th PMOSFET, the source electrode of described 3rd PMOSFET is connected with the drain electrode of the 3rd NMOSFET, the grid of described 3rd NMOSFET is connected with the drain electrode of the 5th NMOSFET, the grid of described 3rd NMOSFET is the first input end of the first charge-discharge control circuit, the source ground of described 3rd NMOSFET, the source ground of described 5th NMOSFET, the grid of described 5th NMOSFET is connected with the output of the 3rd not gate, the drain electrode of described 3rd NMOSFET is connected with the input of the second not gate, the drain electrode of described 4th PMOSFET connects power supply, the source electrode of described 4th PMOSFET is connected with the input of the second not gate, the grid of described 4th PMOSFET is connected with the output of the second not gate, the output of described second not gate is connected with the input of the second buffer, the output of described second not gate is the first output of the first charge-discharge control circuit, the output of described second buffer is connected with the grid of the 5th PMOSFET, the output of described second buffer is the second output of the first charge-discharge control circuit, the drain electrode of described 5th PMOSFET connects power supply, the grid of described 5th PMOSFET is connected with the grid of the 4th NMOSFET, the source electrode of described 5th PMOSFET is connected with the source electrode of the 4th NMOSFET, the source electrode of described 4th NMOSFET is connected with the drain electrode of the 6th NMOSFET, the source ground of described 6th NMOSFET, the grid of described 6th NMOSFET is the second input of the first charge-discharge control circuit, the source electrode of described 5th PMOSFET is connected with the input of the 3rd not gate, the drain electrode of described 6th PMOSFET connects power supply, the source electrode of described 6th PMOSFET is connected with the input of the 3rd not gate, the grid of described 6th PMOSFET is connected with the output of the 3rd not gate, the circuit structure of described second charge-discharge control circuit is identical with the first charge-discharge control circuit.

Further, described clock circuit also comprises output waveform shaping circuit, and the output of described second NAND gate is connected with the input of output waveform shaping circuit.

The beneficial effects of the utility model are: clock circuit of the present utility model is without the need to producing clock pulse by peripheral circuit, practical; The utility model accurately controls the alternation of two-way capacitor charge and discharge circuit by two-way charge-discharge control circuit, can obtain accurate clock waveform; Increase failure detection circuit and ensure that circuit normally works, improve the stability of clock circuit.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, embodiment of the present utility model is described further:

Fig. 1 is a specific embodiment circuit diagram of a kind of clock circuit with failure detection mechanisms of the utility model;

Fig. 2 is a specific embodiment clock waveform figure of a kind of clock circuit with failure detection mechanisms of the utility model;

Fig. 3 is an a kind of specific embodiment circuit diagram with charge-discharge control circuit in the clock circuit of failure detection mechanisms of the utility model;

Fig. 4 is an a kind of specific embodiment circuit diagram with failure detection circuit in the clock circuit of failure detection mechanisms of the utility model.

Embodiment

It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.

A kind of clock circuit with failure detection mechanisms, with reference to figure 1, comprise the first capacitor charge and discharge circuit 1, second capacitor charge and discharge circuit 2, first comparator P1, the second comparator P2, reference voltage input VREF, the first charge-discharge control circuit P3, the second charge-discharge control circuit P4, failure detection circuit P5, the first logic judgment module and the second logic judgment module, in the present embodiment, described first logic judgment module is the 3rd NOR gate P6, and described second logic judgment module is the second NAND gate P7.

Further, described first capacitor charge and discharge circuit 1 comprises a PMOSFETMP1, first resistance R1, one NMOSFETMN1 and the first electric capacity C1, the source electrode of a described PMOSFETMP1 is connected with one end of the first resistance R1, the drain electrode of a described PMOSFETMP1 connects power supply, the other end of described first resistance R1 is connected with one end of the first electric capacity C1, the other end of described first resistance R1 is connected with the drain electrode of a NMOSFETMN1, the other end ground connection of described first electric capacity C1, the source electrode of a described NMOSFETMN1 is connected with the other end of the first electric capacity C1, the grid of a described NMOSFETMN1 is connected with the grid of a PMOSFETMP1, the grid of a described PMOSFETMP1 is the input of the first capacitor charge and discharge circuit 1, the other end of described first resistance R1 is the output of the first capacitor charge and discharge circuit 1, described second capacitor charge and discharge circuit 2 comprises the 2nd PMOSFETMP2, second resistance R2, 2nd NMOSFETMN2 and the second electric capacity C2, the circuit of described second capacitor charge and discharge circuit 2 connects and to be connected with the circuit of the first capacitor charge and discharge circuit 1, the grid of described 2nd PMOSFETMP2 is the input of the second capacitor charge and discharge circuit 2, the other end of described second resistance R2 is the output of the second capacitor charge and discharge circuit 2.

Described first capacitor charge and discharge circuit 1 and the second capacitor charge and discharge circuit 2 produce the charging voltage V1 and V2 that are used for the first electric capacity C1 and the second electric capacity C2 respectively.

The output of described first capacitor charge and discharge circuit 1 is connected with the first input end of the first comparator P1, the output of described second capacitor charge and discharge circuit 2 is connected with the first input end of the second comparator P2, described reference voltage input VREF is connected with second input of the first comparator P1 and second input of the second comparator P2 respectively, the first input end of described first comparator P1 and the first input end of the second comparator P2 are in-phase input end, and second input of described first comparator P1 and second input of the second comparator P2 are inverting input.

With reference to figure 2, described first comparator P1 and the second comparator P2 compares described charging voltage V1 and V2 respectively, controls the time of clock height pulse.

Further, with reference to figure 3, described first charge-discharge control circuit P3 comprises the 3rd PMOSFETM31, 4th PMOSFETM41, 5th PMOSFETM51, 6th PMOSFETM61, second not gate P91, second buffer P101, 3rd not gate P111, 3rd NMOSFETN31, 4th NMOSFETN41, 5th NMOSFETN51 and the 6th NMOSFETN61, the drain electrode of described 3rd PMOSFETM31 connects power supply, the grid of described 3rd PMOSFETM31 is connected with the source electrode of the 5th PMOSFETM51, the source electrode of described 3rd PMOSFETM31 is connected with the drain electrode of the 3rd NMOSFETN31, the grid of described 3rd NMOSFETN31 is connected with the drain electrode of the 5th NMOSFETN51, the grid of described 3rd NMOSFETN31 is the first input end A1 of the first charge-discharge control circuit P3, the source ground of described 3rd NMOSFETN31, the source ground of described 5th NMOSFETN51, the grid of described 5th NMOSFETN51 is connected with the output of the 3rd not gate P111, the drain electrode of described 3rd NMOSFETN31 is connected with the input of the second not gate P91, the drain electrode of described 4th PMOSFETM41 connects power supply, the source electrode of described 4th PMOSFETM41 is connected with the input of the second not gate, the grid of described 4th PMOSFET is connected with the output of the second not gate P91, the output of described second not gate P91 is connected with the input of the second buffer P101, the output of described second not gate P91 is the first output Y1 of the first charge-discharge control circuit P3, the output of described second buffer P101 is connected with the grid of the 5th PMOSFETM51, the output of described second buffer P101 is the second output Z1 of the first charge-discharge control circuit P3, the drain electrode of described 5th PMOSFETM51 connects power supply, the grid of described 5th PMOSFETM51 is connected with the grid of the 4th NMOSFETN41, the source electrode of described 5th PMOSFETM51 is connected with the source electrode of the 4th NMOSFETN41, the source electrode of described 4th NMOSFETN41 is connected with the drain electrode of the 6th NMOSFETN61, the source ground of described 6th NMOSFETN61, the grid of described 6th NMOSFETN61 is the second input B1 of the first charge-discharge control circuit P3, the source electrode of described 5th PMOSFETM51 is connected with the input of the 3rd not gate P111, the drain electrode of described 6th PMOSFETM61 connects power supply, the source electrode of described 6th PMOSFETM61 is connected with the input of the 3rd not gate P111, the grid of described 6th PMOSFETM61 is connected with the output of the 3rd not gate P111, the circuit structure of described second charge-discharge control circuit P4 is identical with the first charge-discharge control circuit P3, described second charge-discharge control circuit P4 comprises first input end A2, second input B2, first output Y2 and the second output Z2.

The output of described first comparator P1 is connected with the first input end A1 of the first charge-discharge control circuit P3, the output of described second comparator P2 is connected with the first input end A2 of the second charge-discharge control circuit P4, the first output Y1 of described first charge-discharge control circuit P3 is connected with the second input B2 of the second charge-discharge control circuit P4, and the first output Y2 of described second charge-discharge control circuit P4 is connected with the second input B1 of the first charge-discharge control circuit P3.

The principle that described charge-discharge control circuit realizes charge and discharge control replaces and to obtain electric work by controlling described first capacitor charge and discharge circuit 1 and the second capacitor charge and discharge circuit 2 and realize, and specific implementation process is as follows:

When the charging voltage V1 that described first capacitor charge and discharge circuit 1 produces reaches reference voltage V ref, the output voltage V3 of described first comparator P1 starts to rise, namely the voltage that the first input end A1 of described first charge-discharge control circuit P3 inputs starts to raise, after input voltage V3 rises to the threshold voltage of described 3rd NMOSFETN31, described 3rd NMOSFETN31 is switched on, the drain terminal voltage of described 4th PMOSFETM41 is pulled low to 0, the signal that then described second not gate P91 inputs is 0, described second not gate P91 exports high level, namely the first output Y1 of described first charge-discharge control circuit P3 exports high level 1, due to described 3rd PMOSFETM31, the latch effect of the 4th PMOSFETM41 and the 6th PMOSFETM61, the first output Y1 of described first charge-discharge control circuit P3 continues to export high level 1, the second output Z1 of described first charge-discharge control circuit P3 also exports high level 1 due to the effect of the second buffer P101, described high level 1 is by becoming logical zero after the 3rd NOR gate P6, and open described 2nd PMOSFETMP2, namely the first capacitor charge and discharge circuit 1 stops charging to the first electric capacity C1, second capacitor charge and discharge circuit 2 starts to charge to the second electric capacity C2.Processing procedure with the first capacitor charge and discharge circuit 1 is the same, when the charging voltage V2 that the second capacitor charge and discharge circuit 2 produces reaches reference voltage V ref, the first output Y2 of described second charge-discharge control circuit P4 exports high level, the then second input B1 input high level 1 of described first charge-discharge control circuit P3, described high level 1 is passed to the 3rd not gate P111, described 3rd not gate P111 produces a high impulse and passes to the 5th NMOSFETN51, change the lock high state of the first output Y1 of the first charge-discharge control circuit P3, described first charge-discharge control circuit P3 is resetted, start next round dock cycles.

Two-way capacitor charge and discharge circuit is utilized to compare with same voltage respectively, the charge completion signal of first via capacitor charge and discharge circuit 1 is as the charging start signal of the second road capacitor charge and discharge circuit 2, the charge completion signal of the second road capacitor charge and discharge circuit 2 is as the charging start signal of first via capacitor charge and discharge circuit 1, so repeatedly alternately obtain the height burst length of clock cycle, accurate clock pulse can be obtained, improve the accuracy of clock circuit.

In this clock implementation, the condition of most critical is, two-way capacitor charge and discharge circuit will interlock to obtain electric work, and this ensures that clock can circulate the primary condition of normal work.But there is simulation department and digital logic portion in circuit, when having external interference or inner generation abnormal conditions, once two-way capacitor charge and discharge circuit carries out or be only have the action of overlapping charging that dock cycles will be made to cause interruption simultaneously, clock was lost efficacy, and therefore the utility model adds failure detection circuit.

Further, with reference to figure 4, described failure detection circuit P5 comprises the first NOR gate P51, first buffer P52, first not gate P53, first NAND gate P54 and the second NOR gate P55, the first input end of described first NOR gate P51 is the first input end A3 of failure detection circuit P5, second input of described first NOR gate P51 is the second input B3 of failure detection circuit P5, the output of described first NOR gate P51 is connected with the input of the first buffer P52, the output of described first buffer P52 is connected with the input of the first not gate P53, the described output of the first not gate P53 is connected with second input of the first NAND gate P54, the first input end of described first NAND gate P54 is the first Enable Pin EN, the output of described first NAND gate P54 is the first output Y3 of failure detection circuit P5, the output of described first buffer P52 is connected with the first input end of the second NOR gate P55, second input of described second NOR gate P55 is the second Enable Pin ENB, the output of described second NOR gate P55 is the second output Z3 of failure detection circuit P5.

The second output Z1 of described first charge-discharge control circuit P3 is connected with the first input end A3 of failure detection circuit P5, the second output Z2 of described second charge-discharge control circuit P4 is connected with the second input B3 of failure detection circuit P5, the first output Y3 of described failure detection circuit P5 is connected with second input of the 3rd NOR gate P6, the first output Y1 of described first charge-discharge control circuit P3 is connected with the first input end of the 3rd NOR gate P6, the output of described 3rd NOR gate P6 is connected with the input of the second capacitor charge and discharge circuit 2, the second output Z3 of described failure detection circuit P5 is connected with the first input end of the second NAND gate P7, the first output Y2 of described second charge-discharge control circuit P4 is connected with second input of the second NAND gate P7, the output of described second NAND gate P7 is connected with the input of the first capacitor charge and discharge circuit 1.

The effect of described failure detection circuit P5 is real-time testing state in clock running, when detecting that the trend that two-way discharge and recharge starts can appear controlling in two comparators simultaneously, pressure restarts discharge and recharge, two-way charge-discharge circuit is made to carry out normal logical order, thus clock circuit can work normally, avoid clock to quit work causing system having a strong impact on.The utility model with the addition of described failure detection circuit P5, improves the stability that circuit produces precision clock pulse.

Described failure detection circuit P5 is the situation that the state of signal that the second output Z2 of the signal that exports of the second output Z1 by detecting the first charge-discharge control circuit P3 and the second charge-discharge control circuit P4 exports judges whether overlapping charging.

When the signal of two-way charge-discharge control circuit input is 0 simultaneously, two-way capacitor charge and discharge circuit is described simultaneously to capacitor charging, after described failure detection circuit P5 process, the first output Y3 of described failure detection circuit P5 exports high level 1, the second output Z3 output low level 0 of described failure detection circuit P5, by difference output logic 0 and 1 after described 3rd NOR gate P6 and the second NAND gate P7, then described second capacitor charge and discharge circuit 2 is started working, described first capacitor charge and discharge circuit 1 quits work, and starts next round clock failure detection.

Further, described clock circuit also comprises output waveform shaping circuit P8, and the output of described second NAND gate P7 is connected with the input of output waveform shaping circuit P8.

As shown in Figure 1, above-mentioned waveform is done further process by described output waveform shaping circuit P8, can obtain the clock signal clk of standard.

More than that better enforcement of the present utility model is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to the utility model spirit, and these equivalent distortion or replacement are all included in the application's claim limited range.

Claims (6)

1. the clock circuit with failure detection mechanisms, it is characterized in that: comprise the first capacitor charge and discharge circuit, second capacitor charge and discharge circuit, first comparator, second comparator, reference voltage input, first charge-discharge control circuit, second charge-discharge control circuit, failure detection circuit, first logic judgment module and the second logic judgment module, the output of described first capacitor charge and discharge circuit is connected with the first input end of the first comparator, the output of described second capacitor charge and discharge circuit is connected with the first input end of the second comparator, described reference voltage input is connected with the second input of the first comparator and the second input of the second comparator respectively, the output of described first comparator is connected with the first input end of the first charge-discharge control circuit, the output of described second comparator is connected with the first input end of the second charge-discharge control circuit, first output of described first charge-discharge control circuit is connected with the second input of the second charge-discharge control circuit, first output of described second charge-discharge control circuit is connected with the second input of the first charge-discharge control circuit, second output of described first charge-discharge control circuit is connected with the first input end of failure detection circuit, second output of described second charge-discharge control circuit is connected with the second input of failure detection circuit, first output of described failure detection circuit is connected with the second input of the first logic judgment module, first output of described first charge-discharge control circuit is connected with the first input end of the first logic judgment module, the output of described first logic judgment module is connected with the input of the second capacitor charge and discharge circuit, second output of described failure detection circuit is connected with the first input end of the second logic judgment module, first output of described second charge-discharge control circuit is connected with the second input of the second logic judgment module, the output of described second logic judgment module is connected with the input of the first capacitor charge and discharge circuit.

2. the clock circuit of band failure detection mechanisms according to claim 1, is characterized in that: described first logic judgment module is the 3rd NOR gate, and described second logic judgment module is the second NAND gate.

3. the clock circuit of band failure detection mechanisms according to claim 2, it is characterized in that: described failure detection circuit comprises the first NOR gate, first buffer, first not gate, first NAND gate and the second NOR gate, the first input end of described first NOR gate is the first input end of failure detection circuit, second input of described first NOR gate is the second input of failure detection circuit, the output of described first NOR gate is connected with the input of the first buffer, the output of described first buffer is connected with the input of the first not gate, the output of described first not gate is connected with the second input of the first NAND gate, the first input end of described first NAND gate is the first Enable Pin, the output of described first NAND gate is the first output of failure detection circuit, the output of described first buffer is connected with the first input end of the second NOR gate, second input of described second NOR gate is the second Enable Pin, the output of described second NOR gate is the second output of failure detection circuit.

4. the clock circuit of band failure detection mechanisms according to claim 3, it is characterized in that: described first capacitor charge and discharge circuit comprises a PMOSFET, first resistance, one NMOSFET and the first electric capacity, the source electrode of a described PMOSFET is connected with one end of the first resistance, the drain electrode of a described PMOSFET connects power supply, the other end of described first resistance is connected with one end of the first electric capacity, the other end of described first resistance is connected with the drain electrode of a NMOSFET, the other end ground connection of described first electric capacity, the source electrode of a described NMOSFET is connected with the other end of the first electric capacity, the grid of a described NMOSFET is connected with the grid of a PMOSFET, the grid of a described PMOSFET is the input of the first capacitor charge and discharge circuit, the other end of described first resistance is the output of the first capacitor charge and discharge circuit, described second capacitor charge and discharge circuit comprises the 2nd PMOSFET, second resistance, 2nd NMOSFET and the second electric capacity, the circuit of described second capacitor charge and discharge circuit connects and to be connected with the circuit of the first capacitor charge and discharge circuit, the grid of described 2nd PMOSFET is the input of the second capacitor charge and discharge circuit, the other end of described second resistance is the output of the second capacitor charge and discharge circuit.

5. the clock circuit of band failure detection mechanisms according to claim 4, it is characterized in that: described first charge-discharge control circuit comprises the 3rd PMOSFET, 4th PMOSFET, 5th PMOSFET, 6th PMOSFET, second not gate, second buffer, 3rd not gate, 3rd NMOSFET, 4th NMOSFET, 5th NMOSFET, 6th NMOSFET, the drain electrode of described 3rd PMOSFET connects power supply, the grid of described 3rd PMOSFET is connected with the source electrode of the 5th PMOSFET, the source electrode of described 3rd PMOSFET is connected with the drain electrode of the 3rd NMOSFET, the grid of described 3rd NMOSFET is connected with the drain electrode of the 5th NMOSFET, the grid of described 3rd NMOSFET is the first input end of the first charge-discharge control circuit, the source ground of described 3rd NMOSFET, the source ground of described 5th NMOSFET, the grid of described 5th NMOSFET is connected with the output of the 3rd not gate, the drain electrode of described 3rd NMOSFET is connected with the input of the second not gate, the drain electrode of described 4th PMOSFET connects power supply, the source electrode of described 4th PMOSFET is connected with the input of the second not gate, the grid of described 4th PMOSFET is connected with the output of the second not gate, the output of described second not gate is connected with the input of the second buffer, the output of described second not gate is the first output of the first charge-discharge control circuit, the output of described second buffer is connected with the grid of the 5th PMOSFET, the output of described second buffer is the second output of the first charge-discharge control circuit, the drain electrode of described 5th PMOSFET connects power supply, the grid of described 5th PMOSFET is connected with the grid of the 4th NMOSFET, the source electrode of described 5th PMOSFET is connected with the source electrode of the 4th NMOSFET, the source electrode of described 4th NMOSFET is connected with the drain electrode of the 6th NMOSFET, the source ground of described 6th NMOSFET, the grid of described 6th NMOSFET is the second input of the first charge-discharge control circuit, the source electrode of described 5th PMOSFET is connected with the input of the 3rd not gate, the drain electrode of described 6th PMOSFET connects power supply, the source electrode of described 6th PMOSFET is connected with the input of the 3rd not gate, the grid of described 6th PMOSFET is connected with the output of the 3rd not gate, the circuit structure of described second charge-discharge control circuit is identical with the first charge-discharge control circuit.

6. the clock circuit of band failure detection mechanisms according to claim 2, is characterized in that: also comprise output waveform shaping circuit, the output of described second NAND gate is connected with the input of output waveform shaping circuit.