CN203661014U - Signal duty ratio and period detection system - Google Patents
Signal duty ratio and period detection system Download PDFInfo
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- CN203661014U CN203661014U CN201320891474.0U CN201320891474U CN203661014U CN 203661014 U CN203661014 U CN 203661014U CN 201320891474 U CN201320891474 U CN 201320891474U CN 203661014 U CN203661014 U CN 203661014U
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Abstract
The utility model discloses a signal duty ratio and period detection system. The system comprises a signal adjusting interface, a time interval measuring module, a data processing module, a data storing module and an adjusting mode selection module, wherein the signal adjusting interface is respectively connected with the time interval measuring module, the data processing module, the data storing module and the adjusting mode selection module, the time interval measuring module is respectively connected with the data processing module and the data storing module, the data processing module is connected with the data storing module, and the data storing module is connected with the adjusting mode selection module. The system measures effective digits according to practical demand increase or decrease to realize signal duty ratio and period adjustment having different precisions, and the whole system has advantages of realization in FPGA, good security, high flexibility and adaptability, simple external circuit structure and low cost.
Description
Technical field
The utility model belongs to signal detection technique field, more specifically, relates to a kind of signal dutyfactor and cycle detecting system.
Background technology
Along with the high speed development of integrated circuit technique, the operating rate of integrated circuit has obtained constantly improving, simultaneously in order further to strengthen the processing throughput of data, streamline, DDR(double data rate) etc. technology be widely used.At double data rate, even in four data rate samples processes, the rising edge of high-speed clock signal and trailing edge need and the stable region of data-signal is strictly aimed at, and now clock signal generation shake or duty ratio occur that deviation all may cause the sample error of data.In addition, in modern control system, pulse width modulation (PWM) technology is comparatively common implementation method, and its principle is exactly the object that recently reaches control object by the duty of change pwm signal.But in real process, a series of uncertain factors such as running frequency, temperature, voltage, distribution link, circuit types, load and technique all affect the performance of signal.
Therefore, the how effectively duty ratio of detection signal and the cycle to feed back to that signal occurs or regulating system seems in the extreme crucial.For clock signal, detection system can provide the foundation of conditioning signal duty ratio and shake; And for pwm signal, can judge the accuracy of signal dutyfactor and check burr etc.At present, relevant detection method mainly exists precision low, and frequency range is narrow, circuit structure complexity, high in cost of production shortcoming.
Utility model content
For above defect or the Improvement requirement of prior art, the utility model provides a kind of signal dutyfactor and cycle detecting system, can increase according to actual needs or reduce measurement number of significant digit, to realize signal dutyfactor and the cycle adjustment of different accuracy, and whole system is in the inner realization of FPGA, good confidentiality, flexibility ratio is high, strong adaptability, external circuit is simple in structure, and cost is low.
For achieving the above object, the utility model provides a kind of signal dutyfactor and cycle detecting system, it is characterized in that, comprises that signal is adjusted interface, time interval measurement module, data processing module, data memory module and adjustment mode is selected module; Described signal adjustment interface connects respectively described time interval measurement module, described data processing module, described data memory module and described adjustment mode and selects module; Described time interval measurement module connects respectively described data processing module and described data memory module; Described data processing module connects described data memory module; Described data memory module connects described adjustment mode and selects module.
Preferably, described signal adjustment interface is used for inputting signal to be detected, duty ratio precision, desired duty cycle and ideal period; Described time interval measurement module is for measuring in real time high level time and the cycle of signal to be detected; Described data processing module, for according to current duty ratio precision, obtains current duty ratio by current high level time and current period; Described data memory module is used for storing current duty ratio and desired duty cycle to duty ratio memory block, also for storing current period and ideal period to cycle memory block; Described adjustment mode selects module to be used for obtaining duty ratio data in duty ratio memory block by system requirements, draw duty ratio adjustment mode sequence and adjust interface output by described signal, also, for obtain cycle data in cycle memory block by system requirements, the cycle that draws is adjusted mode sequence and adjusts interface output by described signal.
Preferably, described time interval measurement module is the time-to-digit converter that adopts tapped delay line method to realize.
Preferably, be integrated in FPGA inside.
In general, the above technical scheme of conceiving by the utility model compared with prior art, has following beneficial effect:
1, support high accuracy duty ratio and shaking detection, also support that precision regulates in real time, increase according to actual needs or reduce and measure number of significant digit, can economize on resources, reduce power consumption simultaneously.
2, circuit structure is simple, can be integrated in FPGA inside, and good confidentiality is disturbed littlely, and cost is low, and is easy to carry out adjustment and the renewal of scheme, and flexibility is high, strong adaptability.
Brief description of the drawings
Fig. 1 is the signal dutyfactor of the utility model embodiment and the structural representation of cycle detecting system;
Fig. 2 is the signal dutyfactor of the utility model embodiment and the workflow diagram of cycle detecting system.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.In addition,, in each execution mode of described the utility model, involved technical characterictic just can combine mutually as long as do not form each other conflict.
As shown in Figure 1, the signal dutyfactor of the utility model embodiment and cycle detecting system comprise: signal is adjusted interface, time interval measurement module, data processing module, data memory module and adjustment mode and selected module.Signal is adjusted interface, and connect hours interval measurement module, data processing module, data memory module and adjustment mode are selected module respectively; Time interval measurement module is connection data processing module and data memory module respectively; Data processing module connection data memory module; Data memory module connects adjustment mode and selects module.
Signal is adjusted the information interaction of Interface realization and system external signal generator (or signal conditioner), the signal to be detected, duty ratio precision, desired duty cycle and the ideal period that produce for input generator, also adjust mode sequence and cycle adjustment mode sequence for output duty cycle, make signal generator make corresponding adjustment, thereby produce the signal that more approaches desired duty cycle and ideal period.Wherein, duty ratio precision is 4 bits, represents the number of significant digit that current duty ratio need to retain.
Time interval measurement module is for measuring in real time high level time and the cycle of signal to be detected, and by its digitized representations output, particularly, time interval measurement module is the time-to-digit converter that adopts tapped delay line method to realize.
Data processing module is used for according to duty ratio precision, and the current high level time that time interval measurement module is exported and current period are processed as calculated and obtained current duty ratio.
Data memory module comprises duty ratio memory block and cycle memory block.Wherein, duty ratio memory block is for storing current duty ratio and the desired duty cycle of data processing module output, and cycle memory block is used for storing corresponding current period and ideal period.Particularly, duty ratio memory block and cycle memory block can be the RAM pieces of FPGA inside, can be also distributed RAM pieces.
Adjustment mode selects module to be used for obtaining the duty ratio data in duty ratio memory block by system requirements, obtaining duty ratio adjusts mode sequence and adjusts interface output by signal, also, for obtain the cycle data in cycle memory block by system requirements, the cycle that obtains is adjusted mode sequence and adjusts interface output by signal.
As shown in Figure 2, the signal dutyfactor of the utility model embodiment and cycle detecting system are worked as follows:
(1) signal generator of system outside or signal conditioner are adjusted interface by signal and are sent enable command to detection system, and system is started working.
(2) time interval measurement module is measured current high level time and the current period of signal to be detected, completes post-tensioning high measurement flag bit t_done.
(3) data processing module detects surveying marker position, if high, the current high level time value by current duty ratio required precision, step (2) being measured obtains current duty ratio divided by current period, draws high calculation flag position duty_done after completing.
(4) data memory module detection computations flag bit, if high, the current duty ratio step (3) being obtained and desired duty cycle are stored in appropriate address place, duty ratio memory block, current period and ideal period are stored in to cycle memory block appropriate address place simultaneously.
(5) adjustment mode selects module to extract duty ratio data and cycle data by system requirements, adjusts decision-making output.
For ensureing the high speed of detection system, in the process that detects operation, can select the method for streamline.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any amendments of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (4)
1. signal dutyfactor and a cycle detecting system, is characterized in that, comprises that signal is adjusted interface, time interval measurement module, data processing module, data memory module and adjustment mode is selected module;
Described signal adjustment interface connects respectively described time interval measurement module, described data processing module, described data memory module and described adjustment mode and selects module; Described time interval measurement module connects respectively described data processing module and described data memory module; Described data processing module connects described data memory module; Described data memory module connects described adjustment mode and selects module.
2. signal dutyfactor as claimed in claim 1 and cycle detecting system, is characterized in that, described signal is adjusted interface and is used for inputting signal to be detected, duty ratio precision, desired duty cycle and ideal period; Described time interval measurement module is for measuring in real time high level time and the cycle of signal to be detected; Described data processing module, for according to current duty ratio precision, obtains current duty ratio by current high level time and current period; Described data memory module is used for storing current duty ratio and desired duty cycle to duty ratio memory block, also for storing current period and ideal period to cycle memory block; Described adjustment mode selects module to be used for obtaining duty ratio data in duty ratio memory block by system requirements, draw duty ratio adjustment mode sequence and adjust interface output by described signal, also, for obtain cycle data in cycle memory block by system requirements, the cycle that draws is adjusted mode sequence and adjusts interface output by described signal.
3. signal dutyfactor as claimed in claim 1 or 2 and cycle detecting system, is characterized in that, described time interval measurement module is the time-to-digit converter that adopts tapped delay line method to realize.
4. signal dutyfactor as claimed in claim 1 and cycle detecting system, is characterized in that, is integrated in FPGA inside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320891474.0U CN203661014U (en) | 2013-12-30 | 2013-12-30 | Signal duty ratio and period detection system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320891474.0U CN203661014U (en) | 2013-12-30 | 2013-12-30 | Signal duty ratio and period detection system |
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| CN203661014U true CN203661014U (en) | 2014-06-18 |
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| CN201320891474.0U Expired - Fee Related CN203661014U (en) | 2013-12-30 | 2013-12-30 | Signal duty ratio and period detection system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109347580A (en) * | 2018-11-19 | 2019-02-15 | 湖南猎航电子科技有限公司 | A kind of adaptive threshold signal detecting method of known duty ratio |
| CN112946355A (en) * | 2021-02-25 | 2021-06-11 | 云谷技术(珠海)有限公司 | Power distribution terminal PWM analog sampling system and method |
-
2013
- 2013-12-30 CN CN201320891474.0U patent/CN203661014U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109347580A (en) * | 2018-11-19 | 2019-02-15 | 湖南猎航电子科技有限公司 | A kind of adaptive threshold signal detecting method of known duty ratio |
| CN109347580B (en) * | 2018-11-19 | 2021-01-19 | 湖南猎航电子科技有限公司 | Self-adaptive threshold signal detection method with known duty ratio |
| CN112946355A (en) * | 2021-02-25 | 2021-06-11 | 云谷技术(珠海)有限公司 | Power distribution terminal PWM analog sampling system and method |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140618 Termination date: 20141230 |
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| EXPY | Termination of patent right or utility model |