CN104283561A - Asynchronous clock parallel-serial conversion half-cycle output circuit - Google Patents
Asynchronous clock parallel-serial conversion half-cycle output circuit Download PDFInfo
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Abstract
The embodiment of the invention discloses an asynchronous clock parallel-serial conversion half-cycle output circuit, which comprises a synchronous frequency division clock generating circuit 10, a data synchronizing circuit 20, a control signal generating circuit 40 and a parallel-serial conversion output circuit 30. The data synchronization circuit 20 achieves synchronization of input data with a high-frequency clock signal, and the parallel-to-serial conversion output circuit 30 achieves conversion of the input data from parallel to serial output. In the circuit of the embodiment of the invention, the asynchronous clock synchronization and the parallel-serial conversion can be simultaneously realized, and the circuit structure is simple.
Description
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Technical field
The present invention relates to production line analog-digital converter technical field, especially relates to a kind of asynchronous clock parallel-serial conversion half period output circuit.
Background technology
Production line analog-digital converter (PL_ADC) has good compromise in area, power consumption, speed and precision, gradually one of implementation becoming High Speed High Precision ADC.
In PL_ADC, the parallel output that realize multiple bit digital signal needs multiple output pad (PAD), owing to exporting PAD Limited Number, so export after data first will being done parallel-serial conversion again.But this relates to again the asynchronous problem of clock.Digital signal due to parallel output produces under the control of internal low-frequency clock, namely synchronous with internal low-frequency rising edge clock.Will export under the control of outside high frequency clock, first asynchronous clock will carry out synchronously by problems faced exactly, how under the prerequisite of the value of digital signal being carried out to accurately sampling, to realize the synchronous of low-and high-frequency clock, acquires a certain degree of difficulty time current.Next will faced by problem be parallel-serial conversion, the method for parallel-serial conversion has a lot, but all too complicated or higher to the frequency requirement of output clock.Realize realizing the synchronous and parallel-serial conversion of asynchronous clock in circuit traditional at present seldom simultaneously, and more complicated, the effect reached is not very desirable.
Summary of the invention
An object of the present invention is to provide a kind of asynchronous clock parallel-serial conversion half period output circuit that simultaneously can realize the synchronous and parallel-serial conversion of asynchronous clock.
Technical scheme disclosed by the invention comprises:
Provide a kind of asynchronous clock parallel-serial conversion half period output circuit, it is characterized in that, comprise: synchronization frequency division clock generation circuit 10, described synchronization frequency division clock generation circuit 10 produces the first sub-frequency clock signal clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4 based on high frequency clock signal clk_f; Data synchronization circuit 20, described data synchronization circuit 20 is connected to described synchronization frequency division clock generation circuit 10, and described data synchronization circuit 20 reception input data D<7:0> is also synchronous with described high frequency clock signal clk_f by described input data D<7:0> according to described first sub-frequency clock signal clk1; Control signal produces circuit 40, described control signal produces circuit 40 and is connected to described synchronization frequency division clock generation circuit 10, and produces control signal sel<3:0> according to described first sub-frequency clock signal clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4; Parallel-serial conversion output circuit 30, described parallel-serial conversion output circuit 30 is connected to described data synchronization circuit 20 and described control signal produces circuit 40, and is exported by described input data serial according to described control signal sel<3:0>.
In one embodiment of the present of invention, described synchronization frequency division clock generation circuit comprises the first d type flip flop 101 and the second d type flip flop 102, wherein: the input end of clock of described first d type flip flop 101 is connected to described high frequency clock signal clk_f, the positive output end of described first d type flip flop 101 exports the data input pin that described 4th sub-frequency clock signal clk4 is connected to described second d type flip flop 102 side by side, and the reversed-phase output of described first d type flip flop 101 exports described second sub-frequency clock signal clk2; The input end of clock of described second d type flip flop 102 is connected to described high frequency clock signal clk_f, the positive output end of described second d type flip flop 102 exports described first sub-frequency clock signal clk1, and the reversed-phase output of described second d type flip flop 102 exports described three frequency division clock signal clk3 and is connected to the data input pin of described first d type flip flop 101.
In one embodiment of the present of invention, described data synchronization circuit 20 comprises the first d type flip flop group 201 and the second d type flip flop group 202, wherein: the input end of clock of described first d type flip flop group 201 is connected to the inversion signal clk0B of low-frequency clock signal, the data input pin of described first d type flip flop group 201 is connected to described input data D<7:0>, and the positive output end of described first d type flip flop group 201 is connected to the data input pin of described second d type flip flop group 202; The input end of clock of described second d type flip flop group 202 is connected to described first sub-frequency clock signal clk1, and the positive output end of described second d type flip flop group 202 is the data output end of described data synchronization circuit 20 and exports synchrodata dataout<7:0>.
In one embodiment of the present of invention, described control signal produces circuit 40 and comprises the first NAND gate 400, second NAND gate 403, 3rd NAND gate 405, 4th NAND gate 409, first not gate 401, second not gate 404, 3rd not gate 406 and the 4th not gate 410, wherein: two inputs of described first NAND gate 400 are connected respectively to described first sub-frequency clock signal clk1 and described 4th sub-frequency clock signal clk4, the output of described first NAND gate 400 exports the inversion signal selB<3> of the 3rd control signal and is connected to the input of described first not gate 401, the output of described first not gate 401 exports the 3rd control signal sel<3>, two inputs of described second NAND gate 403 are connected respectively to described first sub-frequency clock signal clk1 and described second sub-frequency clock signal clk2, the output of described second NAND gate 403 exports the inversion signal selB<2> of the second control signal and is connected to the input of described second not gate 404, and the output of described second not gate 404 exports the second control signal sel<2>, two inputs of described 3rd NAND gate 405 are connected respectively to described three frequency division clock signal clk3 and described second sub-frequency clock signal clk2, the output of described 3rd NAND gate 405 exports the inversion signal selB<1> of the first control signal and is connected to the input of described 3rd not gate 406, and the output of described 3rd not gate 406 exports the first control signal sel<1>, two inputs of described 4th NAND gate 409 are connected respectively to described three frequency division clock signal clk3 and described 4th sub-frequency clock signal clk4, the output of described 4th NAND gate 409 exports the inversion signal selB<0> of the 0th control signal and is connected to the input of described 4th not gate 410, and the output of described 4th not gate 410 exports the 0th control signal sel<0>.
In one embodiment of the present of invention, described parallel-serial conversion output circuit 30 comprises the first transmission gate group 300, second transmission gate group 301, 3d flip-flop 302, four d flip-flop 303, 5th d type flip flop 304 and MUX circuit 305, wherein: the input of described first transmission gate group 300 is connected to the odd bits in described synchrodata dataout<7:0>, the output of described first transmission gate group 300 is connected to the data input pin of described 3d flip-flop 302, first control end of described first transmission gate group 300 is connected to described control signal sel<3:0>, second control end of described first transmission gate group 300 is connected to the inversion signal selB<3:0> of described control signal, the input end of clock of described 3d flip-flop 302 is connected to the inversion signal clk_fB of described high frequency clock signal, and the positive output end of described 3d flip-flop 302 is connected to the first input end of described MUX circuit 305, the input of described second transmission gate group 301 is connected to zero-bit in described synchrodata dataout<7:0> and even bit, the output of described second transmission gate group 301 is connected to the data input pin of described four d flip-flop 303, first control end of described second transmission gate group 301 is connected to described control signal sel<3:0>, second control end of described second transmission gate group 301 is connected to the inversion signal selB<3:0> of described control signal, the input end of clock of described four d flip-flop 303 is connected to the inversion signal clk_fB of described high frequency clock signal, and the positive output end of described four d flip-flop 303 is connected to the data input pin of described 5th d type flip flop 304, the input end of clock of described 5th d type flip flop 304 is connected to described high frequency clock signal clk_f, and the positive output end of described 5th d type flip flop 304 is connected to the second input of described MUX circuit 305, first control end of described MUX circuit 305 is connected to described high frequency clock signal clk_f, and the second control end of described MUX circuit 305 is connected to the inversion signal clk_fB of described high frequency clock signal.
In the circuit of embodiments of the invention, the synchronous and parallel-serial conversion of asynchronous clock can be realized, and circuit structure is simple simultaneously.
Accompanying drawing explanation
Fig. 1 is the structured flowchart schematic diagram of the asynchronous clock parallel-serial conversion half period output circuit of one embodiment of the invention.
Fig. 2 is the structural representation of the synchronization frequency division clock generation circuit of one embodiment of the invention.
Fig. 3 is the structural representation of the data synchronization circuit of one embodiment of the invention.
Fig. 4 is the structural representation of the control signal generation circuit of one embodiment of the invention.
Fig. 5 is the structural representation of the parallel-serial conversion output circuit of one embodiment of the invention.
Embodiment
The concrete structure of the asynchronous clock parallel-serial conversion half period output circuit of embodiments of the invention is described in detail below in conjunction with accompanying drawing.
As shown in Figure 1, in one embodiment of the present of invention, a kind of asynchronous clock parallel-serial conversion half period output circuit comprises synchronization frequency division clock generation circuit 10, data synchronization circuit 20, control signal generation circuit 40 and parallel-serial conversion output circuit 30.
Synchronization frequency division clock generation circuit 10 is for producing the first sub-frequency clock signal clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4 based on high frequency clock signal (such as, outside high frequency clock signal) clk_f.
Data synchronization circuit 20 is connected on synchronization frequency division clock generation circuit 10.This data synchronization circuit 20 receives input data (such as, when to input data be 8, D<7:0>) and will to input data D<7:0> according to the first sub-frequency clock signal clk1 synchronous with high frequency clock signal clk_f.
Control signal produces circuit 40 and is connected to synchronization frequency division clock generation circuit 10, and produces control signal sel<3:0> according to aforesaid first sub-frequency clock signal clk1, the second sub-frequency clock signal clk2, three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4.
Parallel-serial conversion output circuit 30 is connected to data synchronization circuit 20 and control signal produces circuit 40, and exports according to the input data serial that the control signal sel<3:0> that control signal produces circuit 40 generation will be synchronized via data synchronization circuit 20.
As shown in Figure 2, in one embodiment of the present of invention, synchronization frequency division clock generation circuit 10 can comprise the first d type flip flop 101 and the second d type flip flop 102.
The input end of clock of the first d type flip flop 101 is connected to high frequency clock signal clk_f, the positive output end of the first d type flip flop 101 exports the data input pin that the 4th sub-frequency clock signal clk4 is connected to the second d type flip flop 102 side by side, and the reversed-phase output of the first d type flip flop 101 exports the second sub-frequency clock signal clk2.
The input end of clock of the second d type flip flop 102 is connected to high frequency clock signal clk_f, the positive output end of the second d type flip flop 102 exports the first sub-frequency clock signal clk1, and the reversed-phase output of the second d type flip flop 102 exports three frequency division clock signal clk3 and is connected to the data input pin of the first d type flip flop 101.
In the present embodiment, synchronization frequency division clock generation circuit 10 for generation of with the cycle be the high frequency clock signal clk_f rising edge synch of T differ four sub-frequency clock signal clk1, clk2, clk3 and the clk4 being followed successively by 90 degree.
As shown in Figure 3, in one embodiment of the present of invention, data synchronization circuit 20 can comprise the first d type flip flop group 201 and the second d type flip flop group 202.
The input end of clock of the first d type flip flop group 201 is connected to the inversion signal clk0B of low-frequency clock signal, the data input pin of the first d type flip flop group 201 is connected to input data D<7:0>, and the positive output end of the first d type flip flop group 201 is connected to the data input pin of the second d type flip flop group 202.
The input end of clock of the second d type flip flop group 202 is connected to the first sub-frequency clock signal clk1, and the positive output end of the second d type flip flop group 202 is the data output end of data synchronization circuit 20 and exports synchrodata (i.e. the aforesaid input data be synchronized via data synchronization circuit 20) dataout<7:0>.
In the present embodiment, input signal D<7:0> and cycle are the external low frequency clock signal clk0 rising edge synch of 4T, so first carry out sampling with clk0 trailing edge to signal to obtain precise and stable signal di<7:0>, then sample with the synperiodic local low-frequency clock signal clk1 rising edge of clk0, obtain and the signal dataout<7:0> exporting high frequency clock clk_f rising edge synch.
As shown in Figure 4, in one embodiment of the present of invention, control signal produces circuit 40 can comprise the first NAND gate 400, second NAND gate 403, the 3rd NAND gate 405, the 4th NAND gate 409, first not gate 401, second not gate 404, the 3rd not gate 406 and the 4th not gate 410.
Two inputs of the first NAND gate 400 are connected respectively to the first sub-frequency clock signal clk1 and the 4th sub-frequency clock signal clk4, the output of the first NAND gate 400 exports the inversion signal selB<3> of the 3rd control signal and is connected to the input of the first not gate 401, and the output of the first not gate 401 exports the 3rd control signal sel<3>.
Two inputs of the second NAND gate 403 are connected respectively to the first sub-frequency clock signal clk1 and the second sub-frequency clock signal clk2, the output of the second NAND gate 403 exports the inversion signal selB<2> of the second control signal and is connected to the input of the second not gate 404, and the output of the second not gate 404 exports the second control signal sel<2>.
Two inputs of the 3rd NAND gate 405 are connected respectively to three frequency division clock signal clk3 and the second sub-frequency clock signal clk2, the output of the 3rd NAND gate 405 exports the inversion signal selB<1> of the first control signal and is connected to the input of the 3rd not gate 406, and the output of the 3rd not gate 406 exports the first control signal sel<1>.
Two inputs of the 4th NAND gate 409 are connected respectively to three frequency division clock signal clk3 and the 4th sub-frequency clock signal clk4, the output of the 4th NAND gate 409 exports the inversion signal selB<0> of the 0th control signal and is connected to the input of the 4th not gate 410, and the output of the 4th not gate 410 exports the 0th control signal sel<0>.
In the present embodiment, can produce four phases not overlapping control signal sel<3:0> and inversion signal selB<3:0> thereof, local low-frequency clock (i.e. aforesaid sub-frequency clock signal) clk1, clk2, clk3, clk4 that they are followed successively by 90 degree by difference produce.
As shown in Figure 5, in one embodiment of the present of invention, parallel-serial conversion output circuit 30 comprises the first transmission gate group 300, second transmission gate group 301,3d flip-flop 302, four d flip-flop 303, the 5th d type flip flop 304 and MUX circuit 305.
The input of the first transmission gate group 300 is connected to odd bits in synchrodata dataout<7:0> (such as, dataout<7, 5, 3, 1>), the output of the first transmission gate group 300 is connected to the data input pin of 3d flip-flop 302, first control end of the first transmission gate group 300 is connected to control signal sel<3:0>, second control end of the first transmission gate group 300 is connected to the inversion signal selB<3:0> of control signal.
The input end of clock of 3d flip-flop 302 is connected to the inversion signal clk_fB of high frequency clock signal, and the positive output end of 3d flip-flop 302 is connected to the first input end of MUX circuit 305.
The input of the second transmission gate group 301 is connected to zero-bit in synchrodata dataout<7:0> and even bit (such as, dataout<6, 4, 2, 0>), the output of the second transmission gate group 301 is connected to the data input pin of four d flip-flop 303, first control end of the second transmission gate group 301 is connected to control signal sel<3:0>, second control end of the second transmission gate group 301 is connected to the inversion signal selB<3:0> of control signal.
The input end of clock of four d flip-flop 303 is connected to the inversion signal clk_fB of high frequency clock signal, and the positive output end of four d flip-flop 303 is connected to the data input pin of the 5th d type flip flop 304.
The input end of clock of the 5th d type flip flop 304 is connected to high frequency clock signal clk_f, and the positive output end of the 5th d type flip flop 304 is connected to the second input of MUX circuit 305.
First control end of MUX circuit 305 is connected to high frequency clock signal clk_f, and the second control end of MUX circuit 305 is connected to the inversion signal clk_fB of high frequency clock signal.
In one embodiment of the present of invention, this MUX circuit 305 can be such as alternative circuit.
In the present embodiment, first data will be inputted (such as, aforesaid synchrodata dataout<7:0>) odd bits and even bit be divided into two output channels, odd bits dataout<7,5,3, the first transmission gate group 300 of 1> through being controlled by signal sel<3:0> and selB<3:0>, the signal of output is sampled through the trailing edge of the clock signal clk_f of 3d flip-flop 302; Even bit dataout<6,4,2,0> is connected to the second transmission gate group 301 controlled by signal sel<3:0> and selB<3:0>, the signal exported first sample by the trailing edge of the clock signal clk_f of four d flip-flop 303, then by the 5th d type flip flop 304 clock signal clk_f on fall edge and sample again; The odd bits of adopting and even bit signal finally all arrive alternative circuit 305, export odd bits in the clk_f high level valid period, carry-out bit during Low level effective.The advantage of alternative circuit is a clk_f cycle exportable two digits signal; 4 clk_f clock cycle of such use just can realize 8bit parallel data Serial output.
In the circuit of embodiments of the invention, the synchronous and parallel-serial conversion of asynchronous clock can be realized, and circuit structure is simple simultaneously.
Described the present invention by specific embodiment above, but the present invention is not limited to these specific embodiments.It will be understood by those skilled in the art that and can also make various amendment, equivalent replacement, change etc. to the present invention, as long as these conversion do not deviate from spirit of the present invention, all should within protection scope of the present invention.In addition, " embodiment " described in above many places represents different embodiments, can certainly by its all or part of combination in one embodiment.
Claims (5)
1. an asynchronous clock parallel-serial conversion half period output circuit, is characterized in that, comprising:
Synchronization frequency division clock generation circuit (10), described synchronization frequency division clock generation circuit (10) produces the first sub-frequency clock signal (clk1), the second sub-frequency clock signal (clk2), three frequency division clock signal (clk3) and the 4th sub-frequency clock signal (clk4) based on high frequency clock signal (clk_f);
Data synchronization circuit (20), described data synchronization circuit (20) is connected to described synchronization frequency division clock generation circuit (10), and described data synchronization circuit (20) receives input data (D<7:0>) according to described first sub-frequency clock signal (clk1) by synchronous with described high frequency clock signal (clk_f) for described input data (D<7:0>);
Control signal produces circuit (40), described control signal produces circuit (40) and is connected to described synchronization frequency division clock generation circuit (10), and produces control signal (sel<3:0>) according to described first sub-frequency clock signal (clk1), the second sub-frequency clock signal (clk2), three frequency division clock signal (clk3) and the 4th sub-frequency clock signal (clk4);
Parallel-serial conversion output circuit (30), described parallel-serial conversion output circuit (30) is connected to described data synchronization circuit (20) and described control signal produces circuit (40), and is exported by described input data serial according to described control signal (sel<3:0>).
2. circuit as claimed in claim 1, is characterized in that: described synchronization frequency division clock generation circuit comprises the first d type flip flop (101) and the second d type flip flop (102), wherein:
The input end of clock of described first d type flip flop (101) is connected to described high frequency clock signal (clk_f), the positive output end of described first d type flip flop (101) exports the data input pin that described 4th sub-frequency clock signal (clk4) is connected to described second d type flip flop (102) side by side, and the reversed-phase output of described first d type flip flop (101) exports described second sub-frequency clock signal (clk2);
The input end of clock of described second d type flip flop (102) is connected to described high frequency clock signal (clk_f), the positive output end of described second d type flip flop (102) exports described first sub-frequency clock signal (clk1), and the reversed-phase output of described second d type flip flop (102) exports described three frequency division clock signal (clk3) and is connected to the data input pin of described first d type flip flop (101).
3. circuit as described in claim 1 or 2, is characterized in that: described data synchronization circuit (20) comprises the first d type flip flop group (201) and the second d type flip flop group (202), wherein:
The input end of clock of described first d type flip flop group (201) is connected to the inversion signal (clk0B) of low-frequency clock signal, the data input pin of described first d type flip flop group (201) is connected to described input data (D<7:0>), and the positive output end of described first d type flip flop group (201) is connected to the data input pin of described second d type flip flop group (202);
The input end of clock of described second d type flip flop group (202) is connected to described first sub-frequency clock signal (clk1), and the positive output end of described second d type flip flop group (202) is the data output end of described data synchronization circuit (20) and exports synchrodata (dataout<7:0>).
4. as the circuit in claims 1 to 3 as described in any one, it is characterized in that: described control signal produces circuit (40) and comprises the first NAND gate (400), the second NAND gate (403), the 3rd NAND gate (405), the 4th NAND gate (409), the first not gate (401), the second not gate (404), the 3rd not gate (406) and the 4th not gate (410), wherein:
Two inputs of described first NAND gate (400) are connected respectively to described first sub-frequency clock signal (clk1) and described 4th sub-frequency clock signal (clk4), the output of described first NAND gate (400) exports the inversion signal (selB<3>) of the 3rd control signal and is connected to the input of described first not gate (401), and the output of described first not gate (401) exports the 3rd control signal (sel<3>);
Two inputs of described second NAND gate (403) are connected respectively to described first sub-frequency clock signal (clk1) and described second sub-frequency clock signal (clk2), the output of described second NAND gate (403) exports the inversion signal (selB<2>) of the second control signal and is connected to the input of described second not gate (404), and the output of described second not gate (404) exports the second control signal (sel<2>);
Two inputs of described 3rd NAND gate (405) are connected respectively to described three frequency division clock signal (clk3) and described second sub-frequency clock signal (clk2), the output of described 3rd NAND gate (405) exports the inversion signal (selB<1>) of the first control signal and is connected to the input of described 3rd not gate (406), and the output of described 3rd not gate (406) exports the first control signal (sel<1>);
Two inputs of described 4th NAND gate (409) are connected respectively to described three frequency division clock signal (clk3) and described 4th sub-frequency clock signal (clk4), the output of described 4th NAND gate (409) exports the inversion signal (selB<0>) of the 0th control signal and is connected to the input of described 4th not gate (410), and the output of described 4th not gate (410) exports the 0th control signal (sel<0>).
5. circuit as claimed in claim 3, it is characterized in that: described parallel-serial conversion output circuit (30) comprises the first transmission gate group (300), the second transmission gate group (301), 3d flip-flop (302), four d flip-flop (303), the 5th d type flip flop (304) and MUX circuit (305), wherein:
The input of described first transmission gate group (300) is connected to the odd bits in described synchrodata (dataout<7:0>), the output of described first transmission gate group (300) is connected to the data input pin of described 3d flip-flop (302), first control end of described first transmission gate group (300) is connected to described control signal (sel<3:0>), second control end of described first transmission gate group (300) is connected to the inversion signal (selB<3:0>) of described control signal,
The input end of clock of described 3d flip-flop (302) is connected to the inversion signal (clk_fB) of described high frequency clock signal, and the positive output end of described 3d flip-flop (302) is connected to the first input end of described MUX circuit (305);
The input of described second transmission gate group (301) is connected to zero-bit in described synchrodata (dataout<7:0>) and even bit, the output of described second transmission gate group (301) is connected to the data input pin of described four d flip-flop (303), first control end of described second transmission gate group (301) is connected to described control signal (sel<3:0>), second control end of described second transmission gate group (301) is connected to the inversion signal (selB<3:0>) of described control signal,
The input end of clock of described four d flip-flop (303) is connected to the inversion signal (clk_fB) of described high frequency clock signal, and the positive output end of described four d flip-flop (303) is connected to the data input pin of described 5th d type flip flop (304);
The input end of clock of described 5th d type flip flop (304) is connected to described high frequency clock signal (clk_f), and the positive output end of described 5th d type flip flop (304) is connected to the second input of described MUX circuit (305);
First control end of described MUX circuit (305) is connected to described high frequency clock signal (clk_f), and the second control end of described MUX circuit (305) is connected to the inversion signal (clk_fB) of described high frequency clock signal.
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| CN107425844A (en) * | 2017-07-17 | 2017-12-01 | 北京时代民芯科技有限公司 | A kind of configurable clock buffer suitable for SRAM type FPGA |
| CN111224658A (en) * | 2020-01-16 | 2020-06-02 | 电子科技大学 | Design method of parallel data-to-serial data conversion circuit |
| CN113364468A (en) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | Serial-to-parallel conversion alignment circuit and method |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| WO2024113426A1 (en) * | 2022-11-30 | 2024-06-06 | 重庆吉芯科技有限公司 | High-speed parallel-to-serial conversion circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107425844A (en) * | 2017-07-17 | 2017-12-01 | 北京时代民芯科技有限公司 | A kind of configurable clock buffer suitable for SRAM type FPGA |
| CN107425844B (en) * | 2017-07-17 | 2020-09-11 | 北京时代民芯科技有限公司 | Configurable clock buffer suitable for SRAM type FPGA |
| CN111224658A (en) * | 2020-01-16 | 2020-06-02 | 电子科技大学 | Design method of parallel data-to-serial data conversion circuit |
| CN113364468A (en) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | Serial-to-parallel conversion alignment circuit and method |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN114421967B (en) * | 2022-01-24 | 2024-05-31 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic equipment |
| WO2024113426A1 (en) * | 2022-11-30 | 2024-06-06 | 重庆吉芯科技有限公司 | High-speed parallel-to-serial conversion circuit |
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