CN102006033B

CN102006033B - Band-weight-delay-chain-based digital 50 percent duty cycle regulating circuit

Info

Publication number: CN102006033B
Application number: CN2010105559004A
Authority: CN
Inventors: 谭晓强; 陈宝民; 陈怒兴; 石大勇; 蒋仁杰; 郭斌; 李俊丰
Original assignee: CHANGSHA JINGJIA MICROELECTRONICS Co Ltd
Current assignee: Changsha Jingjia Microelectronic Co., Ltd.
Priority date: 2010-11-19
Filing date: 2010-11-19
Publication date: 2012-01-18
Anticipated expiration: 2030-11-19
Also published as: CN102006033A

Abstract

Many high-frequency integrated circuits require 50 percent duty cycle for a clock signal, however, the duty cycle of the clock signal directly output by a phase-locked loop is often over 50 percent. Therefore, a special duty cycle regulating circuit is required for regulating the duty cycle of the clock signal. The duty cycle regulating circuit mainly comprises a duty cycle regulating circuit in an analog mode and a duty cycle regulating circuit in a digital mode. The invention discloses a band-weight-delay-chain-based fast, high-accuracy and digital 50 percent duty cycle regulating circuit, which can obviously quicken the regulating time and improve the regulating accuracy. The circuit consists of two frequency dividers, a band weight delay chain 1, a band weight delay chain 2, a Buffer, an exclusive Or-gate (XOR gate), a D trigger, a detection logic lock and a bidirectional counter.

Description

A kind of numeral 50% duty cycle adjustment circuit based on the heavy delay chain of cum rights

Technical field

The present invention is used for the IC design field, is used for that duty ratio is departed from 50% clock signal and is adjusted to 50% duty ratio.Be specifically related to the heavy delay chain of a kind of cum rights, can faster more accurate duty cycle adjustment to 50% with clock signal.

Background technology

Some integrated circuit has higher requirement to the duty ratio of clock; Require duty ratio near 50%; But producing the duty ratio of the clock signal that circuit generated, the phase-locked loop isochronon often can not accurately equal 50%; Perhaps clock signal causes duty ratio to depart from 50% through behind the asymmetric clock Buffer, so just needs near the special duty cycle adjustment to 50% of duty cycle adjustment circuit with clock signal.

The duty cycle adjustment circuit mainly is divided into two big types, and one type is the regulative mode of simulation, and one type is the regulative mode of numeral.The duty cycle adjustment circuit precision of analog form is high, but the implementation of simulation all contains charge pump and filter capacitor basically, so the analog regulation mode has slow, shortcoming such as chip area is big of adjusting time.The regulative mode of numeral and the regulative mode of simulation are compared, and the adjusting time shortens greatly, has the characteristics of quick response, because digital regulated mode does not need bigger filter capacitor, chip area is littler than analog regulation mode simultaneously.But there are the compromise problem in the degree of regulation and the adjustable range of present digital duty cycle adjustment circuit, are difficult to satisfy simultaneously.Duty cycle adjustment circuit based on the heavy delay chain technology of cum rights disclosed by the invention can be issued to wide adjustable range in the prerequisite of the joint precision of keeping a high profile.

Summary of the invention

The degree of regulation of numeral duty cycle adjustment circuit depends on the minimum adjustable unit of delay chain, and regulating power depends on the maximum adjustable adjusting range of delay chain, but the delay chain of present digital duty cycle adjustment circuit all is the step-length regulative mode such as to take; Be N identical minimum adjustable unit series connection; If the raising degree of regulation, then must minimum adjustable unit be done for a short time, this has just influenced the maximum adjustable adjusting range; If the maximum adjustable adjusting range is done greatly, then will inevitably be influenced degree of regulation.

For addressing the above problem, the invention discloses a kind of digital duty cycle adjustment circuit based on the heavy delay chain of cum rights, main feature of the present invention is:

1, utilize the heavy delay chain of cum rights can take into account adjustable range and two performance index of degree of regulation;

2, the lock-out state that reaches output clock 50% duty ratio that can be faster.

Description of drawings

Fig. 1 is based on the quick high accuracy numeral 50% duty cycle adjustment circuit overall construction drawing of the heavy delay chain of cum rights;

Fig. 2 adjusting waveform of the present invention sketch map;

The heavy delay chain sketch map of Fig. 3 cum rights;

Fig. 4 uses duty cycle adjustment waveform disclosed by the invention figure as a result.

Embodiment

Below in conjunction with accompanying drawing, the structure and the course of work of a kind of quick high accuracy numeral 50% duty cycle adjustment circuit based on the heavy delay chain of cum rights that specifies disclosure of the Invention.

As shown in Figure 1; A kind of quick high accuracy numeral 50% duty cycle adjustment circuit based on the heavy delay chain of cum rights disclosed by the invention mainly comprises a two-divider, two heavy delay chains of cum rights, an XOR gate, a Buffer, a d type flip flop, a lock-in detection logical block and a bidirectional counter, input clock ck _InBe connected to the in end of two-divider, the clk end of lock-in detection logic and the clk end of bidirectional counter; The out of two-divider end is connected respectively to input of XOR gate and the in of the heavy delay chain 1 of cum rights holds; The out end of the heavy delay chain 1 of cum rights is connected to another input of XOR gate; The output of XOR gate is connected to the input of Buffer, and the output of Buffer is output signal ck _Out, ck _OutBe connected to the in end of the heavy delay chain 2 of cum rights and the D end of d type flip flop, the out end of the heavy delay chain 2 of cum rights is connected to the clk end of d type flip flop, the in that the Q end of d type flip flop is connected to the lock-in detection logic hold and bidirectional counter "

" end, the out end of lock-in detection logic is connected to the EN end of bidirectional counter, and the out end of bidirectional counter is connected to ctrl [0:n] end of heavy delay chain 1 of cum rights and the heavy delay chain 2 of cum rights.

The concrete course of work of circuit is following: as shown in Figure 2, depart from the input clock ck of 50% duty ratio _InThrough output frequency behind the two-divider frequency division reduce by half, duty ratio is 50% signal c ₁, c ₁Through the heavy delay chain 1 time-delay output c of cum rights _1d, c ₁And c _1dTwo signals generate c through xor operation ₂If, c _1dAnd c ₁Compare and postponed 1/4 clock cycle, be i.e. 1/2 ck _InCycle, the c that then obtains through xor operation ₂Signal has and ck _InIdentical frequency, and duty ratio is 50%, c ₂Driving obtains final output signal ck through Buffer _Out

The time-delay that the key that obtains 50% duty cycle signals is accurately to control the heavy delay chain 1 of cum rights is 1/4 c ₁Cycle.The control strategy of the heavy delay chain of cum rights is following: utilize and 2 couples of ck of the heavy heavy delay chain of delay chain 1 identical cum rights of cum rights _OutDelay time, obtain ck _{Out_d}, the control signal of two delay chains is identical, 1 couple of c of the heavy delay chain of cum rights ₁Signal delay is 2 couples of ck of the heavy delay chain of cum rights in the time of 1/4 cycle _OutPostpone half period, utilize ck _{Out_d}As the clock of d type flip flop to ck _OutSample.If ck _{Out_d}And ck _OutCompare, postpone less than half period, then sampled result is always high, if postpone greater than half period, then sampled result is always low, if time-delay just equals half period, then sampled result is a high-low level at random.The lock-in detection logic is judged the output result of a d type flip flop m clock cycle, if the result in m cycle is high or complete in low entirely, explains that then the heavy delay chain 2 of cum rights is not with ck _OutSignal just postpones half period, lock-in detection logic output this moment high level, and this signal controlling bidirectional counter takes corresponding counts to change; If in the variation of m cycle memory at high-low level, then explanation time-delay is near 50%, this moment lock-in detection logic output low level, bidirectional counter keeps count results constant.

The sketch map of the heavy delay chain of cum rights is as shown in Figure 3; Form by n level delay cell and a shaping Buffer; Every grade of delay cell is made up of an inverter and a load capacitance, the delay ability of regulating whole delay chain through every grade of delay cell load capacitance of switch.The load capacitance of every grade of delay cell is all inequality in the heavy delay chain of cum rights, from 2 ⁰* k is increased to 2 ^N-1* k, wherein k is the least unit load capacitance.Compare with traditional delay chain, the load capacitance of every grade of delay cell is no longer identical, but is exponential increase; Like this; Through the delay cell of identical progression, the heavy delay chain of cum rights is compared with traditional delay chain and can be obtained wideer adjustable range, and; The degree of regulation of the heavy delay chain of cum rights depends on the delay ability of minimum load capacitance delays unit; Compare with traditional delay chain, the precision that increases delay chain is less to the influence of adjustable range, can obtain higher precision so the heavy delay chain of cum rights is compared with traditional delay chain.

The heavy delay chain of cum rights is controlled by bidirectional counter; " EN " signal in the bidirectional counter is the output result of lock-in detection logic among Fig. 1; If the output result of m cycle d type flip flop is always high or low continuously, then explanation does not reach lock-out state as yet, need regulate the time-delay of the heavy delay chain of cum rights; This moment, the value of EN was a high level, and bidirectional counter changes count value; If there is the high-low level conversion in the output result of m interior d type flip flop of cycle then explains that circuit has reached lock-out state, this moment, the value of EN was a low level, and bidirectional counter keeps count value.In the bidirectional counter "

" signal is the output result of d type flip flop among Fig. 1, "

" signal be high level represent the heavy delay chain 2 of cum rights time-delay less than 1/2 ck _OutCycle needs to strengthen time-delay, and at this moment, bidirectional counter increases counting; "

" the signal low level represent the heavy delay chain 2 of cum rights time-delay greater than 1/2 ck _OutCycle need reduce time-delay, and at this moment, bidirectional counter reduces counting.

Like this, through heavy delay chain of cum rights and bidirectional counter, just can realize interior quick 50% duty cycle adjustment on a large scale.Be illustrated in figure 4 as the duty cycle adjustment oscillogram based on the heavy delay chain quick high accuracy numeral of cum rights 50% duty ratio dispensable circuit disclosed by the invention; Top waveform is that duty ratio departs from 50% input clock, and following waveform is that duty ratio is 50% output clock.

Claims

1. a duty cycle adjustment circuit comprises a two-divider, two heavy delay chains of cum rights, an XOR gate, a Buffer, a d type flip flop, a lock-in detection logical block and a bidirectional counter, input clock ck _InBe connected to the in end of two-divider, the clk end of lock-in detection logic and the clk end of bidirectional counter; The out of two-divider end is connected respectively to input of XOR gate and the in of the heavy delay chain 1 of cum rights holds; The out end of the heavy delay chain 1 of cum rights is connected to another input of XOR gate; The output of XOR gate is connected to the input of Buffer, and the output of Buffer is output signal ck _Out, ck _OutBe connected to the in end of the heavy delay chain 2 of cum rights and the D end of d type flip flop, the out end of the heavy delay chain 2 of cum rights is connected to the clk end of d type flip flop, and in that the Q end of d type flip flop is connected to the lock-in detection logic holds and bidirectional counter

End, the out end of lock-in detection logic is connected to the EN end of bidirectional counter, and the out end of bidirectional counter is connected to ctrl [0:n] end of heavy delay chain 1 of cum rights and the heavy delay chain 2 of cum rights.