CN103036566A - On-line adjustment controller for imitating front-end chip - Google Patents
On-line adjustment controller for imitating front-end chip Download PDFInfo
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Abstract
An on-line adjustment controller for imitating a front-end chip comprises a serial-to-parallel conversion module, a format conversion and fan-out module and a module for receiving and reading data of a register. The serial-to-parallel conversion module carries out serial-to-parallel conversion on serial port data which are input by the exterior, and outputs parallel data and corresponding enable signals of the parallel data to the format conversion and fan-out module. According to the parallel data and the corresponding enable signals of the parallel data, the format conversion and fan-out module outputs three-wire serial interface timing signals, namely a Sclk signal of the on-line adjustment AFE chip, a Sdata signal of the on-line adjustment AFE chip and a Sen signal of the on-line adjustment AFE chip, and the three-wire serial interface timing signals meet the requirements of an analog front end (AFE) chip. The module for receiving and reading the data of the register receives data which is input by a service data objects (SDO) base pin of the AFE chip, carries out the serial-to-parallel conversion on the conditions of the register of the AFE chip and outputs to a fixed storage according to the Sclk signal of the on-line adjustment AFE chip and the Sen signal of the on-line adjustment AFE chip which are output by the format conversion and fan-out module.
Description
Technical field
The present invention relates to a kind of conditioning controller of serial ports register of the AFE (analog front end) AFE chip that uses in signal processing circuit, can carry out online register configuration to multichannel analog front-end A FE chip.
Background technology
The Main Function of ccd signal treatment circuit is to be converted to digital signal after the analog signal of CCD output is processed.Its acp chip is AFE (analog front end) AFE chip.It is digital signal with analog signal conversion that analog front circuit is used the AFE chip.To the AFE AFE (analog front end) of different purposes, its operational environment requirement, operating rate, conversion accuracy differ widely.Thereby the scheme, the mode that realize AFE (analog front end) AFE chip are also different.
The AFE chip all has configurable internal register, and for different input analog signal situations, the chips that carrying out difference needs are regulated, and reaches the different requirements of the digital quantization after control output analog to digital signal is changed.This needs repeatedly, multichannel AFE chip internal register is configured operation, because different AFE chip internal registers do not wait from 8bit to 64bit, need the quantity of configuration and time number average more.
The novel analog front-end A FE chip of existing signal processing circuit in the program debugging process, need to the AFE chip register carry out repeatedly, the on-line control of multichannel, carry out the real-time online configuration of online multi-disc AFE chip internal register by the RS232 serial ports, process is loaded down with trivial details, and the adjusting time is long, often and underaction.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, on-line control controller a kind of versatility, that realize the analog front-end chip of configurable, the configurable any AFE chip register state of system's real-time online is provided.
Technical solution of the present invention is: a kind of on-line control controller of analog front-end chip, comprise string and modular converter, format conversion and fan-out modular, reception readout register data module, wherein:
String and modular converter: the serial data of outside input is gone here and there and changed, and output parallel data and corresponding parallel data enable signal are to format conversion and fan-out modular; Described serial data comprises the register data of AFE (analog front end) AFE chip;
Format conversion and fan-out modular: according to the parallel data of input and corresponding parallel data enable signal and work master clock, three line serial ports clock signals of AFE chip requirement are satisfied in output, described three line serial ports clock signals are respectively on-line control AFE chip Sclk signal, on-line control AFE chip Sdata signal and on-line control AFE chip Sen signal;
Receive the readout register data module: the data that receive the input of AFE chip SDO pin, on-line control AFE chip Sclk signal, on-line control AFE chip Sen signal according to format conversion and fan-out modular output, output in the fixing memory after the buffer status of AFE chip done string and conversion, carry out data storages;
Described format conversion and fan-out modular comprise that frequency counter unit, the generation of frequency division data and counter signals logic matrix unit, three line traffic control Sclk produce matrix unit, serial data counter unit, the code of going here and there enables matrix unit, parallel data latch units and parallel serial conversion unit, wherein:
The frequency counter unit: the work master clock is carried out setting the counting of frequency division value, and count value is from 1 to the frequency division value circulation of setting, and count value is delivered to frequency division data generation unit;
The frequency division data produce and counter signals logic matrix unit: the count value generation duty ratio that transmits according to the frequency counter unit is 1: 1 frequency-dividing clock and delivers to three line traffic control Sclk generation matrix unit; The serial data enable signal that produces the serial data counter unit according to the parallel data enable signal is delivered to the serial data counter unit, the parallel data figure place bit number that the serial data enable signal is processed according to need, the serial data counting number of control serial data counter unit, described serial data enable signal comprises the full bit count signal of the serial data counter unit of complete cycle; The serial data enable signal of serial data counter unit effectively opens and begins constantly to delay master clock cycle of parallel data enable signal;
Three line traffic control Sclk produce matrix unit: the frequency-dividing clock and the on-line control AFE chip Sen signal that receive input, when on-line control AFE chip Sen signal for enabling when invalid, the frequency-dividing clock of input is anti-phase rear as on-line control AFE chip Sclk signal and output, when on-line control AFE chip Sen signal for enabling when effective, with the frequency-dividing clock of input as on-line control AFE chip Sclk signal and output;
Serial data counter unit: when the serial data enable signal of input is effective, begin counting constantly as counter, in count value less than default parallel data bit value 8N+1 and when the rolling counters forward signal is effective, carry out the serial data rolling counters forward, when the serial data count value reaches default parallel data bit value and rolling counters forward signal and remains valid, count value is carried out again counting after the zero clearing, count value is delivered to the string code and is enabled matrix unit, and N is positive integer;
String code enables matrix unit: when the frequency division data of input produce and the serial data enable signal of counter signals logic matrix unit effective, simultaneously in the count value of serial data counter unit output less than preset value 8N+1 and greater than 0 o'clock, on-line control AFE chip Sen signal is set for effectively; Equal 0 or during greater than preset value 8N+1 in the count value of serial data counter unit output, on-line control AFE chip Sen invalidating signal is set; When the serial data enable invalidating signal of the generation of frequency division data and counter signals logic matrix unit, on-line control AFE chip Sen signal is set keeps current state;
The parallel data latch units: the parallel data in input enables when effective, delivers to parallel serial conversion unit after according to the work master clock parallel data of input being latched;
Parallel serial conversion unit: enable when effective in parallel data, the 8Nbit parallel data is lower synchronously at master clock, latch, enable to keep current latch data when invalid in parallel data; When on-line control AFE chip Sen signal is effective, export as on-line control AFE chip Sdata signal by order from high to low after respectively the parallel data that latchs being converted to serial data.
Described string and modular converter comprise that three d type flip flops, judgement serial data begin unit, baud rate counter unit, valid data sign generation unit, string and converting unit, enable counter unit, data splicing and lock unit, wherein:
The first d type flip flop: the serial data of outside input delayed time obtains serial data after the one-level time-delay, and the serial data after the one-level time-delay is sent into simultaneously the second d type flip flop and judged that serial data begins the unit;
The second d type flip flop: the serial data after the one-level time-delay delayed time again obtains serial data after the secondary time-delay, and the serial data after the secondary time-delay is sent into simultaneously judge that serial data begins unit, baud rate counter unit, valid data sign generation unit, string and converting unit;
Judge that serial data begins the unit: the serial data to input carries out the initial judgement of data, when the serial data after the one-level time-delay be 0 and the secondary time-delay after serial data when being 1, the output data enable signal is to the baud rate counter unit; When the count value of baud rate counter unit count down to frame serial data end, stop to export data enable signal;
Baud rate counter unit: when the serial data after the secondary time-delay is 0 and judges that serial data begins the data enable signal of unit output when effective, perhaps when the valid data enable signal of valid data sign generation unit output effectively and judge that serial data begins the data enable signal of unit output when effective, the work master clock counted and count value delivered to simultaneously judge that serial data begins unit, valid data sign generation unit, string and converting unit; When judging that serial data begins the data enable signal of unit output when invalid, carries out the zero clearing of count value;
Valid data sign generation unit: when the serial data after the secondary time-delay is 0 and the count value of baud rate counter unit input when carving in the middle of the first bit data cycle in a frame serial data, output valid data enable signal is also delivered to baud rate counter unit, 3d flip-flop, enable counter unit simultaneously; When the count value of baud rate counter unit input in the middle of last bit data cycle in same frame serial data constantly the time, stop to export the valid data enable signal;
3d flip-flop: the valid data enable signal of input delayed time obtains valid data enable signal after the one-level time-delay, and the valid data enable signal after the one-level time-delay is sent into enable counter unit, string and converting unit simultaneously;
String and converting unit: according to the count value of baud rate counter unit input, a frame serial data in the middle of data cycle of the bits per inch certificate of first and last bit data, constantly respectively the serial data after the secondary time-delay of correspondence is squeezed into the first parallel data register, the data in the first parallel data register are sent into data and are spliced and lock unit; The first parallel data register the valid data enable signal effectively and the valid data enable signal after the one-level time-delay carry out clear operation when invalid;
Enable counter unit: when the valid data enable signal when the valid data enable signal after the time-delay of invalid and one-level is effective, produce a frame serial data and finish id signal, one frame serial data is finished id signal to be counted, when count value arrives the threshold value N that sets, produce data splicing enable signal, data are spliced after enable signal and count value are delivered to data splicing and lock unit count value is carried out zero clearing;
Data splicing and lock unit: inside arranges a 8Nbit data counter and produces 8Nbit parallel data enable signal; The parallel data of input is input in the address location of the second parallel data register, and the data bits of the second parallel data register equals the figure place of N the first parallel data register doubly; When the data splicing enable signal of enable counter unit output is invalid, keep the current data value constant in two data registers; When the data splicing enable signal of enable counter unit output is effective, the 8Nbit data that splicing is good latch, the 8Nbit data counter is resetted, when data splicing enable signal is invalid, the 8Nbit data counter is counted, be in the serial data periodic quantity scope time at 8Nbit data counter counting, produce 8Nbit parallel data enable signal and also be set to enable effectively, 8Nbit data counter counting be arrange outside the serial data periodic quantity scope time 8Nbit parallel data enable signal enable invalid; Enable when effective in the 8Nbit parallel data, synchronous through the work master clock, the output of 8Nbit parallel data is also synchronous through the work master clock to 8Nbit parallel data enable signal, export final 8Nbit parallel data enable signal.
Described reception readout register data module comprises that two d type flip flops, data latch and go here and there and converting unit, signal lag and logic matrix unit, wherein:
Two d type flip flops: the data of AFE chip SDO pin input are carried out being input to after the two-stage time-delay data latch and go here and there and converting unit;
Signal lag and logic matrix unit: AFE chip Sclk signal and AFE chip Sen signal are carried out suitable time-delay, so that the trailing edge of the AFE chip Sclk signal after the time-delay is aimed at the centre of AFE chip Sdo pin data, so that be the output effectual time of Sdo pin data during the AFE chip Sen signal low level after the time-delay;
Data latch and go here and there and converting unit: when the AFE chip Sen signal after the time-delay is effective, AFE chip Sclk signal trailing edge after time-delay constantly, AFE chip Sdo pin data after the two-stage time-delay are latched and go here and there and change, with the buffer status of AFE chip do the string and the conversion after, output in the fixing memory, carry out the data storage.
The present invention's advantage compared with prior art is:
1, it is adjustable online that the present invention adopts AFE chip configuration register, so as not to novel analog front-end A FE chip in the program debugging process, need to the AFE chip register carry out repeatedly, the adjusting of multichannel, reduced the process of modification of program, debugging.Simple RS232 interface is passed through in modification to AFE chip register parameter, can not change in the situation of circuit hardware and software program the acp chip of rapid, succinct conditioning signal treatment circuit;
2, the on-line control AFE chip Sclk signal of the present invention's output, Sen signal and Sdata signal format satisfy AFE chip three line control signal interface formats, can directly export to the AFE chip;
3, but AFE chip register of the present invention adopts 8Nbit data regulating allocation, and the AFE chip register figure place of using at present all has from 16bit to 64bit, and the present invention can use at any AFE chip;
4, reception readout register data module of the present invention can be carried out retaking of a year or grade with the buffer status value with AFE chip output of register retaking of a year or grade function, and after carrying out the data format conversion, whether successful data storages, this function can support the AFE chip register to write judgement.
Description of drawings
Fig. 1 is the theory of constitution figure of on-line control controller of the present invention;
Fig. 2 is string and the schematic diagram of modular converter in the on-line control controller of the present invention;
Fig. 3 is general RS232 serial data data format;
Fig. 4 is the schematic diagram of format conversion and fan-out modular in the on-line control controller of the present invention;
Fig. 5 is the schematic diagram that receives the readout register data module in the on-line control controller of the present invention.
Embodiment
As shown in Figure 1, theory of constitution figure for on-line control controller of the present invention, this on-line control controller system can carry out online register configuration to multichannel analog front-end A FE chip for the adjusting control of the serial ports register of the AFE (analog front end) AFE chip that uses in signal processing circuit.This system comprises string also modular converter, format conversion and fan-out modular, reception readout register data module.String and modular converter are gone here and there to the serial data of outside input and are changed, and the parallel data enable signal of output parallel data and correspondence is to format conversion and fan-out modular; Described serial data comprises the register data of AFE (analog front end) AFE chip.Format conversion and fan-out modular are according to the parallel data of input and corresponding parallel data enable signal and work master clock, the three line serial ports clock signals (being respectively on-line control AFE chip Sclk signal, on-line control AFE chip Sdata signal and on-line control AFE chip Sen signal) of AFE chip requirement are satisfied in output.Receive the data that the readout register data module receives the input of AFE chip SDO pin, on-line control AFE chip Sclk signal, on-line control AFE chip Sen signal according to format conversion and fan-out modular output, output in the fixing memory after the buffer status of AFE chip done string and conversion, carry out data storages.
As shown in Figure 2, string and modular converter comprise three d type flip flops, judge that serial data begins the unit for one, a baud rate counter unit, a valid data sign generation unit is gone here and there and converting unit for one, an enable counter unit, data are spliced and lock unit.All unit all have the input of work master clock to count or data synchronization processing.Through d type flip flop 1, d type flip flop 2 utilizes master clock to carry out two samplings and eliminates metastable state after the serial data input.Judging that serial data begins the unit input serial data is carried out the initial judgement of data.Because the serial data form is fixed form, as shown in Figure 3, first of a frame data are initial low level bit, after connect the 8bit data bit, the no parity check position, last the position be high position of rest.Must be a low level signal at the data starting end.Serial data to two-stage d type flip flop time-delay detects, and is 0 when one-level time-delay serial data occurring, and secondary time-delay serial data is 1 o'clock, is serial data effective zero hour, and export data enable signal this moment is 1 (effectively).According to the counter values of baud rate counter output, counting down to serial ports 8bit valid data and 1 moment that position of rest finishes, the output data enable signal becomes 0, one frame serial data and is sent.Be 0 or when the valid data enable signal of valid data sign generation unit output is 1 (effectively) at serial data two-stage time-delay serial data, and when the data enable signal that the judgement serial data begins to export the unit is 1 (effectively), the work master clock is carried out the baud rate rolling counters forward, and when data enable signal is 0 (invalid), carry out the baud rate counter O reset.Multiple relation between the baud rate that serial communication adopts and the work master clock frequency is calculated, and obtains what cycles that each serial ports valid data accounts for master clock, thereby carries out accurate serial data counting.Valid data sign generation unit is according to the counter values of baud rate counter input, be 0 and counter values in the middle of the cycle the 1st of serial data constantly (this is the stable state of the 1st serial data constantly) at serial data two-stage time-delay serial data, valid data are enabled to be output as 1 (effectively), the moment (this is the stable state of the 10th serial data constantly) enables to be output as 0 (invalid) with valid data in the middle of the cycle of the 10th of serial data.The valid data enable signal is input to d type flip flop 3, carries out 1 grade of d type flip flop time-delay.String and converting unit, squeeze into the parallel data register according to the count value of the baud rate counter of input at the 2bit data of the serial ports 10 Bits Serial data two-stage that (data stabilization state) respectively will this moment constantly in the middle of data cycle of the bits per inch certificate of 9bit data (being the 8bit valid data part of Fig. 3) serial data of delaying time, finish serial data to the conversion of parallel data.It is 1 that the parallel data register enables at valid data, and it is that 0 (being next frame serial data significant instant) carried out the zero clearing of parallel data register that one-level time-delay valid data enable.String and converting unit output parallel data (8bit).Data splicing and lock unit, splicing the rolling counters forward value in data is 1 o'clock, the parallel data (8bit) of string and conversion input is input among the low 8bit of 16bit parallel data register, splicing the rolling counters forward value in data is 2 o'clock, the parallel data (8bit) of string and conversion input is input to (data splicing counter can be the multidigit counter among the high 8bit of 16bit parallel data register, the parallel data of output 8Nbit, this sentences 8X2=16bit is the example explanation).When the data splicing enable signal of enable counter output is 1 (effectively), the 16bit data counter is resetted, when data splicing enable signal is 0 (invalid), the 16bit data counter is counted, be (count range is adjustable) in the serial data periodic quantity scope time at 16bit data counter counting, produce 16bit parallel data enable signal, and assignment is 1, other numerical value assignment are 0, enabling in the 16bit parallel data is 1 o'clock, synchronous through the work master clock, the 16bit parallel data is exported.It is synchronous that 16bit parallel data enable signal also passes through the work master clock, exports final 16bit parallel data enable signal.It is 0 that the enable counter unit judges enables at valid data, it is 1 o'clock that one-level time-delay valid data enable, be the serial data end of input moment, producing a high level pulsewidth is the serial data end id signal of 4 work master clock cycles, this signal is counted, when count value is 2, produce the data splicing enable signal that 2 groups of serial datas of a sign are finished, and simultaneously with the count value zero clearing.And data are spliced the splicing of counter values and data enable output.
As shown in Figure 4, format conversion and fan-out modular comprise a frequency counter unit, the frequency division data produce and counter signals produces the logic matrix unit, three line traffic control Sclk produce matrix unit, the serial data counter unit, the string code enables matrix unit, parallel data latch units and parallel serial conversion unit.All unit all have the input of work master clock to count or data synchronization processing.The work master clock enters the frequency counter unit, master clock is carried out setting the counting (this sentences master clock 4 frequency divisions is that example describes) of frequency division value, when the rolling counters forward value less than 4 the time, the frequency counter counting, when count value equals 4, be 1 with counter again assignment, so count cycle is also exported count value.The generation of frequency division data and counter signals generation logic matrix unit are 1: 1 frequency-dividing clock according to count value generation duty ratio, be 2 o'clock in count value namely, frequency-dividing clock is output as height, during other count values, frequency-dividing clock is output as low, realizes 4 frequency divisions to master clock.It is the low level moment with the on-line control AFE chip Sen signal of inputting that three line traffic control Sclk produce matrix, with the input the anti-phase rear assignment of frequency-dividing clock to on-line control AFE chip Sclk signal, be the moment of high level at on-line control AFE chip Sen signal, on-line control AFE chip Sclk signal assignment is fixing high level 1.The serial data counter unit judges that the counter enable signals of input is 1, perhaps the count value of serial data counter own is not the moment that began to count as the serial data counter in 0 o'clock, (can regulate less than default parallel data bit value in serial data rolling counters forward value, this sentences 16bit parallel data preset value is that example describes) 17 (for the value of 16+1) and be 1 o'clock at the rolling counters forward signal, carry out the serial data rolling counters forward, when the serial data counter values reaches 17 and rolling counters forward signal when being 1, the serial data counter is carried out the zero clearing assignment, serial data rolling counters forward numerical value is exported.It is moment of 1 according to the rolling counters forward signal of input that string code enables matrix, less than preset value 17 and greater than 0 o'clock, is 0 to on-line control AFE chip Sen signal assignment in count value, is 1 to Sen signal assignment constantly at other.The parallel data latch units enables the 16bit parallel data signal of outside input to be effective 1 o'clock of data in parallel data, according to the work master clock parallel data is latched.Parallel serial conversion unit is the low moment with the 16bit parallel data that latchs at the on-line control AFE chip Sen signal of input, with the output that is shifted of the parallel latch data of 16bit, exports on-line control AFE chip Sdata signal.
As shown in Figure 5, receive the readout register data module and comprise 2 d type flip flops, data latch and go here and there and converting unit, signal lag and logic matrix unit.Because the moment of AFE chip Sdo input is relevant with the moment of on-line control AFE chip Sen.AFE chip Sclk signal and AFE chip Sen signal are carried out suitable time-delay, so that the trailing edge of the AFE chip Sclk signal after the time-delay is aimed at the centre of AFE chip Sdo pin data, so that be the output effectual time of Sdo pin data during the AFE chip Sen signal low level after the time-delay.Enable Startup time according to Sen, master clock is counted, count value is the signal lag number.AFE chip Sdo input serial data, carry out the two samplings of data through 2 grades of d type flip flops, eliminate and to be input to data after the data metastable state and to latch and go here and there and converting unit, when the AFE chip Sen signal after time-delay is 0 (data are effective), AFE chip Sclk signal trailing edge after time-delay constantly, the AFE chip Sdo data of two-stage time-delay are latched, and go here and there and change, output 8bit parallel data is also carried out the data exterior storage.
The content that is not described in detail in the specification of the present invention belongs to those skilled in the art's known technology.
Claims (3)
1. the on-line control controller of an analog front-end chip is characterized in that comprising: string and modular converter, format conversion and fan-out modular, reception readout register data module, wherein:
String and modular converter: the serial data of outside input is gone here and there and changed, and output parallel data and corresponding parallel data enable signal are to format conversion and fan-out modular; Described serial data comprises the register data of AFE (analog front end) AFE chip;
Format conversion and fan-out modular: according to the parallel data of input and corresponding parallel data enable signal and work master clock, three line serial ports clock signals of AFE chip requirement are satisfied in output, described three line serial ports clock signals are respectively on-line control AFE chip Sclk signal, on-line control AFE chip Sdata signal and on-line control AFE chip Sen signal;
Receive the readout register data module: the data that receive the input of AFE chip SDO pin, on-line control AFE chip Sclk signal, on-line control AFE chip Sen signal according to format conversion and fan-out modular output, output in the fixing memory after the buffer status of AFE chip done string and conversion, carry out data storages;
Described format conversion and fan-out modular comprise that frequency counter unit, the generation of frequency division data and counter signals logic matrix unit, three line traffic control Sclk produce matrix unit, serial data counter unit, the code of going here and there enables matrix unit, parallel data latch units and parallel serial conversion unit, wherein:
The frequency counter unit: the work master clock is carried out setting the counting of frequency division value, and count value is from 1 to the frequency division value circulation of setting, and count value is delivered to frequency division data generation unit;
The frequency division data produce and counter signals logic matrix unit: the count value generation duty ratio that transmits according to the frequency counter unit is 1: 1 frequency-dividing clock and delivers to three line traffic control Sclk generation matrix unit; The serial data enable signal that produces the serial data counter unit according to the parallel data enable signal is delivered to the serial data counter unit, the parallel data figure place bit number that the serial data enable signal is processed according to need, the serial data counting number of control serial data counter unit, described serial data enable signal comprises the full bit count signal of the serial data counter unit of complete cycle; The serial data enable signal of serial data counter unit effectively opens and begins constantly to delay master clock cycle of parallel data enable signal;
Three line traffic control Sclk produce matrix unit: the frequency-dividing clock and the on-line control AFE chip Sen signal that receive input, when on-line control AFE chip Sen signal for enabling when invalid, the frequency-dividing clock of input is anti-phase rear as on-line control AFE chip Sclk signal and output, when on-line control AFE chip Sen signal for enabling when effective, with the frequency-dividing clock of input as on-line control AFE chip Sclk signal and output;
Serial data counter unit: when the serial data enable signal of input is effective, begin counting constantly as counter, in count value less than default parallel data bit value 8N+1 and when the rolling counters forward signal is effective, carry out the serial data rolling counters forward, when the serial data count value reaches default parallel data bit value and rolling counters forward signal and remains valid, count value is carried out again counting after the zero clearing, count value is delivered to the string code and is enabled matrix unit, and N is positive integer;
String code enables matrix unit: when the frequency division data of input produce and the serial data enable signal of counter signals logic matrix unit effective, simultaneously in the count value of serial data counter unit output less than preset value 8N+1 and greater than 0 o'clock, on-line control AFE chip Sen signal is set for effectively; Equal 0 or during greater than preset value 8N+1 in the count value of serial data counter unit output, on-line control AFE chip Sen invalidating signal is set; When the serial data enable invalidating signal of the generation of frequency division data and counter signals logic matrix unit, on-line control AFE chip Sen signal is set keeps current state;
The parallel data latch units: the parallel data in input enables when effective, delivers to parallel serial conversion unit after according to the work master clock parallel data of input being latched;
Parallel serial conversion unit: enable when effective in parallel data, the 8Nbit parallel data is lower synchronously at master clock, latch, enable to keep current latch data when invalid in parallel data; When on-line control AFE chip Sen signal is effective, export as on-line control AFE chip Sdata signal by order from high to low after respectively the parallel data that latchs being converted to serial data.
2. the on-line control controller of a kind of analog front-end chip according to claim 1, it is characterized in that: described string and modular converter comprise that three d type flip flops, judgement serial data begin unit, baud rate counter unit, valid data sign generation unit, string and converting unit, enable counter unit, data splicing and lock unit, wherein:
The first d type flip flop: the serial data of outside input delayed time obtains serial data after the one-level time-delay, and the serial data after the one-level time-delay is sent into simultaneously the second d type flip flop and judged that serial data begins the unit;
The second d type flip flop: the serial data after the one-level time-delay delayed time again obtains serial data after the secondary time-delay, and the serial data after the secondary time-delay is sent into simultaneously judge that serial data begins unit, baud rate counter unit, valid data sign generation unit, string and converting unit;
Judge that serial data begins the unit: the serial data to input carries out the initial judgement of data, when the serial data after the one-level time-delay be 0 and the secondary time-delay after serial data when being 1, the output data enable signal is to the baud rate counter unit; When the count value of baud rate counter unit count down to frame serial data end, stop to export data enable signal;
Baud rate counter unit: when the serial data after the secondary time-delay is 0 and judges that serial data begins the data enable signal of unit output when effective, perhaps when the valid data enable signal of valid data sign generation unit output effectively and judge that serial data begins the data enable signal of unit output when effective, the work master clock counted and count value delivered to simultaneously judge that serial data begins unit, valid data sign generation unit, string and converting unit; When judging that serial data begins the data enable signal of unit output when invalid, carries out the zero clearing of count value;
Valid data sign generation unit: when the serial data after the secondary time-delay is 0 and the count value of baud rate counter unit input in the middle of the first bit data cycle in a frame serial data constantly the time, output valid data enable signal is also delivered to baud rate counter unit, 3d flip-flop, enable counter unit simultaneously; When the count value of baud rate counter unit input in the middle of last bit data cycle in same frame serial data constantly the time, stop to export the valid data enable signal;
3d flip-flop: the valid data enable signal of input delayed time obtains valid data enable signal after the one-level time-delay, and the valid data enable signal after the one-level time-delay is sent into enable counter unit, string and converting unit simultaneously;
String and converting unit: according to the count value of baud rate counter unit input, a frame serial data in the middle of data cycle of the bits per inch certificate of first and last bit data, constantly respectively the serial data after the secondary time-delay of correspondence is squeezed into the first parallel data register, the data in the first parallel data register are sent into data and are spliced and lock unit; The first parallel data register the valid data enable signal effectively and the valid data enable signal after the one-level time-delay carry out clear operation when invalid;
Enable counter unit: when the valid data enable signal when the valid data enable signal after the time-delay of invalid and one-level is effective, produce a frame serial data and finish id signal, one frame serial data is finished id signal to be counted, when count value arrives the threshold value N that sets, produce data splicing enable signal, data are spliced after enable signal and count value are delivered to data splicing and lock unit count value is carried out zero clearing;
Data splicing and lock unit: inside arranges a 8Nbit data counter and produces 8Nbit parallel data enable signal; The parallel data of input is input in the address location of the second parallel data register, and the data bits of the second parallel data register equals the figure place of N the first parallel data register doubly; When the data splicing enable signal of enable counter unit output is invalid, keep the current data value constant in two data registers; When the data splicing enable signal of enable counter unit output is effective, the 8Nbit data that splicing is good latch, the 8Nbit data counter is resetted, when data splicing enable signal is invalid, the 8Nbit data counter is counted, be in the serial data periodic quantity scope time at 8Nbit data counter counting, produce 8Nbit parallel data enable signal and also be set to enable effectively, 8Nbit data counter counting be arrange outside the serial data periodic quantity scope time 8Nbit parallel data enable signal enable invalid; Enable when effective in the 8Nbit parallel data, synchronous through the work master clock, the output of 8Nbit parallel data is also synchronous through the work master clock to 8Nbit parallel data enable signal, export final 8Nbit parallel data enable signal.
3. the on-line control controller of a kind of analog front-end chip according to claim 1 and 2, it is characterized in that: described reception readout register data module comprises that two d type flip flops, data latch and go here and there and converting unit, signal lag and logic matrix unit, wherein:
Two d type flip flops: the data of AFE chip SDO pin input are carried out being input to after the two-stage time-delay data latch and go here and there and converting unit;
Signal lag and logic matrix unit: AFE chip Sclk signal and AFE chip Sen signal are carried out suitable time-delay, so that the trailing edge of the AFE chip Sclk signal after the time-delay is aimed at the centre of AFE chip Sdo pin data, so that be the output effectual time of Sdo pin data during the AFE chip Sen signal low level after the time-delay;
Data latch and go here and there and converting unit: when the AFE chip Sen signal after the time-delay is effective, AFE chip Sclk signal trailing edge after time-delay constantly, AFE chip Sdo pin data after the two-stage time-delay are latched and go here and there and change, with the buffer status of AFE chip do the string and the conversion after, output in the fixing memory, carry out the data storage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108873766A (en) * | 2017-08-15 | 2018-11-23 | 北京旷视科技有限公司 | A kind of I/O control circuitry and camera apparatus for camera |
| CN111786723A (en) * | 2020-06-29 | 2020-10-16 | 安徽理工大学 | PPM code generating device for VLC system for detecting miner signs |
| CN114401014A (en) * | 2022-01-04 | 2022-04-26 | 电子科技大学 | Low-power-consumption parallel-serial conversion circuit |
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| US20090065929A1 (en) * | 2005-03-31 | 2009-03-12 | Kazuhiko Hiranuma | Multi-chip semiconductor device |
| CN202551008U (en) * | 2012-03-26 | 2012-11-21 | 北京空间机电研究所 | Controller of analog-to-digital conversion chip |
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| US20090065929A1 (en) * | 2005-03-31 | 2009-03-12 | Kazuhiko Hiranuma | Multi-chip semiconductor device |
| CN202551008U (en) * | 2012-03-26 | 2012-11-21 | 北京空间机电研究所 | Controller of analog-to-digital conversion chip |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108873766A (en) * | 2017-08-15 | 2018-11-23 | 北京旷视科技有限公司 | A kind of I/O control circuitry and camera apparatus for camera |
| CN111786723A (en) * | 2020-06-29 | 2020-10-16 | 安徽理工大学 | PPM code generating device for VLC system for detecting miner signs |
| CN114401014A (en) * | 2022-01-04 | 2022-04-26 | 电子科技大学 | Low-power-consumption parallel-serial conversion circuit |
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