CN102571075A - Limited overturning dynamic logic circuit with scanning function - Google Patents

Limited overturning dynamic logic circuit with scanning function Download PDF

Info

Publication number
CN102571075A
CN102571075A CN2012100124772A CN201210012477A CN102571075A CN 102571075 A CN102571075 A CN 102571075A CN 2012100124772 A CN2012100124772 A CN 2012100124772A CN 201210012477 A CN201210012477 A CN 201210012477A CN 102571075 A CN102571075 A CN 102571075A
Authority
CN
China
Prior art keywords
input
scan
output
scanning
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012100124772A
Other languages
Chinese (zh)
Inventor
李振涛
郭阳
宋芳芳
刘蓬侠
陈书明
刘祥远
唐涛
胡春媚
张子杰
付志刚
王丽娟
冯国柱
邢冬生
高维娜
唐茜茜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National University of Defense Technology
Original Assignee
National University of Defense Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National University of Defense Technology filed Critical National University of Defense Technology
Priority to CN2012100124772A priority Critical patent/CN102571075A/en
Publication of CN102571075A publication Critical patent/CN102571075A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a limited overturning dynamic logic circuit with a scanning function, which comprises a peripheral module and at least one LSDL core unit, wherein the LSDL core unit comprises a dynamic gate circuit, an N-C2MOS latch, a scanning enable input port, a scanning input port, a scanning output port and a scanning input logic device. The peripheral module comprises an enable control module, an input end of the scanning input logic device is respectively connected with the scanning enable input port, the scanning input port and clock signals, an output end of the scanning input logic device is connected with an input end of the N-C2MOS latch, and the scanning output port is connected with an output end of the N-C2MOS latch. An input end of the enable control module is connected with the scanning enable input port, and an output end of the enable control module is connected with a control end of a pull-down logical network. The limited overturning dynamic logic circuit has the advantages of good logic measurability, small time delay influence, small overall area expenses and low power consumption.

Description

Limited upset dynamic logic circuit with scan function
Technical field
The present invention relates to the high speed dynamic gate design field of digital integrated circuit, be specifically related to a kind of limited upset dynamic logic circuit with scan function.
Background technology
As shown in Figure 1; The LSDL unit of the limited upset dynamic logic of prior art (Limited Switching Dynamic Logic:LSDL) circuit generally can be divided into two-stage: the first order is a dynamic gate 1, is used for the quick evaluation of many inputs complex logic; The second level is a N-C 2MOS latch 2.Dynamic gate 1 and N-C 2MOS latch 2 shared clocks, when dynamic gate 1 evaluation, N-C 22 conductings of MOS latch, dateout is upgraded; When dynamic gate 1 preliminary filling, N-C 2MOS latch 2 cuts out, and dateout keeps.N-C 2The function that MOS latch 2 has latching simultaneously and amplifies, the utilance of metal-oxide-semiconductor is high, and the LSDL logic has the advantage that speed is fast, low in energy consumption and area is little, in the design of high-speed digital circuit, has a good application prospect.But because preliminary filling is all wanted in the every bat of limited upset dynamic logic of prior art, but because N-C 2The MOS latch is kept apart dynamic gate and output, has reduced effective upset rate of LSDL logic.And along with chip-scale constantly increases, it is more important and difficult that the design for Measurability of chip becomes.It is an important technology that improves the chip measurability that scan chain inserts, and the latch or the trigger that are connected into scan chain must have scan function.Common LSDL logic is not supported scan function, can't be connected in the scan chain, causes relevant with it logic measurability to reduce.In order to improve the design measurability of LSDL logic, need make improvements, make it have scan function.The at present existing several kinds of implementation methods of supporting the LSDL logic of scan functions, but existing method generally has time-delay, shortcoming that area overhead is big.
Summary of the invention
The technical problem that the present invention will solve provides the limited upset dynamic logic circuit with scan function that a kind of logic measurability is good, the time-delay influence is little, the total area expense is little, low in energy consumption.
In order to solve the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of limited upset dynamic logic circuit with scan function, and it comprises peripheral module and at least one LSDL core cell, said LSDL core cell comprises dynamic gate, N-C 2MOS latch, scan enable input port, scan input end mouth, scanning output end mouth, be used for when said scan enable input input signal is effective the signal of scan input end mouth is delivered to the scan input logic of scanning output end mouth output; Said peripheral module comprises the energy control module that makes that is used for when said scan enable input is imported useful signal, closing the drop-down logical network of said dynamic gate; The input of said scan input logic links to each other with scan enable input, scan input end mouth and clock signal respectively, the output of said scan input logic and N-C 2The input of MOS latch links to each other, said scanning output end mouth and said N-C 2The output of MOS latch links to each other; The said input of energy control module that makes links to each other with said scan enable input, and the said output of energy control module that makes links to each other with the control end of drop-down logical network.
Further improvement as technique scheme:
Said scan input logic comprises the NMOS pipe and the 2nd NMOS pipe of series connection successively, and said NMOS pipe is positioned at by N-C 2One side of MOS latch input, said scan enable input links to each other with the grid of NMOS pipe, and said scan input end mouth links to each other with the grid of the 2nd NMOS pipe.
Said LSDL core cell also comprises and being used for N-C 2The scanning output logic of the output signal lag output of MOS latch, said scanning output logic comprises delay circuit, said scanning output end mouth is through delay circuit and said N-C 2The output of MOS latch links to each other.
Said peripheral module also comprises the clock generating module that is used to produce narrow pulse signal, and the input of said clock generating module links to each other with standard clock signal, the output of said clock generating module respectively with dynamic gate, N-C 2MOS latch and scan input logic link to each other.
The present invention has following advantage:
1, the present invention is through making energy control module in LSDL core cell increase scan enable input port, scan input end mouth, scanning output end mouth and scan input logic, peripheral module increase; Can control the LSDL core cell normal and scan between two kinds of mode of operations and switch through scan enable signals; Can support scan function and make up scan chain, the logic measurability is good; And it realizes not increasing the stacks as high of the NMOS pipe on the critical path, and is little to the time-delay influence of critical path.
2, the present invention includes peripheral module and at least one LSDL core cell, peripheral module and LSDL core cell are separate, can realize making in the peripheral module the shared of energy control module, and the total area expense is little, low in energy consumption.
3, LSDL core cell of the present invention further comprises and being used for N-C 2The scanning output logic of the output signal lag output of MOS latch; Make that the output time-delay of scanning output end mouth is bigger; Guaranteed that next scan input end mouth has enough retention times; Make the present invention directly to be connected in series and constitute scan chain, and occur the retention time can avoid being connected in series the time and break rules with other the timing unit circuit of of the same type or other types with the timing unit circuit of of the same type or other types.
4, peripheral module of the present invention further comprises the clock generating module that is used to produce narrow pulse signal, clock generating module input dynamic circuit and N-C 2The high level of the work clock of MOS latch is a burst pulse, and the retention time of input port is little, and the output time-delay of output port is big, can connect and compose scan chain with other various types of timing units, and compatible performance is good; Because the retention time of input port is little, the present invention can also use as d type flip flop; The clock generating module is located in the peripheral module, also can realize shared to the clock generating module can further reducing total area expense and power consumption.
Description of drawings
Fig. 1 is the circuit theory sketch map of the basic element circuit of prior art.
Fig. 2 is the circuit theory sketch map of the embodiment of the invention one.
Fig. 3 is the circuit theory sketch map of the embodiment of the invention two.
Fig. 4 is the circuit theory sketch map of the embodiment of the invention three.
Marginal data: 1, dynamic gate; 11, drop-down logical network; 2, N-C 2The MOS latch; 3, scan input logic; 4, make energy control module; 5, scanning output logic; 51, delay circuit; 6, clock generating module; 7, LSDL unit; 8, LSDL core cell.
Embodiment
The scan chain circuits that to combine a LSDL element circuit and two length below respectively be N amounts to three embodiment the limited upset dynamic logic circuit that the present invention has scan function is further specified:
Embodiment one:
Present embodiment is the LSDL unit with limited upset dynamic logic circuit of scan function, and is as shown in Figure 2, and present embodiment comprises peripheral module and a LSDL core cell 8, and LSDL core cell 8 comprises dynamic gate 1, N-C 2MOS latch 2, scan enable input port SE, scan input end mouth SI, scanning output end mouth SO, be used for when scan enable input SE input signal is effective the signal of scan input end mouth SI is delivered to the scan input logic 3 of scanning output end mouth SO output; Peripheral module comprise be used for when scan enable input SE input useful signal, closing dynamic gate 1 drop-down logical network 11 make energy control module 4; The input of scan input logic 3 links to each other with scan enable input SE, scan input end mouth SI and clock signal respectively, the output of scan input logic 3 and N-C 2The input of MOS latch 2 links to each other, scanning output end mouth SO and N-C 2The output of MOS latch 2 links to each other; The input of energy control module 4 is linked to each other with scan enable input SE, the output of energy control module 4 is linked to each other with the control end of drop-down logical network 11.
Input signal (scan enable signals) high level of present embodiment scan enable input port SE is effectively, controls two kinds of mode of operations of the normal of limited upset dynamic logic circuit and scanning through scan enable signals:
1) when scan enable signals is 1 (high level); Present embodiment is in the scanning work pattern; Make energy control module 4 that all control inputs are changed to 0; Drop-down logical network 11 is closed, and scan input logic 3 is started working, and during clk_p is height, the signal of scan input end mouth SI is delivered to scanning output end mouth SO output;
2) when scan enable signals is 0 (low level); Present embodiment is in normal mode of operation; Scan input logic 3 is closed, and makes energy control module 4 that scan enable signals directly is passed to drop-down logical network 11, and present embodiment is carried out normal normal logic and the latch operation carried out.
Scan input logic 3 comprises the NMOS pipe N0 and the 2nd NMOS pipe N1 of series connection successively, and NMOS pipe N0 is positioned at by N-C 2One side of MOS latch 2 inputs, scan enable input SE links to each other with the grid of NMOS pipe N0, and scan input end mouth SI links to each other with the grid of the 2nd NMOS pipe N1.Scan input logic 3 constitutes drop-down path, and this drop-down path is in effectively conducting when (high level) of scan enable signals, exports after the signal of scan input end mouth SI input is delivered to scanning output end mouth SO.
LSDL core cell 8 also comprises and being used for N-C 2The scanning output logic 5 of the output signal lag output of MOS latch 2, scanning output logic 5 comprises delay circuit 51, scanning output end mouth SO is through delay circuit 51 and N-C 2The output of MOS latch 2 links to each other.Because output output signal SO delivers to scanning output end mouth SO after delaying time through delay circuit 41; So the output of SO port time-delay is bigger; Guaranteed that next scan input end mouth SI has enough retention times; Thereby present embodiment can directly be connected in series with the timing unit circuit of of the same type or other types and constitute scan chain, and occurs the retention time can avoid being connected in series with other the timing unit circuit of of the same type or other types the time and break rules.
The peripheral module of present embodiment has also increased on the basis of prior art basic element circuit and has been used to produce the work clock of the clock generating module 6 of narrow pulse signal as the LSDL logic; The input of clock generating module 6 links to each other with standard clock signal, the output of clock generating module 6 respectively with dynamic gate 1, N-C 2MOS latch 2 and scan input logic 3 link to each other.Clock generating module 6 is a monostable trigger-action circuit, triggered by the rising edge of input clock signal clk, on output clock clk_p, produces the effective burst pulse of high level.Because clock generating module 6 produces narrow pulse signal, and imports dynamic gate 1 and N-C respectively 2 MOS latch 2, dynamic gate 1 and N-C 2The high level of the work clock clk_p of MOS latch 2 all is a narrow pulse signal, and the retention time of input port is little, so present embodiment can also use as d type flip flop.
Compared with prior art, present embodiment has increased by 3 ports: scan enable port SE, scanning input FPDP SI and scanning output end mouth SO; In the LSDL core cell 8, increased scan input logic 3 in dynamic gate 1 part, at N-C 2The output Q of MOS latch 2 has increased scanning output logic 5; In addition, present embodiment has increased peripheral module (making energy control module 4 and clock generating module 6), and the quantity of peripheral module can be set to one or more flexibly according to practical application.
Embodiment two:
Present embodiment is the limited upset dynamic logic scan chain circuits with scan function of N for forming length through the LSDL unit among a plurality of embodiment one.Present embodiment and embodiment one are basic identical, and its main difference point is: present embodiment comprises N independently LSDL unit 7, and each LSDL unit 7 all comprises 1 peripheral module and 1 LSDL core cell 8.As shown in Figure 3; The length that makes up in the present embodiment is that the scan chain of N is done as a whole instantiation N time with the LSDL unit 7 among the embodiment one; Make it comprise that N is the LSDL unit 7 that chain distributes; And the scanning output end mouth SO of previous stage LSDL unit 7 links to each other with the scan input end mouth SI of next stage LSDL unit 7, and the like, constituting length is the scan chain of N.
Embodiment three:
Present embodiment is that length is the limited upset dynamic logic scan chain circuits with scan function of N.Present embodiment and embodiment one are basic identical, and its main difference point is: present embodiment comprises 1 public peripheral module and N LSDL core cell 8.As shown in Figure 4; The length that makes up in the present embodiment is that the scan chain of N only connects N LSDL core cell 8 and is chain and distributes; N LSDL core cell 8 shared peripheral modules; The output that makes energy control module 4 and clock generating module 6 is as a common signal driving N LSDL core cell 8 simultaneously, and this implementation method is applicable to and enables the design imported jointly that its advantage is that area is little, low in energy consumption.
The above only is a preferred implementation of the present invention, and protection scope of the present invention also not only is confined to the foregoing description, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art in the some improvement and the retouching that do not break away under the principle of the invention prerequisite, these improvement and retouching also should be regarded as protection scope of the present invention.

Claims (4)

1. limited upset dynamic logic circuit with scan function is characterized in that: it comprises peripheral module and at least one LSDL core cell (8), and said LSDL core cell (8) comprises dynamic gate (1), N-C 2MOS latch (2), scan enable input port, scan input end mouth, scanning output end mouth, be used for when said scan enable input input signal is effective the signal of scan input end mouth is delivered to the scan input logic (3) of scanning output end mouth output; Said peripheral module comprise be used for when said scan enable input input useful signal, closing the drop-down logical network of said dynamic gate (1) (11) make energy control module (4); The input of said scan input logic (3) links to each other with scan enable input, scan input end mouth and clock signal respectively, the output and the N-C of said scan input logic (3) 2The input of MOS latch (2) links to each other, said scanning output end mouth and said N-C 2The output of MOS latch (2) links to each other; The said input of energy control module (4) that makes links to each other with said scan enable input, and the said output of energy control module (4) that makes links to each other with the control end of drop-down logical network (11).
2. the limited upset dynamic logic circuit with scan function according to claim 1 is characterized in that: said scan input logic (3) comprises the NMOS pipe and the 2nd NMOS pipe of series connection successively, and said NMOS pipe is positioned at by N-C 2One side of MOS latch (2) input, said scan enable input links to each other with the grid of NMOS pipe, and said scan input end mouth links to each other with the grid of the 2nd NMOS pipe.
3. the limited upset dynamic logic circuit with scan function according to claim 1 and 2, it is characterized in that: said LSDL core cell (8) also comprises and being used for N-C 2The scanning output logic (5) of the output signal lag output of MOS latch (2), said scanning output logic (5) comprises delay circuit (51), said scanning output end mouth is through delay circuit (51) and said N-C 2The output of MOS latch (2) links to each other.
4. the limited upset dynamic logic circuit with scan function according to claim 3; It is characterized in that: said peripheral module also comprises the clock generating module (6) that is used to produce narrow pulse signal; The input of said clock generating module (6) links to each other with standard clock signal, the output of said clock generating module (6) respectively with dynamic gate (1), N-C 2MOS latch (2) and scan input logic (3) link to each other.
CN2012100124772A 2012-01-16 2012-01-16 Limited overturning dynamic logic circuit with scanning function Pending CN102571075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012100124772A CN102571075A (en) 2012-01-16 2012-01-16 Limited overturning dynamic logic circuit with scanning function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012100124772A CN102571075A (en) 2012-01-16 2012-01-16 Limited overturning dynamic logic circuit with scanning function

Publications (1)

Publication Number Publication Date
CN102571075A true CN102571075A (en) 2012-07-11

Family

ID=46415655

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012100124772A Pending CN102571075A (en) 2012-01-16 2012-01-16 Limited overturning dynamic logic circuit with scanning function

Country Status (1)

Country Link
CN (1) CN102571075A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960684A (en) * 2016-01-11 2017-07-18 中芯国际集成电路制造(上海)有限公司 Limit the dynamic logic circuit and static RAM of upset
CN108152719A (en) * 2016-12-02 2018-06-12 Arm 有限公司 For the scanning element of dual-ported memory application

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178838A1 (en) * 2003-03-13 2004-09-16 International Business Machines Corporation Variable pulse width and pulse separation clock generator
CN101174831A (en) * 2006-10-31 2008-05-07 国际商业机器公司 Scannable dynamic logic latch circuit
US7501850B1 (en) * 2007-12-20 2009-03-10 International Business Machines Corporation Scannable limited switch dynamic logic (LSDL) circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178838A1 (en) * 2003-03-13 2004-09-16 International Business Machines Corporation Variable pulse width and pulse separation clock generator
CN101174831A (en) * 2006-10-31 2008-05-07 国际商业机器公司 Scannable dynamic logic latch circuit
US7501850B1 (en) * 2007-12-20 2009-03-10 International Business Machines Corporation Scannable limited switch dynamic logic (LSDL) circuit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
《中国博士学位论文全文数据库信息科技辑》 20090731 李振涛 "高性能DSP关键电路及EDA技术研究" 正文第24页 1-4 , 第7期 *
《第十五届计算机工程与工艺年会暨第一届微处理器技术论坛论文集（A辑）》 20110812 冯国柱等 "高速多端口寄存器文件的可测性设计" 264-268 1-4 , *
冯国柱等: ""高速多端口寄存器文件的可测性设计"", 《第十五届计算机工程与工艺年会暨第一届微处理器技术论坛论文集（A辑）》 *
李振涛: ""高性能DSP关键电路及EDA技术研究"", 《中国博士学位论文全文数据库信息科技辑》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960684A (en) * 2016-01-11 2017-07-18 中芯国际集成电路制造(上海)有限公司 Limit the dynamic logic circuit and static RAM of upset
CN108152719A (en) * 2016-12-02 2018-06-12 Arm 有限公司 For the scanning element of dual-ported memory application
CN108152719B (en) * 2016-12-02 2022-09-06 Arm 有限公司 Scan cell for dual port memory applications

Similar Documents

Publication Publication Date Title
CN105553447B (en) Clock switch circuit
CN201409126Y (en) Clock synchronous circuit in serialization of high-speed parallel data
CN104378114A (en) Method for achieving synchronization of multichannel analog-digital converter
CN109120257A (en) A kind of low jitter frequency-dividing clock circuit
CN104617926A (en) Pulse swallowing type clock synchronization circuit
CN102497201A (en) True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption
CN107517046A (en) A kind of multi-clock selection switching circuit, clock switching chip and method
CN101350612B (en) Circuit for preventing gating clock bur
CN106788353A (en) A kind of skewed clock correcting method and circuit, terminal device
CN101110582B (en) Delayed control circuit
CN103199864B (en) A kind of gradual approaching A/D converter
CN110007217A (en) A kind of low-power consumption boundary scanning test method
CN102195619A (en) Method and circuit for detecting and eliminating signal glitch
Tsai et al. A novel low gate-count pipeline topology with multiplexer-flip-flops for serial link
CN102880441B (en) First in-first out device and realizing method thereof
CN102571075A (en) Limited overturning dynamic logic circuit with scanning function
CN103066960B (en) Generating device and method of large-amplitude ultra-high speed synchronization pulse
CN202713274U (en) Structure of high speed clock data recovery system
CN103208980A (en) Window voltage comparison device
CN202444477U (en) High-speed and low-power true single-phase clock 2/3 dual-modulus prescaler
CN203180865U (en) Time-delay generation circuit with pulse width adjustable
CN102723930A (en) Double-edge D trigger
CN1980062A (en) Circuit reducing FPGA chip power-consumption and method
CN105306022B (en) A kind of asymmetric time-delay mechanism for four phase Handshake Protocol of asynchronous circuit
CN110555269B (en) Top-level clock tree structure of system on chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120711