CN109192239A - The on-chip test circuit and test method of SRAM memory - Google Patents
The on-chip test circuit and test method of SRAM memory Download PDFInfo
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- CN109192239A CN109192239A CN201810829670.2A CN201810829670A CN109192239A CN 109192239 A CN109192239 A CN 109192239A CN 201810829670 A CN201810829670 A CN 201810829670A CN 109192239 A CN109192239 A CN 109192239A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The present invention provides a kind of on-chip test circuit of SRAM memory and test methods, it establishes and retention time measuring circuit, access time measuring circuit, functional test circuit is connected between control circuit and multiplexer circuit, multiplexer circuit connects SRAM memory, and control circuit controls multiplexer circuit；It establishes and retention time measuring circuit and access time measuring circuit includes digit time converter, digit time converter is made of adjustable delay chain, and adjustable delay chain is made of delay unit, and different delays is arranged by adjusting the quantity of delay unit.The present invention combines control circuit, foundation and retention time measuring circuit, access time measuring circuit, functional test circuit, access time, settling time, retention time and the store function of measurement SRAM are realized simultaneously, the testing time is substantially reduced, and improves the precision of measurement.
Description
Technical field
The present invention relates to electronic circuit technology fields, and in particular, to the on-chip test circuit of SRAM memory and test
Method.
Background technique
SRAM (Static Random Access Memory, static random access memory) is usually as the master in piece
The cache between data storage or CPU and main memory is wanted, is one of the main IP module in System on Chip/SoC.In SRAM
In IP design process, do not only need to ensure that the functions meet your requirements of IP, the time sequence parameter of IP interface are also required to guarantee.SRAM IP
Interface signal belong to internal signal, due to drive it is small, speed is high and signal is more, performance and precision can be brought in traditional test
Loss, using test circuit, portion's test can bring test performance and test to the function and timing performance of SRAM IP in the chip
The raising of precision.
In the prior art, access time, settling time, retention time and the function of memory can't be measured simultaneously at present
It can test.With the continuous continuous improvement reduced with working frequency of digital integrated electronic circuit size, the timing ginseng of the port SRAM IP
Number it is smaller and smaller, design on-chip test circuit to SRAM IP tested increasingly it is necessary to.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of on-chip test circuit of SRAM memory and
Test method.
The on-chip test circuit of a kind of SRAM memory provided according to the present invention, comprising: control circuit, foundation and holding
Time measuring circuit, access time measuring circuit, functional test circuit and multiplexer circuit；
The foundation and retention time measuring circuit, the access time measuring circuit, functional test circuit difference
It is connected between the control circuit and the multiplexer circuit, the multiplexer circuit connects SRAM memory, described
Control circuit controls the multiplexer circuit；
The foundation and retention time measuring circuit and the access time measuring circuit include digit time converter,
The digit time converter is made of adjustable delay chain, and the adjustable delay chain is made of delay unit, by adjusting delay
The quantity of unit is arranged different delays.
Preferably, it is described foundation and retention time measuring circuit using digit time converter constantly regulate ADDR signal and
CLK signal arrives separately at the delay relationship of the port ADDR of SRAM memory, the port CLK, believes the ADDR into the port ADDR
It number constantly approaches and to be just met for establishing and the case where retention time constraint, established and the retention time to measure ADDR port
Value.
Preferably, the output for exporting the data output end of SRAM memory is believed in establishing the measurement with the retention time
Number it is set as low level, is stored in high level data, the port CLK and the port ADDR of SRAM memory in SRAM memory preset address
It is respectively connected to digit time converter, makes to establish and the retention time meets the requirements, adjust and reduce CLK signal and ADDR signal
Delay, when the output signal of SRAM memory is there is no overturning, delay at this moment does not meet foundation and the retention time requires,
The delay inequality for calculating adjustable delay chain structure obtains the port ADDR of SRAM memory and foundation and the retention time of the port CLK.
Preferably, the access time measuring circuit inputs SRAM memory significant address signal, digit time is constantly adjusted
Converter enables the output signal of SRAM memory and CLK signal to reach comparison module simultaneously, thus when measuring access
Between.
Preferably, inputting SRAM memory CLK signal in the measurement of access time and significant address signal, SRAM being deposited
If the output signal and CLK signal of reservoir pass through dry circuit respectively reaches digit time converter, digit time converter is adjusted,
Until the output signal of SRAM memory and corresponding CLK signal are just met for the requirement of the settling time of d type flip flop.
Preferably, the functional test circuit includes address-generation unit, comparison module and built-in self-test control circuit
Composition, wherein built-in self-test control circuit uses March C algorithm, and control address-generation unit generates address, and carries out
The read-write of SRAM memory, control comparison module reads the data of SRAM memory automatically, and is compared with the data of write-in,
To obtain the correctness of SRAM memory read-write capability.
Preferably, the delay unit includes big delay unit and small delay unit, it is single that each delay is obtained by fitting
The size of the delay time of member.
Preferably, combining the signal of two adjustable delay chains by conversion circuit only has rising/rising.
Preferably, being connected separately with controllable inverter in the port CLK of SRAM memory and data output end.
The on-chip testing method of a kind of SRAM memory provided according to the present invention, comprising: establish and the retention time measures
Submethod, access time measure at least one of submethod or functional test submethod；
The foundation and retention time measure submethod and constantly regulate ADDR signal and CLK letter using digit time converter
Number the port ADDR of SRAM memory, the delay relationship of the port CLK are arrived separately at, keeps the ADDR signal into the port ADDR continuous
The case where being just met for establishing with retention time constraint is approached, to measure the value of the port ADDR foundation and retention time；
The access time measurement submethod inputs SRAM memory significant address signal, constantly adjusts digit time conversion
Device enables the output signal of SRAM memory and CLK signal to reach comparison module simultaneously, to measure access time；
The functional test submethod is generated by using the built-in self-test control circuit control address of March C algorithm
Unit generates address, and carries out the read-write of SRAM memory, and control comparison module reads the data of SRAM memory automatically, and with
The data of write-in are compared, to obtain the correctness of SRAM memory read-write capability.
Compared with prior art, the present invention have it is following the utility model has the advantages that
The present invention is by control circuit, foundation and retention time measuring circuit, access time measuring circuit, functional test circuit
In conjunction with, while realizing access time, settling time, retention time and the store function of measurement SRAM, when substantially reducing test
Between, and improve the precision of measurement.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is module diagram of the invention；
Fig. 2 is to establish and retention time measuring principle schematic diagram；
Fig. 3 is to establish and retention time instrumentation plan；
Fig. 4 is access time to measure time diagram；
Fig. 5 is instrumentation plan between access；
Fig. 6 is to establish and the switching path schematic diagram in retention time measurement；
Fig. 7 is the switching path schematic diagram in access time measurement
Fig. 8 is the structural schematic diagram for calibrating circuit；
Fig. 9 is the structural schematic diagram of functional test circuit；
Figure 10 is to establish to measure time diagram with the retention time；
Figure 11 is the structural schematic diagram of time delay chain；
Figure 12 is the connecting structure from beginning to end schematic diagram of time delay chain；
Figure 13 is the structural schematic diagram of multi-selection device.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
As shown in Figure 1, a kind of on-chip test circuit of SRAM memory provided by the invention, comprising: control circuit, foundation
With retention time measuring circuit, access time measuring circuit, functional test circuit and multiplexer circuit.When establishing and keeping
Between measuring circuit, access time measuring circuit, functional test circuit be connected between control circuit and multiplexer circuit,
Multiplexer circuit connects SRAM memory, and control circuit controls multiplexer circuit.
Establishing with retention time measuring circuit and access time measuring circuit includes digit time converter (Digital
To Time Converter, DTC), digit time converter is made of adjustable delay chain, and adjustable delay chain is by delay unit structure
At being arranged different delays by adjusting the quantity of delay unit.
It establishes and retention time measuring circuit:
SRAM memory settling time is that can guarantee to be written efficiently into and read data, and signal relative time clock edge must be protected in advance
Best time available is held, the retention time is clock after, and input signal must keep best time available, establish and protect
The measuring principle for holding the time is as shown in Fig. 2.
As shown in figure 3, constantly regulate ADDR signal using digit time converter and CLK signal arrives separately at SRAM and stores
The delay relationship of the port ADDR of device, the port CLK, make the ADDR signal into the port ADDR constantly approach be just met for establishing and
The case where retention time constrains, to measure the value of the port ADDR foundation and retention time.Establishing the measurement with the retention time
In, the output signal that the data output end of SRAM memory exports is set as low level, is stored in SRAM memory preset address
High level data, the port CLK and the port ADDR of SRAM memory are respectively connected to digit time converter, when making to establish and keep
Between meet the requirements, the delay of CLK signal and ADDR signal is adjusted and reduces, when there is no turning over for the output signal of SRAM memory
Turn, delay at this moment does not meet foundation and the retention time requires, and the delay inequality for calculating adjustable delay chain structure obtains SRAM storage
The port ADDR of device and foundation and the retention time of the port CLK.
Access time measuring circuit: being exactly when carrying out read operation to SRAM memory, on CLK rising edge and the end output end Q
Rise the time interval of edge or failing edge.Measuring principle figure is as shown in Fig. 4.SRAM memory significant address signal is inputted, constantly
Digit time converter is adjusted, enables the output signal of SRAM memory and CLK signal to reach comparison module simultaneously, to measure
Access time out.It is as shown in Fig. 5 to measure timing diagram.In the measurement of access time, inputs SRAM memory CLK signal and have
Address signal is imitated, if the output signal of SRAM memory and CLK signal pass through dry circuit respectively and reach digit time converter, is adjusted
Integer word time converter, until the output signal of SRAM memory and corresponding CLK signal are just met for the foundation of d type flip flop
The requirement of time.
Calibration method:
It establishes and main source of error that retention time and access time measure is in, the constant time lag difference of time delay chain, and
By temperature/technique/voltage influence error.Since in design and actual circuit, there is fixed delay in DTC delay unit
Difference, for the constant time lag difference of time delay chain, using the method for path exchanging, as seen in figs. 6 and 7.Measuring an address
When the foundation of line and retention time, delay chain survey can be exchanged twice, then be averaged, eliminated asymmetric above two one time delay chains
Error.In measurement between at the time of reading, delay circuit is exchanged, then is measured once, measurement result is averaged twice, to disappear
Except the error and other errors of d type flip flop settling time.
Delay unit is originally experienced temperature/technique/voltage influence generation error, by fitting prolonging for each delay cell
The size of slow time.As shown in Fig. 8, by controlling the input of oscillator, oscillator is made to generate the clock signal of different cycles.
Oscillator two output signals STEP1 and STEP2 differ a clock cycle, by constantly adjusting the size of DTC, to measure
One clock cycle corresponding how many a delay cells.It is located in DTC, big buffer delay is Tbsel, the delay of small buffer
For Tlsel, it is to meet following relationship that the settling time of d type flip flop, which is the clock cycle after 128 times of surveyed frequency dividings:
For tsetupClock cycle after the 128 times of frequency dividings surveyed is T, meets following relationship:
Wherein, m is the number of big buffer in time delay chain, and n is the number of small buffer, and T is the concussion period surveyed, and is led to
The adjustment concussion period is spent, the different data group of several groups (m, n, T) is obtained, by polynary least-squares linear regression, is used
Matlab fits parameters survey.To obtain the delay T of the big buffer under special processbselWith the delay of small buffer
Tlsel, it is used for subsequent measurement.
Functional test circuit: functional test circuit includes address-generation unit, comparison module and built-in self-test control electricity
Road composition, as shown in figure 9, wherein built-in self-test control circuit uses March C algorithm, control address-generation unit generates ground
Location, and the read-write of SRAM memory is carried out, control comparison module reads the data of SRAM memory, and the data with write-in automatically
It is compared, to obtain the correctness of SRAM memory read-write capability.
Since PMOS with NMOS performance is different in cmos device, rising edge and failing edge are by time delay chain and mutually powered-down
Lu Shihui generates different delays, the aborning signal combination of two one time delay chains are as follows: rising/rising, rise/fall, decline/on
It rises, decline/decline, greatly increases the complexity of test circuit.By conversion circuit in the present invention, make the signal group in time delay chain
It closes and there was only rising/rising, and optimize the design of time delay chain in this case, so that measurement accuracy is higher.
In the measurement of access time, different prolong is generated in order to eliminate rising edge and failing edge in subsequent measuring circuit
When error, connect controllable inverter respectively with data output end Q at the end CLK of SRAM memory.Due to the signal one at the end CLK
It is directly rising edge, so the inverter controlling end ground connection that the end CLK is connect, then the controllable inverter is just without negative function.?
The data output end Q of SRAM, when output data is rising edge, the control terminal ground connection of connect controllable inverter；Work as output data
When for failing edge, the control of the phase inverter connect terminates VDD, and failing edge is converted into rising edge, exists to eliminate different edges
The different error that is delayed in measuring circuit.
Assuming that the true value of read access time is T, the settling time of register is Tsetup.When the data of SRAM memory export
End is linked to the end D of register by the delay of upper end, and the clock signal terminal of SRAM is linked to register by lower end delay
When clock signal terminal, measured value T1, because to meet the settling time of register, the end the D rising edge of register needs to compare CLK
End rising edge shifts to an earlier date Tsetup, so meeting following relationship:
T1=T-Tsetup
After exchanging time delay chain, SRAM data output end is linked to the clock signal terminal of register by the delay of lower end,
The clock signal terminal of SRAM is linked to the end D of register by upper end delay, and measured value is T at this time2.In order to meet register
Settling time requires, and the rising edge at the end CLK of register needs at least more late than the end D rising edge to Tsetup, therefore meet following relationship
Formula
T2=T+Tsetup
It measurement result will be averaged, obtain twice:
So error can be eliminated by exchange time delay chain.
For time delay chain as the key component for quantifying time delay interval in DTC circuit, precision and the linearity affect entire survey
Measure the accuracy of result.Simplest time delay chain can be realized by chain of inverters, and as unit of two phase inverters, propagation delay is made
For unit delay, signal is picked out after each section phase inverter unit, as the input terminal of multistage mux, controls signal control
Mux, the signal after a certain section phase inverter unit of final output, as shown in Fig. 10.In the circuit not high to required precision, make
With such time delay chain.But in such time delay chain, in addition to the delay time error between delay unit itself, signal is never
It is drawn after same delay unit, is output to output port via the different path mux, the delay that will introduce mux difference path misses
Difference.And in the higher circuit of required precision, the error in mux difference path will bring the influence that can not ignore.Therefore, have in fact
Necessity proposes a kind of technological means, to effectively improve the linearity of time delay chain, reduces error.
In order to overcome the deficiencies of the above existing technologies, the present invention proposes a kind of delay chain structure of high linearity, reduces
Influence of the other parts to circuit delay in circuit, to improve measurement accuracy.As shown in figure 11, high linearity prolongs in the present invention
When chain include: decoder module (Decoder) and time delay chain module (Delayline).The major function of decoder module be by
The control signal of external circuit is decoded.It is exactly the position the n control signal from external circuit that it, which is inputted, and specific digit depends on
The range of time delay chain required for circuit.It is that 2n-1 root controls signal that it, which is exported, is connected in time delay chain module, respectively control delay
The selection path of each delay unit in chain module.The major function of time delay chain module is to give input signal a certain amount of delay
Amount.Analog signal with time delays amount is the input of its time delay chain port, and the control signal of decoder is also time delay chain mould
The EN signal of the multi-selection device of each delay unit in block.It is the analog signal with specific amount of delay that it, which is exported, to reference
The output signal of time delay chain compares, to obtain prolonging between measured signal and reference signal according to specific delay unit quantity
The time difference.Time delay chain module is the time delay chain formed by 2n-1 delay unit (Buffer Unit, BU) series connection, and each delay is single
Member receives the decoded signal (EN) from decoder to selection path.The head and the tail of time delay chain module are respectively connected to one
Buffer provides driving identical with other delay units for first to circuit and the last one delay unit and bears
It carries, reduces error.
Delay unit is made of two Buffer and one multi-selection device with enable signal, and input signal is divided into two-way,
It is directly connected to an input port of multi-selection device all the way, another way is connected to an input of multi-selection device by level-one buffer
Port；Multi-selection device receives the enable signal from decoder, and one is selected in two accesses of mux according to the value of EN signal；
The output end of multi-selection device meets level-one buffer again, is the output of delay unit.Wherein Buffer is that two-stage inverter series form.
The present invention is decoded, mux in each delay unit on control time delay chain by changing n bit word by decoder
Gating path measured signal is passed through into the output signal and reference signal that time delay chain obtains to adjust the delay of time delay chain
It is compared, to obtain the temporal information of measured signal.Such gating path makes the linearity of time delay chain higher.
In order to measure the delay of measured signal, two sets delay chain structures are selected, measured signal is from a set of chain structure that is delayed
The input of the end IN, IN end input of the reference signal as another set of delay chain structure.The reference time delay determination of estimation measured signal is prolonged
When chain survey range, determine the quantity of delay unit in conjunction with the amount of delay of delay unit, determine the code word digit of coding.With five
For bit word, it can control 32 delay units.Control coding is passed into decoder by the control unit of external circuit, from
And the access selection of delay unit in time delay chain is controlled, each delay unit receives the control signal from decoder, is led to
Road selection.If controlling signal is 0, the access without buffer is selected, is followed by by multi-selection device onto a buffer, delay is single
Member is the amount of delay of a buffer；If controlling signal is 1, selection has the access of buffer, is followed by by multi-selection device to one
A buffer and then the amount of delay for adjusting time delay chain, delay unit are the amount of delay of two buffer.It is selected by access
Adjust the amount of delay of delay link.
When measurement, the code word of a link wherein link where the link and measured signal where reference signal can be consolidated
It is fixed, by adjusting the delay of both links, obtain when the output signal of both links while when overturning, the amount of delay for the link that is delayed
Difference, the as delay inequality between measured signal and reference signal.
By taking measured signal code word is fixed as 00000 (five-bit code word) as an example, delay unit control signals all at this time is equal
It is 0, all delay units all select the access without buffer, and the quantity of delay unit is the buffer of first-in-chain(FIC) of being delayed, and 32
The buffer that delay unit respectively includes, and the buffer, totally 34 buffer of delay last-of-chain.Adjust the code of reference signal
Word shows the delay of time delay chain at this time if the output signal of the output signal ratio of reference link link to be measured is first overturn at this time
Amount is also not up to the amount of delay of measured signal, needs to tune up the code word of reference signal；If the output signal of link to be measured at this time
Output signal than reference link is first overturn, and shows that the amount of delay of time delay chain at this time alreadys exceed the delay of measured signal
Amount, needs to turn down the code word of reference signal.When both links output signal simultaneously overturn or two neighboring code word one
It is bigger than normal one it is less than normal when, that is, reach critical point, at this time both links delay link amount of delay difference, as measured signal with
Delay inequality between reference signal.
As it can be seen that the head and the tail of time delay chain are all connected to a buffer unit in attached drawing 12, the drive of visible multi-selection device in attached drawing 13
Dynamic and load is buffer unit, and such circuit structure design effectively balances driving and load is prolonged to device in circuit
When bring influence.
The on-chip testing method of a kind of SRAM memory provided according to the present invention, comprising: establish and the retention time measures
Submethod, access time measure at least one of submethod or functional test submethod；
It establishes and retention time measurement submethod constantly regulate ADDR signal using digit time converter and CLK signal divides
It is clipped to the delay relationship of the port ADDR, the port CLK that reach SRAM memory, approaches the ADDR signal into the port ADDR constantly
It is just met for the case where establishing with retention time constraint, to measure the value of the port ADDR foundation and retention time；
Access time measures submethod and inputs SRAM memory significant address signal, constantly adjusts digit time converter, makes
The output signal and CLK signal for obtaining SRAM memory can reach comparison module simultaneously, to measure access time；
Functional test submethod controls address-generation unit by using the built-in self-test control circuit of March C algorithm
Generate address, and carry out the read-write of SRAM memory, control comparison module reads the data of SRAM memory automatically, and with write-in
Data be compared, to obtain the correctness of SRAM memory read-write capability.
One skilled in the art will appreciate that in addition to realizing system provided by the invention in a manner of pure computer readable program code
It, completely can be by the way that method and step be carried out programming in logic come so that this hair and its other than each device, module, unit, circuit
The system of bright offer and its each device, module, unit are with logic gate, switch, specific integrated circuit, programmable logic controller (PLC)
And the form of embedded microcontroller etc. realizes identical function.So system provided by the invention and its every device, mould
Block, unit are considered a kind of hardware component, and to including for realizing the device of various functions, module, list in it
Member can also be considered as the structure in hardware component；Both can also may be used being considered as realizing the device of various functions, module, unit
To be that the software module of implementation method can be the structure in hardware component again.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. a kind of on-chip test circuit of SRAM memory characterized by comprising control circuit, foundation and retention time survey
Measure circuit, access time measuring circuit, functional test circuit and multiplexer circuit；
The foundation and retention time measuring circuit, the access time measuring circuit, the functional test circuit are separately connected
Between the control circuit and the multiplexer circuit, the multiplexer circuit connects SRAM memory, the control
Multiplexer circuit described in circuit control；
The foundation and retention time measuring circuit and the access time measuring circuit include digit time converter, described
Digit time converter is made of adjustable delay chain, and the adjustable delay chain is made of delay unit, by adjusting delay unit
Quantity different delays is set.
2. the on-chip test circuit of SRAM memory according to claim 1, which is characterized in that when the foundation and holding
Between measuring circuit constantly regulate ADDR signal using digit time converter and CLK signal arrives separately at the ADDR of SRAM memory
The delay relationship of port, the port CLK approaches the ADDR signal into the port ADDR constantly and is just met for foundation and retention time
The case where constraint, to measure the value of the port ADDR foundation and retention time.
3. the on-chip test circuit of SRAM memory according to claim 2, which is characterized in that in foundation and retention time
Measurement in, the output signal that the data output end of SRAM memory exports is set as low level, on the default ground of SRAM memory
Location is stored in high level data, and the port CLK and the port ADDR of SRAM memory be respectively connected to digit time converter, make to establish and
Retention time meets the requirements, and adjusts and reduce the delay of CLK signal and ADDR signal, when the output signal of SRAM memory does not have
It is flipped, delay at this moment does not meet foundation and the retention time requires, and the delay inequality for calculating adjustable delay chain structure obtains
The port ADDR of SRAM memory and foundation and the retention time of the port CLK.
4. the on-chip test circuit of SRAM memory according to claim 1, which is characterized in that the access time measurement
Circuit inputs SRAM memory significant address signal, digit time converter is constantly adjusted, so that the output signal of SRAM memory
Comparison module can be reached simultaneously with CLK signal, to measure access time.
5. the on-chip test circuit of SRAM memory according to claim 4, which is characterized in that in the measurement of access time
In, it inputs SRAM memory CLK signal and significant address signal, the output signal and CLK signal of SRAM memory is passed through respectively
If dry circuit reaches digit time converter, digit time converter is adjusted, until the output signal of SRAM memory and corresponding
CLK signal be just met for d type flip flop settling time requirement.
6. the on-chip test circuit of SRAM memory according to claim 1, which is characterized in that the functional test circuit
It is formed including address-generation unit, comparison module and built-in self-test control circuit, wherein built-in self-test control circuit uses
March C algorithm controls address-generation unit and generates address, and carries out the read-write of SRAM memory, and control comparison module is read automatically
The data of SRAM memory are taken, and are compared with the data of write-in, to obtain the correctness of SRAM memory read-write capability.
7. the on-chip test circuit of SRAM memory according to claim 1, which is characterized in that the delay unit includes
Big delay unit and small delay unit obtain the size of the delay time of each delay cell by being fitted.
8. the on-chip test circuit of SRAM memory according to claim 1, which is characterized in that make two by conversion circuit
The signal combination of adjustable delay chain described in item only has rising/rising.
9. the on-chip test circuit of SRAM memory according to claim 1, which is characterized in that in SRAM memory
The port CLK and data output end are connected separately with controllable inverter.
10. a kind of on-chip testing method of SRAM memory characterized by comprising establish and the retention time measurement submethod,
Access time measures at least one of submethod or functional test submethod；
The foundation and retention time measure submethod and constantly regulate ADDR signal and CLK signal point using digit time converter
It is clipped to the delay relationship of the port ADDR, the port CLK that reach SRAM memory, approaches the ADDR signal into the port ADDR constantly
It is just met for the case where establishing with retention time constraint, to measure the value of the port ADDR foundation and retention time；
The access time measurement submethod inputs SRAM memory significant address signal, constantly adjusts digit time converter, makes
The output signal and CLK signal for obtaining SRAM memory can reach comparison module simultaneously, to measure access time；
The functional test submethod controls address-generation unit by using the built-in self-test control circuit of March C algorithm
Generate address, and carry out the read-write of SRAM memory, control comparison module reads the data of SRAM memory automatically, and with write-in
Data be compared, to obtain the correctness of SRAM memory read-write capability.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111210865A (en) * | 2020-04-20 | 2020-05-29 | 南京邮电大学 | On-chip measuring circuit and measuring method for low-voltage SRAM time parameter |
| WO2021238829A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Timing unit establishing time measuring method and measuring circuit |
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