CN1235286C - 一种电子装置与制作此装置的方法 - Google Patents

一种电子装置与制作此装置的方法 Download PDF

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Publication number
CN1235286C
CN1235286C CNB011253703A CN01125370A CN1235286C CN 1235286 C CN1235286 C CN 1235286C CN B011253703 A CNB011253703 A CN B011253703A CN 01125370 A CN01125370 A CN 01125370A CN 1235286 C CN1235286 C CN 1235286C
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terminal block
semiconductor chip
projection
type surface
electrode tip
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Expired - Fee Related
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CNB011253703A
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CN1340857A (zh
Inventor
今须诚士
吉田育生
岸川笵夫
角义之
田口一之
内藤孝洋
佐藤俊彦
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Renesas Electronics Corp
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Hitachi Ltd
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Abstract

一种电子装置包括：一个在它的一个主表面上有许多电极座的半导体芯片；一块在它的一个主表面上有许多连接部分的接线板；与许多分别布置在半导体芯片的各电极座与连线板的各连接部分之间以提供二者之间电连接的凸起电极，这些凸起电极布置成一个使半导体芯片相对于接线板的一个主表面不平衡的阵列，接线板的许多连接部分布置在向从接线板的一个主表面的深度方向比这个主表面较深的位置上。

Description

一种电子装置与制作此装置 的方法
技术领域
本发明涉及一种电子装置与制作此装置的方法。尤其是，本发明涉及一种可有效地适用于采用倒装芯片装配(安装)技术的电子装置的技术。
背景技术
关于电子装置已知一种称为MCM(多芯片模块)的电子装置。在一个MCM中，每个包括一个集成电路的许多半导体芯片装配在一块接线板上以完成一个综合的功能。关于MCM，采用倒装芯片装配技术变为越来越流行，在此技术中，一个带有形成在电路形成表面的电极座(electrode pad)上的凸起电极的半导体芯片(倒装芯片)装配在接线板上。这是为了提高数据传输速度与减小装置尺寸。
关于倒装芯片装配技术，已提出各种装配方法并投入实际应用。例如，称为CCB(可控崩塌粘结)与ACF(各向异性传导膜)的装配方法已被实际采用。
在CCB法中，形成例如球形的焊料凸块作为半导体芯片的电极座上的凸块电极(凸起电极)，然后把此半导体芯片放置在接线板上，之后进行熔化焊料凸块的热处理以便在电气上与机械上连接作为接成板上接线部分的连接部分与半导体芯片的电极座。
在ACF装配法中，形成例如金(Au)的纽扣凸块(stud bump)作为半导体芯片的电极座上的凸块电极(凸起电极)，然后通过一个片状的各向异性的传导树脂(ACF)作为粘结树脂把半导体芯片放置在接线板上，之后在加热状态下把半导体芯片压粘在接线板上从而使纽扣凸块同接线板上的连接部分电气连接。各向异性的传导树脂包含一种绝缘树脂与大量散布并混合在其中的传导颗粒。
经研究上述倒装芯片装配技术，本发明发现下列问题。
(1)关于半导体芯片的座阵列。有各种类型的阵列。它们之中包括一种中央座阵列，在此阵列中许多电极座布置成沿中心区域的一行，此行沿半导体芯片的电路形成表面的X或Y方向的中心线延伸。这种中央座阵列用于例如其中包括一个DRAM(动态随机存取存贮器)作为一个存贮电路的半导体芯片。
例如在一个DRAM的情况下，有下列关于电极座(粘结座)布置的要求。为减小接线电感电极座应布置在输入/输出电路的附近。而且，为防止在粘结过程损坏装置，不应正好在电极座下构成半导体器件。此外，为了改进运行速度的目的，从输入/输出电路至存贮器垫板(memory mat)内的最远部分的距离做得尽可能短。满足这些要求导致如图21中所示的这样一个关于DRAM芯片的布局，在此布局中电极座沿芯片的长边方向布置在中央。在图21中，标记号30表示DRAM芯片，MARY表示存贮器阵列，PC表示周边电路，I/O表示输入/输出电路，而BP表示电极座。
在中央座阵列情况下，分别形成在电极座上的凸块电极阵列也是中央凸块阵列。如果在倒装芯片装配中使用这种半导体芯片，得到芯片的平衡是不可能的，从而使芯片相对于接线板的一个主表面发生倾斜。因此，在半导体芯片有中央座阵列的情况下，实现倒装芯片装配是困难的。关于半导体芯片不良好平衡的座阵列(凸块阵列)的例子，除了中央座阵列以外，还有一边座阵列(一边凸块阵列)，在此阵列中许多电极座布置成沿芯片的两条对边之一的一行。
(2)在ACF装配法中，利用***在按线板与半导体芯片之间的各向异性的传导树脂的热收缩力(因从加热状态返回至正常状态而产生的收缩力)或热固化收缩力(因热固树脂的固化而产生的收缩力)把纽扣凸块压粘在接线板的连接部分上。另一方面，由于各向异性传导树脂的热膨胀系数通常大于纽扣凸块的热膨胀系数，各向异性传导树脂向厚度方向的膨胀量大于纽扣凸块向高度方向的膨胀量。因而，可能出现低劣的连接使得纽扣凸块由于热的影响而脱离接线板的连接部分。因此，必须把接线板与半导体芯片之间的各向异性传导树脂的体积做成尽可能小。
在此连接中，一个用于减小接线板与半导体芯片之间的各向异性传导树脂体积的技术公开在例如日本出版的未经审查的专利申请No.Hei10(1998)-270496(USP6208525)中。根据此未经审查公开中的技术，如其图12中所示，“在一块坚硬的接线板19内形成一个槽19A，在槽19A内形成电极座4A，而电极座4A同凸块电极15在槽19内连接在一起。根据此构造，接线板19与半导体芯片10之间的间隙同接线板19与电极座上没有顶部绝缘层因而暴露顶部接线层的情况相比变窄一个相当于槽19A深度的量，从而可减少***在接线板19与半导体芯片10之间的粘结剂(各向异性传导树脂)16的厚度。”
然而，根据上述构造，其中在接线板内形成一个槽，接线板上的电极座(连接部分)与凸块电极(纽扣凸块)在槽内连接在一起，由此产生一个新问题。
在半导体芯片上电极座情况下，平面尺寸与电极座的阵列间距(座阵列间距)有关，座阵列间距越窄，平面尺寸越小。如果由于电极座平面尺寸的这个减小而使用较细的金线来形成较小直径的纽扣凸块，每个纽扣凸块的高度也相应地变为较小。即是说，如果座阵列间距不同，则纽扣凸块的高度也不同。
另一方面，在某些电子装置例如MCM中，在单块接线板上装配在集成程度与功能方面不同的几种类型半导体芯片，而这些半导体芯片在座阵列阵间距方面不总是相等的。由于不同的座阵列间距，而有不同的纽扣凸块高度。因此在其中纽扣凸块高度大于从接线板的一个主表面至它的连接部分的深度的半导体芯片情况下，可容易地实现接线板连接部分同纽扣凸块之间的连接，而在其中纽扣凸块高度小于从接线板的一个主表面至它的连接部分的深度的半导体芯片情况下，实现接线板连接部分同纽扣凸块之间的连接是困难的。
如果调节接线板连接部分的深度位置以匹配被装配在接线板上的半导体芯片中有最小纽扣凸块高度的半导体芯片，这时即使是有最小的纽扣凸块高度的半导体芯片，也可连接纽扣凸块与接线板的连接部分。然而，在此情况下，对有大的纽扣凸块高度的半导体芯片，***在半导体芯片与接线板之间的各向异性传导树脂的体积变大，从而可能产生一个低劣的连接使得在热影响下纽扣凸块脱离接线板的连接部分。
发明内容
本发明的一个目的是提供一种能抑制半导体芯片相对于接线板的一个主表面倾斜的技术。
本发明的另一个目的是提供一种容许在座阵列间距方面不同的几种类型半导体芯片装配在单块接线板上的技术。
根据下面的描述与各附图，本发明的上述与其它目的及新颖的特点将变为显而易见。
下面将给出关于本申请中公开的典型发明的简要说明。
(1)一种根据本发明的电子装置包括：
一个在它的一个主表面上有许多电极座的半导体芯片；
一个在它的一个主表面上有许多连接部分的接线板；与
许多在半导体芯片的各电极座与接线板的各连接部分之间布置成行的凸起电极，
接线板的连接部分布置在向从接线板的一个主表面的深度方向比这一个主表面较深的位置上。
接线板还包括一个形成在它的一个主表面上的绝缘膜，一个形成在此绝缘膜中的孔，与布置在此孔底部的许多连接部分。
绝缘膜呈现为跨置在半导体芯片的周边上。
孔的平面尺寸小于半导体芯片的平面尺寸，而绝缘膜的平面尺寸大于半导体芯片的平面尺寸。
根据上述装置(1)，在倒装芯片装配半导体芯片时，凸起电极的高度被从接线板的一个主表面至连接部分的深度包容，使得能抑制半导体芯片相对于接线板的一个主表面的倾斜。
(2)一种根据本发明的电子装置包括：
一个有许多按第一座阵列间距布置在它的一个主表面上的第一电极座的第一半导体芯片；
一个有许多按小于第一座阵列间距的第二座阵列间距布置在它的一个主表面上的第二电极座的第二半导体芯片；
一块在它的一个主表面的第一区域内有许多对应于第一电极座布置的第一连接部分与在不同于一个主表面的第一区域的第二区域内也有许多对应于第二电极座布置的第二连接部分的接线板；
许多每个布置在每个第一电极座与每个第一连接部分之间以提供二者之间电连接的第一凸起电极；与
许多每个布置在每个第二电极座与每个第二连接部分之间以提供二者之间电连接的第二凸起电极，
许多第一连接部分与许多第二连接部分布置在向从接线板的一个主表面的深度方向比这一个主表面较深的位置上，且
许多第二凸起电极有一个其级数多于第一凸起电极的多级凸块结构。
接线板还包括一个形成在它的一个主表面上的绝缘膜，一个形成在这一个主表面的第一区域内的绝缘膜中的第一孔，与一个形成在这一个主表面的第二区域内的绝缘膜中的第二孔，在第一孔的底部布置许多第一连接部分而在第二孔的底部布置许多第二连接部分。
第二凸起电极有一个多级凸块结构，此结构有一个连接第二半导体芯片的第二电极座的基底凸起与一个堆叠在基底凸起上的堆叠凸起。
第二凸起电极有一个多级凸块结构，此结构有一个连接第二半导体芯片的第二电极座的基底凸块，一个堆叠在基底凸块上的第一堆叠凸块，与一个堆叠在第一堆叠凸块上的第二堆叠凸块。
根据上述装置(2)，在倒装安装第一与第二半导体芯片时，第二半导体芯片中的凸起电极也可同接线板的连接部分连接，使得座阵列间距不同的第一与第二半导体芯片可装配在单块接线板上。
附图说明
图1是一个根据本发明第一实施例的一个MCM(一种电子装置)的示意平面图；
图2是一个图1中表示的MCM的示意底视图；
图3是一个表示包括在图1中表示的MCM中的一个缓冲器芯片的装配状态的示意剖视图；
图4是一个表示包括在图1中表示的MCM中的一个存贮器芯片的装配状态的示意剖视图；
图5是一个表示包括在图1中表示的MCM中的一个控制器芯片的装配状态的示意剖视图；
图6是一个表示包括在图1中表示的MCM中的一个电容器的装配状态的示意剖视图；
图7是一组局部表示包括在图1中表示的MCM中的一个缓冲器芯片、一个存贮器芯片与一个控制器芯片的座阵列的示意平面图；
图8是一组表示包括在图1中表示的MCM中的一个缓冲器芯片、一个存贮器芯片与一个控制器芯片的构造的示意剖视图；
图9是一个表示包括在图1中表示的MCM中的存贮器芯片的构造的示意平面图；
图10是一个表示用于图1中表示的MCM的一块接线板的一部分的示意剖视图；
图11是一组用于说明在根据第一实施例制作MCM时在存贮器芯片中的一个电极座上形成一个纽扣凸块过程的示意剖视图；
图12是一个用于说明在根据第一实施例制作MCM中缓冲器芯片装配过程的示意剖视图；
图13是一个用于说明在根据第一实施例制作MCM中缓冲器芯片装配过程的示意剖视图；
图14是一个用于说明在根据第一实施例制作MCM中存贮器芯片装配过程示意剖视图；
图15是一个用于说明在根据第一实施例制作MCM中存贮器芯片装配过程的示意剖视图；
图16是一组表示根据第一实施例的MCM中另外的凸块阵列模式的存贮器芯片的示意平面图；
图17是一个表示包括在根据第一实施例的第一修改方案的MCM中的一个存贮器芯片的装配状态的示意剖视图；
图18是一个表示包括在根据第一实施例的第二修改方案的MCM中的一个存贮器芯片的装配状态的示意剖视图；
图19是一个表示包括在根据第二实施例的MCM中的一个存贮器芯片的示意剖视图；
图20是一个图19的局部放大示意剖视图；与
图21是一个常规的DRAM芯片的平面布局图。
具体实施方式
下面将参照各附图详细描述本发明的各实施例。在所有用于说明各实施例的附图中，具有相同功能的部分用相同的标记号标识从而将省略对它们的重复说明。
图1是一个根据本发明第一实施例的一个MCM(一种电子装置)的示意平面图，图2是一个此MCM的底视图，而图3是一个表示包括在图1的MCM中的一个缓冲器芯片的装配状态的示意剖视图，图4是一个表示包括在图1的MCM中的一个存贮器芯片的装配状态的示意剖视图，图5是一个表示包括在图1的MCM中的一个控制器芯片的装配状态的示意剖视图，图6是一个表示包括在图1的MCM中的一个电容器的装配状态的示意剖视图，图7是一组局部表示包括在图1的MCM中的一个缓冲器芯片、一个存贮器芯片与一个控制器芯片的座布置的示意平面图，图8是一组表示包括在图1的MCM中的一个缓冲器芯片、一个存贮器芯片与一个控制器芯片的构造的示意剖视图，而图9是一个表示包括在图1的MCM的存贮器芯片的示意剖面图。
如图1与图2中表示，根据本实施例的MCM(电子装置)1的构造，许多有源部件与许多无源部件作为电子部件装配在接线板2的一个主表面2X上，而许多球状焊料凸块22作为外部连接端子布置在接线板2的同此主表面相对的背面(另一个主表面)2Y上。关于有源部件，使用许多每个包括一个缓冲电路的半导体芯片(以后称为“缓冲器芯片”)10，许多每个包括存贮电路(例如SDRAM)的半导体芯片(以后称为“存贮器芯片”)12，一个包括控制电路的半导体芯片(以后称为“控制器芯片”)14，与一个包括NAND电路的半导体芯片(以后称为“运算器芯片”)16。这些有源部件按照倒装芯片装配技术装配在接线板2的一个主表面2X上。关于无源部件，使用许多都是表面安装型的电容器17、18与电阻器19。这些无源部件按照回流焊法装配在接线板2的一个主表面2X上。
如图3至图6表示，接线板2有一个坚硬的衬底3，一个通过装配法形成在此坚硬衬底3上的软层4，与一个形成在此软层4上的绝缘膜9。坚硬衬底3与软层4有一个多层互连结构，虽然它们的细节未表示。坚硬衬底3内的各绝缘层由包括浸透环氧或聚酰亚胺树脂的玻璃纤维的高弹性树脂板构成，而软层4内的各绝缘层由例如低弹性的环氧树脂构成。此外，在坚硬衬底3与软层4内的接线层由金属膜例如铜(Cu)膜构成。绝缘膜9由例如聚酰亚胺树脂构成。绝缘膜9控制在装配焊接部件期间焊接部件(本实施例中的17、18与19)的湿润和焊料散布，并保证在装配芯片部件期间粘结树脂对倒装芯片(本实施例的10，12和14)部件的粘结力。
缓冲器芯片10、存贮器芯片12、控制器芯片14与运算器芯片16形成平面内的一个正方形或矩形。在本实施例中，缓冲器芯片10与存贮器芯片12每个形成一个矩形，而控制器芯片14与运算器芯片16每个形成一个正方形。
缓冲器芯片10、存贮器芯片12、控制器芯片14与运算器芯片16每个主要包括一个半导体衬底，一个包括绝缘层与在半导体衬底的电路形成表面上堆叠成多级的接线层的多层互连结构，与一个为覆盖多层互连结构而形成的表面保护层(最后保护)。例如，半导体衬底由单晶硅构成，绝缘层由氧化硅膜构成，而互连结构由金属膜例如铝(Al)或铝合金膜构成，存贮器芯片12的表面保护膜使用例如能改进存贮器中抗α射线强度的聚酰亚胺树脂构成。缓冲器芯片10、控制器芯片14与运算器芯片16的表面保护膜每个由一个绝缘膜例如氧化硅或氮化硅膜或一个有机的绝缘膜构成。关于运算器芯片16，由于它的构造与缓冲器芯片10基本相同，因此将省略对它的进一步说明。
在每个缓冲器芯片10、存贮器芯片12与控制器芯片14中，许多电极座(10a，12a，14a)形成在一个电路形成表面(10X，12X，14X)上，此电路形成表面是一个主表面与同它彼此相对的另一个主表面之中的一个主表面，如图3和7中所示。每种芯片的电极座(10a，12a与14a)形成在每种芯片的多层互连结构中的顶部接线层上并通过形成在每种芯片的表面保护膜中的接合孔暴露在外。
如图7(a)中表示，每个缓冲器芯片10的电极座10a沿缓冲器芯片的电路形成表面10X的四边布置。如图7(b)中表示，每个存贮器12的电极座12b沿中心区域布置，沿存贮器芯片12的电路形成表面12X的两条互相交叉的分别指向长(X)方向与短(Y)方向的中心线的一条长边中心线延伸。如图7(c)中表示，控制器芯片14的电极座14b沿控制器芯片的电路形成表面14X的四边布置。因此，每个缓冲器芯片10与控制器芯片14的电极座布置成四边座阵列，而存贮器芯片12的电极座12a布置成中央座阵列。
如图8(a)表示，一个纽扣凸块11由例如金(Au)形成在每个缓冲器芯片10的每个电极座10a上作为一个凸起电极。如图8(b)表示，一个纽扣凸块13由例如Au形成在每个存贮器芯片12的每个电极座12a上作为一个凸起电极。此外，如图8(c)表示，一个纽扣凸块15由例如Au形成在控制器芯片14的每个电极座14a上作为一个凸起电极。这些纽扣凸块(11，13，15)通过例如使用金线并应用热压粘结与超声振荡的球接合法形成。按照球接合法，在Au线尖端形成一个球然后在应用超声振荡的条件下压力接合在芯片的电极座上。之后，从球部分切断Au线以形成一个凸块。这样，形成在电极座上的纽扣凸块同电极座牢固地连接。
在接线板1中的软层4的顶部接线层中形成许多导线5(参看图3)许多导线6(参看图4)、许多导线7(参看图5)与许多电极座8(参看图6)，虽然对这些未作详细的图示说明。
如图3中表示，许多导线5的每个有一个由一部分导线构成的连接部分5a，导线5的连接部分5a通过形成在绝缘膜9中的孔9a暴露。导线5的其它部分用绝缘膜9覆盖。各导线5的连接部分5a对应于每个缓冲器芯片10的各电极座10a布置。
如图4表示，许多导线6的每个有一个由一部分导线构成的连接部分6a，导线6的连接部分6a通过形成在绝缘膜9中的孔9b暴露。导线6的其它部分用绝缘膜9覆盖。各导线6的连接部分6a对应于每个存贮器芯片12的各电极座12a布置。
如图5表示，许多导线7的每个有一个由一部分导线构成的连接部分7a，导线7的连接部分7a通过形成在绝缘膜9中的孔9c暴露。导线7的其它部分用绝缘膜9覆盖。各导线7的连接部分7a对应于控制器芯片14的各电极座14a布置。
如图6表示，许多电极座8通过形成在绝缘膜9中的孔9d暴露。电极座8由软层4的顶部接线层中形成的许多导线的各一部分构成，许多导线的各其它部分用绝缘膜9覆盖。
许多连接部分5a、6a、7a和许多电极座8分别布置在孔9a、9b、9c、与9d的底部。这样，接线板2有许多连接部分5a、6a、7a与许多电极座8，布置在一个主表面2X的表面层部分的向主表面2X的深度方向比这一个主表面较深的位置上。
如图3中表示，每个缓冲器芯片10以它的电路形成表面10X面向接线板2的一个主表面2X这样的方式装配。一个各向异性的传导树脂20，作为粘结树脂的例子，***在缓冲器芯片10与接线板2之间。使用各向异性传导树脂20，把缓冲器芯片10粘结并固定在接线板2上。
许多纽扣凸块11布置在每个缓冲器芯片10的电极座10a与接线板2的连接部分5a之间以提供一个二者之间的电连接。利用***在接线板2与缓冲器芯片10之间的各向异性传导树脂20的热收缩力(因从热状态返回至正常温度而产生的收缩力)或热固化收缩力(因热固树脂的固化而产生的收缩力)把纽扣凸块11压粘在接线板2的连接部分5a上。混入各向异性传导树脂20的大量传导颗粒的一部分介入在纽扣凸块11与接线板2的连接部分5a之间。
接线板2的连接部分5a每个向接线板2的深度方向凹下。每个纽扣凸块11与有关的连接部分5a在每个这种凹口的内部连接在一起。通过这样在凹口内部连接纽扣凸块11与连接部分5a，在连接板2的一个主表面2X与每个缓冲器芯片10的电路形成表面10X之间的各向异性传导树脂的体积可减小一个相当于凹口降低量的量。
纽扣凸块11通过形成在绝缘膜9中的孔9a同布置在孔9a底部的连接部分5a连接。即是说，纽扣凸块11同布置在向从接线板2的一个主表面2X的深度方向比这一个主表面2X较深位置上的连接部分5a连接。通过这样把连接部分布置在比接线板2的一个主表面2X较深的位置上，在接线板2的一个主表面2X与缓冲器芯片10的电路形成表面10X之间的各向异性导树脂20的体积可减小一个相当于从一个主表面2X至连接部分5a的深度的量。
每个连接部分5a的凹口通过连接部分5a与软层4的弹性变形形成。因此以这种弹性变形为基础的凹口可利用在把缓冲器芯片10装配到接线板2的一个主表面上时使用的压粘力形成。在通过每个连接部分5a与软层4的弹性变形形成凹口的情况下，连接部分5a与软层4的弹性力作用在有关的纽扣凸块11上，使得纽扣凸块11与连接部分5a之间的压粘力增大。
即使接线板2的一个主表面2X与缓冲器芯片10的电路形成表面10X之间的间距由于各向异性传导树脂20厚度方向的扩展与纽扣凸块相应地向上移动而扩大，每个连接部分5a中凹口的降低量随着有关纽扣凸块的移动而变化，使得可保持导线5的连接部分5a同纽扣凸块11连接。
如图4中表示，每个存贮器芯片12在它的电路形成表面12X面向接线板2的一个主表面2X的状态下装配。例如，各向异性传导树脂20***在存贮器芯片12与接线板2之间作为粘结树脂，从而把存贮器芯片12粘结并固定在接线板2上。
许多纽扣凸块13每个布置在存贮器芯片12的每个电极座12a与接线板2的每个连接部分6a之间以提供二者之间的电连接。利用***在接线板2与存贮器芯片12之间的各向异性传导树脂20的热收缩力或热固化收缩力把纽扣凸块13压粘在接线板2的连接部分6a上。混入各向异性传导树脂20的大量传导颗粒的一部分***在纽扣凸块13与接线板1的连接部分6a之间。
接线板2的连接部分6a每个向接线板2的深度方向凹入，而每个纽扣凸块13与有关的连接部分6a在每个这种凹口的底部连接在一起，如同缓冲器芯片10的情况。纽扣凸块13通过形成在绝缘膜9的孔9b同布置在孔9b底部的连接部分6a连接。这样，相似于缓冲器芯片10的情况，纽扣凸块13同布置在向接线板2的一个主表面2X的深度方向比这一个主表面2X较深的位置上的连接部分6a连接。
如图5中表示，控制器芯片14在它的电路形成表面14X面向接线板2的一个主表面2X的状态下装配。在控制器芯片14与接线板2之间***例如各向异性传导树脂20作为粘结树脂，从而用此各向异性传导树脂20把控制器芯片14粘结并固定在接线板2上。
许多纽扣凸块15每个布置在控制器芯片14的每个电极座14a与接线板2的每个连接部分7a之间以提供二者之间的电连接。利用***在接线板2与控制器芯片14之间的各向异性传导树脂20的热收缩力或热固化收缩力把纽扣凸块15压粘在接线板2的连接部分7a上。混入各向异性传导树脂20的大量传导颗粒的一部分***在纽扣凸块15与连接板2的连接部分7a之间。
接线板2的连接部分7a向接线板2的深度方向凹入，如同每个缓冲器芯片10的情况，每个纽扣凸块15与有关的连接部分7a在每个这种凹口的底部粘结在一起。纽扣凸块15通过形成在绝缘膜9中的孔9c同布置在孔9c底部的连接部分7a连接。即是说，如同缓冲器芯片10的情况，纽扣凸块15同布置在一个向从接线板2的一个主表面2X的深度方向比这一个主表面2X较深的位置上的连接部分7a连接。
如图6中表示，电容器17的电极17a通过焊料21同电极座8电气与机械连接。为控制焊料21的润湿与散布，通过形成在绝缘膜9中的孔9d进行电容器电极17a同接线板2的电极座8的连接。电容器18与电阻器19也以与装配电容器17相同的方法装配。
如图7中表示，每个缓冲器芯片10的座阵列间距P1调节至约为110[μm]。每个存贮器芯片12与控制器芯片14的座阵列间距P2、P3调节至约为80[μm]。每个芯片电极座的平面尺寸与座阵列间距有关，且座阵列间距越小，平面尺寸越小。另一方面，形成在每个芯片电极座上的每个纽扣凸块11的高度与每个电极座的平面尺寸有关，且每个电极座的平面尺寸越小，纽扣凸块的高度越低。即是说，形成在每个存贮器芯片12与控制器芯片14上的纽扣凸块13、15的高度比形成在每个缓冲器芯片10上的纽扣凸块的高度较低。
在一个芯片其中纽扣凸块高度大于从接线板2的一个主表面2X至同一接线板的连接线5a、6a、7a的深度的情况下，接线板2的连接部分与柱纽扣凸块可容易地连接在一起，而在一个芯片其中纽扣凸块高度小于从接线板2的一个主表面2X至同一接线板的连接部分的深度的情况下，接线板2的连接部分与纽扣凸块难以连接。
因此，在芯片有一窄的座阵列间距即有小的电极座平面尺寸的情况下，采用多级纽扣凸块结构以增加高度是有效的。在本实施例中，如同图3中所示，每个缓冲器芯片10的纽扣凸块11为单级凸块结构。如图4中所示，每个存贮器芯片12的纽扣凸块13每个为一个有一个形成在每个电极座12a上的基底凸块13a与一个堆叠在此基底凸块13a上的堆叠凸块13b的两级凸块结构。如图5中所示，控制器芯片14的纽扣凸块15每个为一个有一个形成在每个电极座14a上的基底凸块15a与一个堆叠在此基底凸块15a上的堆叠凸块15b的两级凸块结构。如图8中所示，每个纽扣凸块11的高度T1，每个纽扣凸块13的高度T2，与每个纽扣凸块15的高度T3几乎相等。
通过这样调节使座阵列间距不同的芯片在纽扣凸块高度上几乎相等，同样可把座阵列间距窄的存贮器芯片12与控制器芯片14中纽扣凸块13、15同接线板2的连接部分6a、7a连接。
如图7(b)中表示，每个存贮器芯片12的电极座12b布置成中央座阵列。同样，形成在电极座12b上的纽扣凸块13也排成中央凸块阵列。这样，在带有布置成中央凸块阵列的纽扣凸块13的存贮器芯片12用于倒装芯片装配的情况下，将由于存贮器芯片12不良好平衡而导致它相对于接线板2的主表面2X倾斜。
作为克服存贮器芯片12中这种不平衡纽扣凸块阵列的有效措施是把接线板2的连接部分6a布置在一个向从接线板2的一个主表面2X的深度方向比这一个主表面2X较深的位置上。在本实施例中，如图4中所示，连接部分6a被确定在一个比接线板2的一个主表面2X较深的位置上，其深度差为形成在连接部分6a上面的绝缘膜9的厚度。通过这样布置连接部分6a，在倒装芯片装配存贮器芯片12时，纽扣凸块13的高度被接线板2的一个主表面2X至连接部分6a的深度包容，使得接线板2的一个主表面2X与存贮器芯片12的电路形成表面12X之间的间距变窄，从而可抑制存贮器芯片12相对于接线板2的一个主表面2X的倾斜。
为了把连接部分6a布置在一个比接线板2的一个主表面2X较的位置上从而抑制存贮器芯片12相对于接线板2的一个主表面2X的倾斜，必须以这样的方式形成绝缘膜9和孔9b使得绝缘膜9呈现为跨置于存贮器芯片9的周边。即是说，把绝缘膜9的平面尺寸调节至大于每个存贮器芯片12的平面尺寸而把孔9b的平面尺寸做成小于存贮器芯片12的平面尺寸。在本实施例中，绝缘膜9形成为一个基本覆盖接线板2的主表面2X的整个区域的平面尺寸，而孔9b形成为一个小于存贮器芯片12的平面尺寸。而且，孔9b形成为向接线板2的连接部分6a的布置方向延伸的矩形平面形状。
接着，下面将参照图11至图15描述制作MCM1的方法。
图11是一个用于说明一个多级凸块结构的纽扣凸块形成过程的示意剖视图，图12与图13是用于说明一个缓冲器芯片装配过程的示意剖视图，图14与图15是用于说明一个存贮器芯片装配过程的示意剖视图。
首先，提供将装配在接线板2上的电子部件10、12、14、16、17、18与19。
接着，按照球接合法在缓冲器芯片10、存贮器芯片12、控制器芯片14与运算器芯片16上形成纽扣凸块。对于缓冲器芯片10与运算器芯片16，形成单级凸块结构的纽扣凸块。对于存贮器芯片12与控制器芯片14，形成多级凸块结构(本实施例中为两级)的纽扣凸块。以每个存贮器芯片12作为一个例子，现在将给出一个关于形成两级凸块结构的纽扣凸块方法的说明。首先，把一个存贮器芯片12安装在热台25上，然后如图11(a)中所示，按照球接合法在存贮器芯片12的电极座12a上形成一个基底凸块13a，之后在基底凸块13a上形成一个堆叠凸块13b，如图11(b)中所示。通过在堆叠凸块13b上进一步形成一个堆叠凸块可形成一个三级或更多级的凸块结构。
接着，把一个加工成片(膜)形的各向异性传导树脂20附着在接线板2的一个主要表面2X上的一个缓冲器芯片装配区域上。关于这里使用的各向异性传导树脂20，是一种例如其中混合大量传导颗粒的环氧热固化树脂。
接着，把接线板2装在台26A上，之后，如图12中所示，通过在接线板2的一个主表面2X上的缓冲器芯片装配区域内的各向异性传导树脂20装配缓冲器芯片10。以这样的方法进行缓冲器芯片10的装配使它的电路形成表面10X面向接线板2的一个主表面2X。
接着，把接线板2装在热台26B上，然后，如图13中所示，在加热状态下使用工具27把缓冲器芯片10压粘在接线板2上，随之每个纽扣凸块11同接线板2的有关连接部分5a连接，并保持此压粘状态直至各向异性传导树脂固化。这时，纽扣凸块11同接线板2的连接部分5a被压力粘结。在此过程中，通过设置从接线板2的一个主表面2X至连接部分5a的深度小于纽扣凸块11的高度，利用缓冲器芯片10的压粘力在连接部分5a的连接纽扣凸块11的部分内引成一个凹口。接线板2的连接部分5a同纽扣凸块在凹口内部连接在一起。由于凹口由连接部分5a与软层4的弹性变形形成，因此有一个连接部分5a与软层4的弹性力作用在纽扣凸块11上。
接着，通过与对缓冲器芯片10相同的装配方法在接线板2的一个主表面2X上的一个运算器芯片装配区域内装配运算器芯片16。
接着，把一个加工成片(膜)状的各向异性传导树脂20附着在接线板2的一个主表面2X上的存贮器芯片装配区域上。关于这里使用的各向异性传导树脂20，是一种例如其中混合大量传导颗粒的环氧热固化树脂。
接着，把接线板2装在台26A上，之后，如图14所示，通过接线板2的一个主表面上的存贮器芯片装配区域内的各向异性传导树脂20装配存贮器芯片12。这样进行存贮器芯片12的装配使它的电路形成表面12X面向接线板2的一个主表面2X。接着，把接线板2装在热台26B上，之后，如图15所示，在加热状态下使用工具28把存贮器芯片12压粘在接线板2上，随之每个纽扣凸块13同有关的连接部分6a连接，并保持此压粘状态直至各向异性传导树脂20固化。这时，纽扣凸块13同接线板2的连接部分6a被压力粘结。在此过程中，如同对缓冲器芯片10的情况，利用存贮器芯片12的压粘力在连接部分6a的连接纽扣凸块13的部分内形成一个凹口。连线板2的每个连接部分6a同有关的纽扣凸块13在凹口内部连接在一起。由于凹口内连接部分6a与软层4的弹性变形形成，因此有一个连接部分6a与软层4的弹性力作用在纽扣凸块13上。
而且，在此过程中，由于每个纽扣凸块是多级凸块结构，因此即使在座阵列间距窄的存贮器芯片12的情况下，此纽扣凸块也能同接线板2的有关连按件6a连接。
此外，在此过程中，由于连接部分6a位于比接线板的一个主表面2X较深的其差值为形成在连接部分6a上的绝缘膜9厚度的位置上，因此纽扣凸块13的高度被从接线板2的一个主表面2X至连接部分6a的深度包容，从而使接线板2的一个主表面2X与存贮器芯片12的电路形成表凸12X之间的间距变窄。如果此间距变窄，即使存贮器芯片12在装配过程中倾斜，例如接线板2的一个主表面2X支撑存贮器片12，也可防止它倾斜至使得在装配后造成结构方面的问题这样的程度。
在用于粘结芯片的粘结树脂中含有例如传导颗粒一氧化硅填料的微粒物质，此微粒物质夹在接线板2的一个主表面2X与存贮器芯片12的电路形成表面12X之间，使得在半导体芯片装配过程中存贮器芯片12的倾斜受到进一步的抑制。
此外，当半导体芯片装配过程中粘结树脂20的粘度高时，存贮器芯片12的倾斜受到抵抗粘结树脂流动的阻力的抑制。因此，通过这些机制中的任何机制，可抑制存贮器晶12相对于接线板2的一个主表面2X的倾斜。
接着，通过与对存贮器芯片12相同的装配方法，把控制器芯片14装配在接线板的一个主表面2X上的控制器芯片装配区域内。同样，在座阵列间距窄的控制器芯片14的情况下，可把每个纽扣凸块15同接线板2的有关连接部分7a连接。
芯片装配顺序不受上述顺序的限制。例如，可首先装配存贮器芯片与控制器芯片。
接着，把膏状焊料21涂敷在接线板2的电极座8上，然后把有源元件17、18、19、布置在电极座8上，继之通过加热处理熔解膏状焊料21以相互固定有源元件电极与接线板2的电极座。
然后，在接线板2的一个主表面2X的相对背侧上布置的许多电极座的这些表面上分别形成作为连接端子的球状焊料凸块22，从而基本完成本实施例的MCM1。
根据本实施例得到下列结果。
(1)在MCM1中，许多连接部分6a布置在向从接线板2的一个主表面2X较深的位置上。按照这个构造，在倒装装配不平衡凸块阵列的存贮器芯片12时，纽扣凸块13的高度被从接线板2的一个主表面2X至连接部分6a的深度包容，随之使接线板2的一个主表面2X与存贮器芯片12的电路形成表面12X之间的间距变窄，从而可抑制存贮器芯片12相对于接线板2的一个主表面2X的倾斜。
(2)在MCM1中，接线板2有形成在一个主表面2X上的绝缘膜9，形成在绝缘膜9中的孔9b，与布置在孔9b底部的连接部分6a。绝缘膜9控制润湿与在装配焊接部件(在本实施例中为17、18与19)时焊接部件焊料的散布，并保证在装配部件时倒装芯片部件(10，12与14)有足够的粘结力。根据这个构造，可容易地构成这样的接线板2，其中许多连接部分6a布置在向从接线板2的一个主表面2X的深度方向比这个主表面2X较深的位置上，使可提供其中按照倒装芯片法把不平衡凸块阵列存贮器芯片12装配在接线板2的一个主表面2X上的MCM1。
(3)在MCM1中，每个有窄的座间距的存贮器芯片12与控制器芯片14的纽扣凸块13、15做成多级凸块结构。根据这个构造，即使在存贮器芯片12与控制器芯片14每个有窄的座阵列间距的情况下，纽扣凸块(13，15)可同接线板2的连接部分(6a，7a)连接，从而使座阵列间距不同的缓冲器芯片10、存贮器芯片12、控制器芯片14与运算器芯片16可装配在单块接线板2中。
虽然在本实施例中描述了一个中央凸块阵列作为芯片上的不平衡凸块阵列的一个例子，还有如图16中所示的这样一些其它的芯片上的不平衡凸块阵列。图16(a)表示一个其中许多纽扣凸块13布置成z字形的中央凸块阵列。图16(b)表示一个其中许多纽扣凸块13配置成不同阶梯的中央凸块阵列。图16(c)表示一个一边凸块阵列。芯片上不平衡凸块阵列的另外例子包括：其中芯片的电路形成表面被划分为三个相等的区域而纽扣凸块布置在此三个区域之一内的凸块阵列；其中半导体芯片的重心位于由连接各凸块而形成的多边形之外的凸块阵列。
本实施例中采用的纽扣凸块13为两级凸块结构以增加它们的高度，但根据从接线板2的一个主表面2X至连接部分6a的深度与每个电极座12a的平凸尺寸，也可采用如图17中所示的这样一种三级凸块结构，其中纽扣凸块13包括一个同电极座2a连接的基底凸块13a，一个堆叠在基底凸块13a上的堆叠凸块13b，与一个堆叠在堆叠凸块13b上的堆叠凸块13c。
虽然在本实施例中采用的两级凸块结构中基层底凸块13a与堆叠凸块13b的直径几乎相等，也可采用如图18中所示的包括一个基底凸块13a与一个不同直径的堆叠凸块13b的这样一种两级凸块结构。在此情况下，通过在按照球接合法形成纽扣凸块时使用不同直径的Au线，可得到一个基底凸块13a与一个不同直径的堆叠凸块13b。
虽然在本实施例中采用纽扣凸块作为形成在每个半导体芯片的电极座上的凸起电极，但不由此构成限制。例如，也可使用含有Pb-Sn成份的焊料凸块。在此情况下，使用的焊料凸块熔点高于在装配半导体芯片时采用的热压粘温度的材料制成。
虽然在本实施例中***在每个半导体芯片的各电极座与接线板的各连接部分之间的凸起电极预先形成在芯片的电极座上，这些凸起电极也可预先形成在接线板的连接部分上。
虽然本实施例中使用一种片状的各向异性传导树脂作为把每个半导体芯片粘结并固定在接线板上的粘结树脂，但这不构成限制。例如，可使用一种膏状的各向异性传导树脂(ACP：各向异性导电膏)或一种片状的不传导树脂(NCF：不传导膜)。
现在，将参照图19与图20给出关于改进在耐湿试验中的连接可靠性的说明。图19是一个表示根据本发明的第二实施例的MCM中的一个装配状态下的存贮器芯片的示意剖视图，而图20是一个表示放大比例的图19的一部分的示意剖视图。本实施例中使用的柱形凸板13为单级结构。
在使用各向异性传导树脂20的倒装芯片装配结构中，保证在防混试验中有高的连接可靠性是重要的。经评估接线板2中各种不同厚度的绝缘膜9的抗湿性，本发明发现通过减薄绝缘膜9提高了接线板2的连接部分6a与纽扣凸块13之间的连接寿命。认为这是由于下述原因。
在ACF装配法中，参照一个存贮器芯片12作为例子，把此存贮器芯片12通过各向异性传导树脂20放置在接线板2上，然后在加热状态下压粘在接线板上，从而固定在接线板上，同时纽扣凸块13同接线板2的连接部分6a连接。这时，各向异性传导树脂20充入形成在绝缘膜9中的孔9b内。各向异性传导树脂20具有在固化后由于吸湿而体积膨胀的特性。充入里面有纽扣凸块13的孔 9b的各向异性传导树脂20比充入接线板2的一个主表面2X与每个存贮器芯片12的电路形成表面12X之间的各向异性传导树脂20较厚，使得由吸湿引起的膨胀而导致的位移量也变大。当从接线板2中软层4的弹性形变恢复不再能跟随在接线板2的一个主表面2X与存贮器芯片12的电路形成表面12X之间的由各向异性传导树脂20的吸湿膨胀引起的位移时，从而发生纽扣凸块13与接线板2的连接部分6a之间的连接缺陷。由于孔9b的深度取决于绝缘膜9的厚度，绝缘膜9越薄，孔9b越浅，使得孔9b内部的各向异性传导树脂20的体积变为较小。因此，认为通过减薄绝缘膜9可提高接线板2的连接部分6a与纽扣凸块13之间连接的寿命。
下面是在温度85℃与湿度85％条件下得到的评估结果的一个例子。
(1)当导线6上面的绝缘膜9的厚度9t(参看图20)调节至25[μm]时，连接寿命为96h。
(2)当导线6上面的绝缘膜9的厚度9t调节至20[μm]时，连接寿命不短于500h。
(3)当导线6上面的绝缘膜9的厚度9t调节至15[μm]时，连接寿命不短于500h。
根据以上结果判断，导线6上面的绝缘膜9的厚度9t较好为不大于20[μm]。
作为可能的情况，绝缘膜9中混入大量的填充物。在此情况下，必须把导线6上面绝缘膜9的厚度9t制成大于混入绝缘膜中的填充物的最大颗粒直径。如果绝缘膜9的厚度9t制成小于填充物的最大颗粒直径，填充物将从绝缘膜9中跳出。
当为了改进可靠性而把纽扣凸块13制成较小并相应地把绝缘膜9的厚度9t制成较小时，如果绝缘膜9的厚度9t变为这样小以致不适于控制润湿与在周围位置内形成的焊接部件焊料的散布，可根据在接线板上的位置改变绝缘膜的厚度使其成为最佳厚度。
虽然上面已根据上述各实施例具体地描述了本发明，不用说本发明不受那些实施例的限制，而可在不违背本发明的要旨的范围内做出各种修改。
下面是由本发明获得的典型效果的简要说明。
可抑制半导体芯片相对于接线板的一个主表面的倾斜。
可在单块接线板上安装阵列间距不同的多种类型的半导体芯片。

Claims (16)

1.一种电子装置，包括：
一个第一半导体芯片，有多个按第一阵列间距布置在该第一半导体芯片的一个主表面上的第一电极座；
一个第二半导体芯片，有多个按小于第一阵列间距的第二阵列间距布置在该第二半导体芯片的一个主表面上的第二电极座；
一块接线板，在该接线板的一个表面的一个第一区域内有多个对应于所述多个第一电极座布置的第一连接部分，而在该接线板的所述表面的一个不同于第一区域的第二区域内有多个对应于所述多个第二电极座布置的第二连接部分；
多个分别布置在所述多个第一电极座与所述多个第一连接部分之间而提供所述多个第一电极座与所述多个第一连接部分之间的电连接的第一凸起电极；与
多个分别布置在所述多个第二电极座与所述多个第二连接部分之间而提供所述多个第二电极座与所述多个第二连接部分之间的电连接的第二凸起电极，
所述多个第一连接部分与所述多个第二连接部分布置在从所述接线板的所述表面的深度方向上比所述接线板的所述表面较深的位置上；且
所述多个第二凸起电极为一个比所述多个第一凸起电极有更多的级数的多级凸块结构。
2.根据权利要求1的电子装置，其中接线板还有一个暴露在该接线板的所述表面上的绝缘膜，形成在该接线板的所述表面的第一区域内的绝缘膜中的第一孔，与形成在该接线板的所述表面的第二区域内的绝缘膜中的第二孔，所述多个第一连接部分布置在第一孔的底部，而所述多个第二连接部分布置在第二孔的底部。
3.根据权利要求1的电子装置，其中第二凸起电极每个为多级凸块结构，该结构有一个同第二半导体芯片的每个第二电极座连接的基底凸块与一个堆叠在基底凸块上的堆叠凸块。
4.根据权利要求1的电子装置，其中第二凸起电极每个为多级凸块结构，该结构有一个同第二半导体芯片的每个第二电极座连接的基底凸块、一个堆叠在基底凸块上的第一堆叠凸块与一个堆叠在第一堆叠凸块上的第二堆叠凸块。
5.根据权利要求1的电子装置，其中第一与第二凸起电极为纽扣凸块。
6.根据权利要求1的电子装置，其中接线板有一个多层互连结构，而它的所述多个第一与第二连接部分分别为形成在接线板的顶部接线层上的多条导线的各个部分。
7.根据权利要求1的电子装置，其中第一与第二半导体芯片通过粘结树脂粘结在接线板上。
8.根据权利要求7的电子装置，其中粘结树脂是一种包括其中混合大量传导颗粒的绝缘树脂的各向异性的传导树脂。
9.根据权利要求1的电子装置，其中半导体芯片的所述一个主表面为矩形，而第一直线同半导体芯片的所述一个主表面的两条短边相交。
10.根据权利要求1的电子装置，其中半导体芯片形成为平面内的一个四边形形状，而凸起电极布置在通过把所述第二半导体芯片的所述一个主表面划分为三个相等区域而得到的三个区域的一个中心区域中。
11.根据权利要求1的电子装置，其中所述多个连接部分均具有一个凹口，与其相连的各凸起电极具有容纳进所述凹口中的一个部分。
12.根据权利要求11的电子装置，其中所述多个连接部分的每一个的凹口是通过连接部分和接线板的弹性形变形成的。
13.根据权利要求12的电子装置，其中半导体芯片形成为平面内的一个四边形形状，而凸起电极布置在通过把所述第二半导体芯片的所述一个主表面划分为三个相等区域而得到的三个区域的一个中心区域中。
14.根据权利要求13的电子装置，其中所述第二半导体芯片具有动态随机存取存储器，该动态随机存取存储器是SDRAM。
15.一种制作一种电子装置的方法，包括步骤：
提供：一个有许多按第一阵列间距布置在它的一个主表面上的第一电极座与许多分别同这些第一电极座连接的第一凸起电极的第一半导体芯片；一个有许多按小于第一阵列间距的第二阵列间距布置在它的一个主表面上的第二电极座与许多分别同这些第二电极座连接的并有级数比第一凸起电极更多的多级凸块结构的第二凸起电极的第二半导体芯片；与一块接线板，该板有一个形成在它的一个主表面上的绝缘膜、形成在所述一个主表面的第一区域内的绝缘膜中的第一孔、形成在所述一个主表面的不同于第一区域的第二区域内的绝缘膜中的第二孔、许多对应于许多第一凸起电极布置在第一孔底部的第一连接部分与许多对应于许多第二凸起电极布置在第二孔底部的第二连接部分；
在接线板的所述一个主表面的第一区域与第一半导体芯片的所述一个主表面之间***第一粘结树脂并把第一半导体芯片压粘到接线板的所述一个主表面的第一区域上以分别电连接各第一凸起电极与各第一连接部分；与
在接线板的所述一个主表面的第二区域与第二半导体芯片的所述一个主表面之间***第二粘结树脂并把第二半导体芯片压粘到接线板的所述一个主表面的第二区域上以分别电连接各第二凸起电极与各第二连接部分。
16.一种电子装置，包括：
一个第一半导体芯片，在该第一半导体芯片的一个主表面上有一个第一电极座；
一个第二半导体芯片，在该第二半导体芯片的一个主表面上有一个第二电极座，此第二电极座有一个比第一电极座小的平面面积；
一块接线板，具有：一个绝缘膜；形成在一个第一区域内的该绝缘膜中的第一孔；形成在所述一个不同于第一区域的第二区域内的该绝缘膜中的第二孔；一个布置在第一孔底部的第一连接部分；与一个布置在第二孔底部的第二连接部分；
一个布置在所述接线板的第一区域与所述第一半导体芯片的所述一个主表面之间的第一粘结树脂；
一个布置在所述接线板的第二区域与所述第二半导体芯片的所述一个主表面之间的第二粘结树脂；
一个布置在第一电极座与第一连接部分之间以提供二者之间电连接的第一凸起电极；与
一个布置在第二电极座与第二连接部分之间以提供二者之间电连接的第二凸起电极，
其中第二凸起电极有一个级数比第一凸起电极更多的多级凸块结构。
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