CN1185697C - 安装半导体芯片的方法 - Google Patents

安装半导体芯片的方法 Download PDF

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Publication number
CN1185697C
CN1185697C CNB001225316A CN00122531A CN1185697C CN 1185697 C CN1185697 C CN 1185697C CN B001225316 A CNB001225316 A CN B001225316A CN 00122531 A CN00122531 A CN 00122531A CN 1185697 C CN1185697 C CN 1185697C
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chip
magnetic head
instrument
semiconductor chip
bonding
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CN1320957A (zh
Inventor
马场俊二
山上高丰
海沼则夫
小八重健二
吉良秀彦
小林弘
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Fujitsu Ltd
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Fujitsu Ltd
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Abstract

一种安装半导体芯片的方法，其中通过用作为底填料的粘合剂填充芯片和基板之间的间隙来安装IC芯片。底填料的轮廓线做成具有需要的形状。为此，提供有突点的磁头IC芯片放置在由底填料粘合剂覆盖并提供有焊盘的悬杆上。一粘结工具按压磁头IC芯片并对磁头IC芯片施加超声振荡，以将突点正确地粘结到焊盘上。当按压磁头IC芯片并进行超声振荡时，发出紫外线108以硬化在磁头IC芯片11和悬杆12之间扩展的粘合剂151的周边部分151a。

Description

安装半导体芯片的方法
技术领域
本发明通常涉及安装半导体芯片的方法，以及安装半导体芯片的装置。
背景技术
安装半导体芯片的方法适用于将硬盘装置10的磁头IC芯片11安装到悬杆(suspension)12上，如图1A和1B所示，或将印制电路板单元30的IC芯片31安装到基板32上，如图3A到3C所示。
如图1A和1B所示，硬盘装置10有一个在气密地密封的外壳15中高速旋转的硬盘16，而且磁头滑动器组件19固定到臂18的顶端。磁头滑动器组件19包括磁头滑动器20和安装在悬杆12上的磁头IC芯片11，如图2所示。磁头滑动器20带有一个由薄膜形成技术形成的磁头21。磁头IC芯片11通过例如放大由磁头21读取的弱信号而控制磁头21。如图2的放大图所示，磁头IC芯片11在它的下表面有金突点(Au bump)22粘结到布线图形23边缘处的金焊盘24上。
印制电路板单元30包括提供有热沉的多芯片组件36、存储器插座38以及I/O连接器39，所有这些都安装在母板35上，如图3A所示。多芯片组件36有多个安装在基板32上的IC芯片31，如图3B所示。磁头IC芯片31在它的下表面有金突点42粘结到形成在基板32上的金焊盘43上。磁头IC芯片31通过底填料(underfill)44粘结到基板32上。
图4A到4C表示常规的磁头滑动器组件的制造方法。在磁头IC芯片11的下表面有金突点51。在悬杆12的上表面有金焊盘61。所述磁头滑动器组件以下面的方式制造。
首先，悬杆12固定到工作台70上。然后使用精密的分配器(未示出)，将作为“底填料”的预定量绝缘粘合剂71涂敷到悬杆12的上表面。磁头IC芯片11由具有吸气孔76的工具75的负压吸引拾取，并移到悬杆12上。然后工具75用力F按压磁头IC芯片11，几微米振幅的超声振动施加到磁头IC芯片11几秒钟，如箭头B所示。由此，金突点51粘结到金焊盘61上。然后停止工具75的负压吸引，由此工具75与磁头IC芯片11分离。之后将悬杆12移到加热炉80，以便通过加热固化粘合剂71。这里，形成底填料72，并通过底填料72将磁头IC芯片11粘结到悬杆12上。由此，完成了磁头滑动器组件19。
以上常规的磁头滑动器组件19的制造方法至少显示出以下不足：
1.底填料的轮廓线的形状不稳定。
作为底填料的粘合剂71在悬杆12上为圆形，如图5A中的双点划线所示。当工具75按压磁头IC芯片11时，粘合剂71被磁头IC芯片11的下表面按压，并放射状地扩展。扩展的粘合剂71延伸到磁头IC芯片11下表面的周围，并形成轮廓线90。由作为底填料的粘合剂71的扩展状态确定轮廓线90的形状。粘合剂71的扩展状态随粘合剂71的施加量和施加位置而变化。根据情况，粘合剂71会在悬杆12的上表面上显著溢流，如图5A和5B中的参考数字91所示。
随着硬盘装置变小，悬杆12的宽度W1也变小。另一方面，随着添加更多的功能，磁头IC芯片11在图5A所示的L1的方向上变大。因此，悬杆12上安装的磁头IC芯片11的外部的额外部分92宽度W2变小。此外，粘合剂大量的溢流对于磁头滑动器20相对于硬盘的浮动特性具有不利影响。
对于图3A到3B中所示的多芯片组件36来说，基板32上表面上粘合剂的大量溢流经常妨碍其它部件的安装。
2.溢流的粘合剂粘到工具75上
根据粘合剂71的施加量和施加位置，粘合剂71溢流到磁头IC芯片11的上表面，并粘到工具75的顶端，如图6A和6B中的参考数字93所示。
当粘合剂71粘到工具75的顶端时，工具75的吸引操作变成不稳定。因此，工具75的顶端需要经常清理。然而，每次完成一个磁头IC芯片11的安装时，清理工具75的顶端很麻烦。
当从上面看时，施加的粘合剂71为圆形并放射状扩展。因此粘合剂71从磁头IC芯片11的侧面溢出，并延伸到磁头IC芯片11的上表面。
3.由工具75到磁头IC芯片11的超声波传导率很低。
如图4B所示，工具75直接与磁头IC芯片11接触。工具75由不锈钢制成，磁头IC芯片11由硅制成。工具75和IC芯片11之间的摩擦系数μ1在0.5到0.7的范围内，较低。因此，由工具75到磁头IC芯片11的超声波传导率很低，且金突点51到金焊盘61的粘结需要很长的时间。
4.安装时磁头IC芯片经常偏离，偏离导致有缺陷安装。
如图4B所示，工具75和磁头IC芯片11直接相互接触。由于工具75的端面75的轻微取向，每次工具75超声振荡时，沿超声振荡的一个方向(例如沿X1方向)，磁头IC芯片11与图7A所示的初始位置稍微偏离。根据情况，金突点51可能会脱离金焊盘61，如图7B所示，导致有缺陷的粘结。
在图3A到3C所示的多芯片组件36中，在基板32上形成的焊盘中每个均为矩形，如图8中的参考数字43A所示。然而，图8中水平对准的焊盘43A的纵向等于图8中垂直对准的焊盘43A的宽度方向。因此，当工具75超声振荡时，基板32上的焊盘不能总是有效地防止磁头IC芯片11偏离。
发明内容
鉴于此，本发明致力于提供一种半导体芯片的安装方法和装置，其中消除了以上问题。
为解决以上问题，本发明提供一种将半导体芯片安装到基板上的方法，包括以下步骤：
通过按压半导体芯片，利用置于半导体芯片和基板之间的绝缘粘合剂，将形成在半导体芯片上的突点粘结到基板上形成的焊盘上；
硬化在半导体芯片和基板之间扩展出的绝缘粘合剂，
其中硬化步骤包括以下步骤：
通过加热来硬化在半导体芯片和基板之间扩展出的绝缘粘合剂的周边部分；
通过加热来硬化全部绝缘粘合剂。
当按压半导体芯片时，由于绝缘粘合剂的周边部分从半导体芯片和基板之间被扩展出去，因此可以防止大量的绝缘粘合剂溢流。由此底填料的轮廓线可以形成希望的形状。
按照以上方法，粘结步骤还包括向半导体芯片施加超声振荡以将形成在半导体芯片上的突点粘结到基板上形成的焊盘上。
由于绝缘粘合剂不会大量溢流，因此可以防止绝缘粘合剂进入粘结工具和半导体芯片之间的接触空间。由此可以保持优选的接触条件。
按照以上方法，通过光或热固化绝缘粘合剂的周边部分。
采用光或加热，可以快速和稳定地固化在半导体芯片和基板之间扩展的绝缘粘合剂的周边部分。
本发明还提供一种半导体芯片安装装置，包括：
按压半导体芯片的机构，同时在提供有突点的半导体芯片和提供有焊盘的基板之间设置绝缘粘合剂，并通过将突点粘结到焊盘上而将半导体芯片安装到基板上；
周边部分硬化单元，当按压半导体芯片时，该周边部分硬化单元通过加热来硬化由半导体芯片的周边露出的绝缘粘合剂的周边部分；以及
加热头，该加热头通过加热来硬化全部所述绝缘粘合剂。
由于按压半导体芯片时绝缘粘合剂的周边部分在半导体芯片和基板之间扩展，因此绝缘粘合剂可以防止大量溢流。由此底填料的轮廓线可以形成希望的形状。
以上的半导体芯片安装装置还包括将突点超声粘结到焊盘上的超声波振荡器。
由于绝缘粘合剂不会大量溢流，因此可以防止绝缘粘合剂进入传输超声振荡的粘结工具和半导体芯片之间的接触空间。由此可以保持希望的接触条件。
在以上的半导体芯片安装装置中，周边部分硬化单元为光提供单元或热提供单元。
采用光提供单元或热提供单元，可以快速和稳定地固化在半导体芯片和基板之间扩展的绝缘粘合剂的周边部分。
本发明还提供一种半导体芯片安装装置，其包括按压半导体芯片的粘结工具，同时绝缘粘合剂置于提供有突点的半导体芯片和提供有焊盘的基板之间，并将突点超声粘结到焊盘上，其中该粘结工具基本为方杆形，其侧面相对于粘结工具的相邻拐角之间实际(virtual)的平坦表面向内弯曲。
当粘结工具按压并且超声振荡施加到半导体芯片时，绝缘粘合剂从半导体芯片的侧面，而不是半导体芯片的拐角溢出。粘结工具基本为方杆形，而且粘结工具的侧面相对于粘结工具的相邻拐角之间实际上的平坦表面向内弯曲。在所述结构中，溢流的绝缘粘合剂没有延伸和粘住粘结工具。因此，不需要清理粘结工具。此外，由于粘结工具基本为方杆形，因此粘结工具可以均匀地按压包括拐角在内的整个半导体芯片。由此，不会在半导体芯片中发生龟裂。
本发明还提供一种将半导体芯片安装在基板上的安装方法，通过粘结工具按压半导体芯片，同时将绝缘粘合剂置于提供有突点的半导体芯片和提供有焊盘的基板之间，并将突点超声粘结到焊盘上，其中将一对于半导体芯片和粘结工具的摩擦系数比半导体芯片和粘结工具之间的摩擦系数大的薄片置于半导体芯片和粘结工具之间，由此进行超声粘结。
由于置于半导体芯片和粘结工具之间的薄片对于半导体芯片和粘结工具的摩擦系数比半导体芯片和粘结工具之间的摩擦系数大，因此可以高效率地进行由粘结工具到半导体芯片的能量传输，而且将形成在半导体芯片上的突点粘结到形成在基板上的焊盘上可以在短时间周期内完成。此外，在半导体芯片的位置很少发生偏离。
本发明还提供一种半导体芯片安装装置，包括一按压半导体芯片的粘结工具，同时绝缘粘合剂置于提供有突点的半导体芯片和提供有焊盘的基板之间，并将突点超声粘结到焊盘上；以及在半导体芯片和粘结工具之间移动和放置一对于半导体芯片和粘结工具的摩擦系数比半导体芯片和粘结工具之间的摩擦系数大的薄片的装置。
由于粘结工具和薄片以及薄片和半导体芯片之间的摩擦系数都大于粘结工具和半导体芯片之间的摩擦系数，因此通过在半导体芯片和粘结工具之间放置薄片，可以有效地进行由粘结工具到半导体芯片的能量传输。因此，将形成在半导体芯片上的突点粘结到形成在基板上的焊盘可以在短时间周期内完成。此外，在半导体芯片的位置很少发生偏离。
本发明还提供一种通过超声粘结将半导体芯片安装其上的基板，其所包括的每个焊盘具有沿施加到半导体芯片上的超声振荡的方向拉长的形状。
当粘结工具向半导体芯片施加超声振荡时，由于粘结工具的取向使半导体芯片趋于移动。然而在以上结构中，形成在半导体芯片上的突点不会离开具有沿施加到半导体芯片上的超声振荡的方向拉长的形状的每个焊盘。由此可以防止半导体芯片和基板之间的有缺陷粘结。
附图说明
图1A和1B表示常规的硬盘装置；
图2表示在图1A和1B的硬盘装置中的磁头滑动组件；
图3A到3C表示常规的印制电路板单元；
图4A到4C表示制造常规半导体芯片的方法；
图5A和5B表示现有技术存在的第一个问题；
图6A和6B表示现有技术存在的第二个问题；
图7A和7B表示现有技术存在的第四个问题；
图8表示现有技术的矩形焊盘；
图9A和9B表示本发明第一实施例的磁头IC芯片安装装置；
图10为图9A和9B所示紫外线灯的布局的平面图；
图11为磁头滑动组件的制造工序的流程图；
图12A到12D为图9A和9B的芯片安装装置的操作时序图；
图13表示图11的流程中的定位步骤；
图14表示图11的流程中的按压和紫外线照射的步骤；
图15表示图11的流程中的按压、超声振荡、以及紫外线照射步骤；
图16表示按压、超声振荡、以及紫外线照射步骤之后的情况；
图17A和17B表示由图11所示的工序完成的磁头滑动组件的一部分；
图18A和18B表示本发明第二实施例的芯片安装装置；
图19A和19B表示本发明第三实施例的芯片安装装置；
图20表示图19A和19B所示粘结工具的顶端；
图21表示图20粘结工具的第一种改型；
图22表示图20粘结工具的第二种改型；
图23A和23B表示本发明第四实施例的芯片安装装置；
图24表示图23A和23B所示聚酰亚胺薄膜支撑机构；
图25为使用图23A和23B的芯片安装装置制造图2的磁头滑动组件的方法流程图；
图26A到26F为图23A和23B的芯片安装装置的操作的时序图；
图27表示图25的工序中芯片定位步骤之后的情况；
图28表示图25的工序中的临时放置步骤；
图29表示图25的工序中的粘结工具提升步骤；
图30表示图25的工序中的聚酰亚胺薄膜***步骤；
图31表示图25的工序中按压和超声振荡步骤；
图32表示图25的工序中粘结工具提升和聚酰亚胺薄膜支撑机构的缩回步骤；
图33A和33B表示图25的工序中聚酰亚胺薄膜馈送步骤；
图34A到34D表示本发明第五实施例的磁头滑动组件；
图35A到35H表示图34A到34D所示金焊盘的制造工序；
图36A到36G表示从图35H继续的制造工序；以及
图37A和37B表示本发明第六实施例的磁头滑动组件。
具体实施方式
第一实施例解决了底填料的轮廓线的形状不可靠的问题。
图9A和9B表示作为本发明第一实施例的磁头IC芯片安装装置100。磁头IC芯片安装装置100包括工作台101、粘结单元110以及控制单元130。
工作台101容纳图2所示的悬杆12，并提供有吸气孔102用于吸引和牵引悬杆12。在工作台101上，还有四个紫外线灯104到107环绕在芯片安装位置109周围，面向被安装的磁头IC芯片11的四个侧面，以便用紫外线照射磁头IC芯片11的全部四个侧面。
粘结单元110包括粘结头111、从粘结头111垂下的粘结工具112、以及与粘结工具112形成一体的超声振荡器113。粘结工具112通过升降机构(未示出)上下移动。粘结单元110由磁头IC芯片安装装置100的框架103可移动地支撑，并且可以通过移动机构(未示出)移动。
粘结头111包含连接到电源或真空源(未示出)上的负载传感器(按压机构)114和阀115。负载传感器114上下移动粘结工具112，并测量通过粘结工具112施加到磁头IC芯片50上的力。
粘结工具112提供有与阀115相通的吸气孔116。超声振荡器113向粘结工具112提供超声振荡。
控制单元130包括控制超声振荡器113的控制器131、控制负载传感器114的控制器132、控制阀115的控制器133、以及控制紫外线灯104到107的控制器134。控制单元130还包括控制所有控制器130到134的综合控制器135。
现在参考图11，下面介绍使用以上的磁头IC芯片安装装置100制造图2的磁头滑动器组件19的方法。
通过进行图11所示的步骤140到147制造磁头滑动器组件19。在步骤140到147之中，通过图12A到12D所示操作磁头IC芯片安装装置100进行步骤144到146。
步骤140
使用引线接合装置使金突点51形成在磁头IC芯片11的下表面上。
步骤141、142和143
金焊盘61形成在悬杆12上，作为底填料的粘合剂150施加到芯片安装位置109的中心。金焊盘61和粘合剂150面朝上，悬杆12放置在工作台101上，并被吸附到工作台101上。
粘合剂150由热固性粘合剂和紫外线固化剂的混合物组成。具体地说，粘合剂150由氨基甲酸乙酯丙烯酸酯树脂作为主要成分，安息香烷基醚作为用于聚合的光引发剂，丙烯酸盐作为热固性引发剂。
定位步骤144(参见图13和12A)
粘结单元110位于与磁头IC芯片11对准的位置。通过升降机构(未示出)向下移动粘结工具112。如图12A所示，根据由控制器133传来的控制信号打开阀115。由粘结工具112的顶端真空吸取一个磁头IC芯片11。然后粘结工具112向上移动以提升磁头IC芯片11。接着，通过移动机构(未示出)沿框架103移动粘结单元110以运送磁头IC芯片11。然后粘结单元110停止在磁头IC芯片11设置在悬杆12上的位置处，如图13所示。
按压和紫外线照射步骤145(图14、12B和12C)
随着升降机构(未示出)的启动，负载传感器114根据控制器132传来的控制信号工作，如图12C所示。然后粘结工具112向下移动用预定的力F按压磁头IC芯片11，由此将金突点51压向金焊盘61。磁头IC芯片11也通过力F扩展粘合剂150。这里，粘合剂150被扩展到粘合剂150的边缘溢出磁头IC芯片11边缘的程度。在图14中，参考数字151表示粘合剂在悬杆12上扩展到磁头IC芯片11。
当负载传感器114开始对磁头IC芯片11加压时，紫外线灯104到107根据控制器134传来的控制信号点亮。磁头IC芯片11周围的区域由紫外线108照射，并且露出磁头IC芯片11边缘的粘合剂151的一部分151a开始硬化。因此，扩展的粘合剂151部分地硬化。在图14中，参考数字152表示硬化的部分。
按照以上的方式，露出磁头IC芯片11边缘的粘合剂151的一部分151a被硬化，由此在露出部分151a处形成坚硬的膜。因此，当将磁头IC芯片11压向悬杆12时，可以防止粘合剂151流出悬杆12。
紫外线108不会到达磁头IC芯片11的底部。因此，此时磁头IC芯片11下面的那部分粘合剂151不会硬化。由此，当按压磁头IC芯片11时，粘合剂150可以平滑地扩展，金突点51可以准确地压向金焊盘61。
按压、超声振荡以及紫外线照射步骤146(参见图15，16，12A，12B，12C和12D)
如图12A，12B和12C所示，紫外线灯104到107点亮，粘结工具112真空吸取磁头IC芯片11，负载传感器114按压磁头IC芯片11。在该条件下，超声振荡器113根据控制器131传来的控制信号开始振荡，并保持振荡几秒钟。
图15表示以上情况。当超声振荡器113振荡时，粘结工具112按箭头B所示超声振荡。粘结工具112的超声振荡传送到磁头IC芯片11的金突点51，金突点51对金焊盘61超声振荡。由此，金突点51被粘结到金焊盘61上。
露出磁头IC芯片11边缘的粘合剂151的一部分151a进一步硬化。在图15中，参考数字153表示进一步硬化的部分。由于露出磁头IC芯片11边缘的部分151a被硬化，因此当磁头IC芯片11超声振荡时，可以防止粘合剂151流出悬杆12。此外，可以防止粘合剂151进入粘结工具112和磁头IC芯片11之间的接触部分。由此，在粘结工具112和磁头IC芯片11之间可以保持希望的接触条件。
紫外线108不会到达磁头IC芯片11的底部。因此，此时磁头IC芯片11下面的那部分粘合剂151没有硬化。金突点51可以正确地压向金焊盘61。由此，在金突点51和金焊盘61之间可以保持希望的粘结条件
图16表示按压、超声振荡以及紫外线照射步骤146之后的情况。紫外线灯104到107关闭，而且金突点51被粘结到金焊盘61上。粘合剂151填充磁头IC芯片11的下表面和悬杆12的上表面之间的小空间152，仅有露出磁头IC芯片11边缘的部分151a硬化。
加热步骤147
从芯片安装装置100中取出粘结有磁头IC芯片11的悬杆12。然后把悬杆12放置到加热炉内以热硬化粘合剂151。此时，整个粘合剂151完全被硬化而形成底填料155。
通过以上的步骤，完成了图17A和17B中所示的磁头滑动器组件19A。形成在磁头IC芯片11下表面的金突点51被粘结到悬杆12上的金焊盘61上。磁头IC芯片11也通过底填料155粘结到悬杆上，底填料155由紫外线固化和热固性粘合剂150硬化形成。底填料155在它的整个周边部分有希望的轮廓线156。由于首先施加粘合剂150，因此底填料155具有高质量并且没有空隙。
本发明的第二实施例为第一实施例的改型，解决了底填料的轮廓线形状变化的问题。
图18A和18B表示本发明第二实施例的芯片安装装置100。芯片安装装置100提供加热器164到167代替图9A和9B中示出的芯片安装装置100的紫外线灯104到107。加热器164到167环绕芯片安装位置109设置，以用热线168照射磁头IC芯片11的所有侧面。
至于粘合剂，可以使用热固性粘合剂150A。
当磁头IC芯片11被压在悬杆12上和对磁头IC芯片11施加超声波时，加热器164到167接通而用热线168照射露出磁头IC芯片11边缘的热固性粘合剂150A的一部分151a，由此硬化露出部分151a。由此，可以防止粘合剂150A流出悬杆12，并且可以形成优良的轮廓线156。
第三、第四和第五实施例解决了溢出的粘合剂粘到粘结工具的问题。
图19A和19B表示本发明第三实施例的芯片安装装置100B。芯片安装装置100B不包括图9A和9B所示的芯片安装装置100的紫外线灯104到107和控制器134，并且提供有图20所示的粘结工具112C代替粘结工具112。
粘结工具112C由不锈钢制成，为柱形。粘结工具112C的剖面为对应于磁头IC芯片11的方形。此外，粘结工具112C与常规的粘结工具112的尺寸相同。粘结工具112C与粘结工具112的不同之处为它具有V形的侧面。换句话说，粘结工具112C为基本上的方柱，具有四个V形侧面112Ca到112Cd和四个拐角112Ce到112Ch。侧面112Ca到112Cd相对于拐角112Ce到112Ch每两个相邻的拐角之间实际的平坦表面向内弯曲。
如图19A所示，粘结工具112C吸取磁头IC芯片11，以便磁头IC芯片11压向悬杆12，拐角112Ce到112Ch则对应于磁头IC芯片11的拐角11a。粘结工具112C的侧面112Ca到112Cd相对于磁头IC芯片11的侧面11b朝磁头IC芯片11的中心弯曲。
当通过粘结工具112C按压磁头IC芯片11时，粘合剂150C会从下面溢出到磁头IC芯片11的上表面。在图19A和19B中，粘合剂150C的溢出部分由参考数字150Ca表示。当从上面看时，施加的粘合剂150C为圆形，且溢出部分应放射形地扩展。因此，磁头IC芯片11上表面上的粘合剂150C的溢出部分150Ca位于磁头IC芯片11的侧面11b上。
由于粘结工具112C的侧面112Ca到112Cd朝磁头IC芯片11的中心弯曲，因此粘合剂150C的溢出部分150Ca不会粘到粘结工具112C的侧面112Ca到112Cd上。因此粘结工具112C的顶端总是保持干净的，且每次完成一个磁头IC芯片11的安装时，不需要麻烦地清理粘结工具112C的顶端。
为防止磁头IC芯片11上表面粘合剂的溢出部分粘到粘结工具的顶端，也可以将粘结工具的顶端加工成方形，并且使粘结工具比磁头IC芯片小得多。然而此时，粘结工具按压磁头IC芯片11的中心，粘结工具的压力集中在磁头IC芯片11的中心。其结果是在磁头IC芯片11中将发生龟裂。
由于粘结工具112C基本上与常规的粘结工具112尺寸相同，因此四个拐角112Ce到112Ch按压磁头IC芯片11的拐角11a的相邻区域。因此，和常规的粘结工具112一样，粘结工具112C按压磁头IC芯片11的整个上表面，由此而在磁头IC芯片11中不会发生龟裂。
代替图20所示的粘结工具112C，可以使用图21所示的粘结工具112D或图22所示的粘结工具112E。
图21所示的粘结工具112D有四个拐角112De到112Dh，和四个弯曲的侧面112Da到112Dd。侧面112Da到112Dd相对于相邻拐角112De到112Dh之间实际的平坦表面向内弯曲。
粘结工具112E有四个拐角112Ee到112Eh，和四个弯曲的侧面112Ea到112Ed。侧面112Ea到112Ed相对于相邻拐角112Ee到112Eh之间实际的平坦表面向内弯曲。
采用图21所示的粘结工具112D或图22所示的粘结工具112E，可以得到和图20所示粘结工具112C一样的效果。
本发明的第四实施例解决了由工具到磁头IC芯片的超声波传导率低的问题。
图23A和23B表示本发明第四实施例的芯片安装装置100F。芯片安装装置100F在工作台101上提供有聚酰亚胺薄膜支撑机构170，代替图9A和9B中芯片安装装置100的紫外线灯104到107。在图23A和23B中，与图9A和9B中相同的部件由相同的参考数字表示，省略了对这些部件的说明。芯片安装装置100F的宽度方向由X1和X2表示，芯片安装装置100F的深度方向由Z1和Z2表示。
如图24所示，聚酰亚胺薄膜支撑机构170包括U形框架172、设置在框架172的X1一侧并支撑用于馈送带型聚酰亚胺薄膜171的供料辊173的供料辊支撑部件174、以及设置在框架172的X2一侧并支撑电动机175和卷绕辊176的卷绕辊支撑部件174。U形框架172可以在工作台101上在Y1-Y2方向上沿导轨178移动。含有电动机180的移动机构181在粘结工具112下的***位置P1和沿Y2方向从***位置P1移动的收回位置之间移动框架172。带型聚酰亚胺薄膜171在供料辊173和卷绕辊176之间水平地延伸，与被安装的磁头IC芯片11的上表面在相同的高度P3。
控制单元130F包括控制电动机180的控制器190和控制电动机175的控制器191，代替图9B中的控制器134。
现在参见图25，介绍使用以上的芯片安装装置100F制造图2的磁头滑动器组件19的方法。
通过步骤140到144，147和200到205制造磁头滑动器组件19。在这些步骤140到144，147和200到205之中，通过图26A到26F所示操作芯片安装装置100F进行步骤144和200到205。
聚酰亚胺薄膜支撑机构170位于图23B和24中所示的收回位置P2。以和图11中所示工序的相同方式进行步骤140到144。
图27表示定位步骤144之后的情况。在图27中，粘结工具112的顶端真空吸取一个磁头IC芯片11，并停止在预定的位置，以将磁头IC芯片11定位到固定在工作台101上的悬杆上。
临时放置步骤200(参见图28、26A和26B)
随着升降机构(未示出)的启动，粘结工具112向下移动，以便磁头IC芯片11扩展粘合剂150。因此，磁头IC芯片11通过粘合剂150定位并粘接到悬杆12上。由此，磁头IC芯片11被临时地放置在悬杆12上。
粘结工具提升步骤201(参见图29、26A和26B)
如图26A所示，关闭阀115以停止真空吸取。如图28和26B所示，粘结工具112通过升降机构(未示出)向上移动，将磁头IC芯片11留在悬杆12上。
聚酰亚胺薄膜***步骤202(参见图30和26C)
如图26C所示，通过控制器190驱动电动机180，聚酰亚胺薄膜支撑机构170通过移动机构181沿Y1方向移动。聚酰亚胺薄膜支撑机构170移动到图30所示的***位置P1，以便聚酰亚胺薄膜171覆盖磁头IC芯片11。
按压和超声振荡步骤203(参见图31、26D和26E)
随着升降机构(未示出)的启动，粘结工具112如图26B所示向下移动。负载传感器114根据控制器132传来的控制信号工作，如图26D所示。如图31所示，降低的粘结工具112以预定的力F经由聚酰亚胺薄膜171按压磁头IC芯片11，由此而将金突点51压向金焊盘61。
如图26E所示，超声振荡器113根据控制器131传来的控制信号开始振荡，并保持振荡几秒钟。随着超声振荡器113振荡，粘结工具112沿图31所示的箭头B的方向超声振荡。粘结工具112的超声振荡经由聚酰亚胺薄膜171传送到磁头IC芯片11上的金突点51。金突点51进而对金焊盘61超声振荡。由此而将金突点51粘结到金焊盘61上。
不锈钢的粘结工具112和聚酰亚胺薄膜171之间的摩擦系数μ10在1到4的范围内，聚酰亚胺薄膜171和硅磁头IC芯片11之间的摩擦系数μ11也在1到4的范围内，这些摩擦系数μ10和μ11大于工具75和磁头IC芯片11之间的摩擦系数μ1。因此可以比现有技术更高效地从粘结工具112到磁头IC芯片11进行超声波传送，并且可以在比现有技术更短的时间周期内完成金突点51到金焊盘61的粘结。
粘结工具提升和聚酰亚胺薄膜支撑机构收回步骤204(参见图32，26B和26C)
随着图26B所示启动升降机构(未示出)，粘结工具112向上移动，如图32B所示。如图26C所示，通过控制器190驱动电动机180，通过移动机构181沿Y2方向移动聚酰亚胺薄膜支撑机构170。聚酰亚胺薄膜支撑机构170退回图32B所示的收回位置P2，且聚酰亚胺薄膜171从磁头IC芯片11收回，使磁头IC芯片11处于暴露状态。
加热步骤147
从芯片安装装置110F中取出其上粘结有磁头IC芯片11的悬杆12，并放置到加热炉内，如图4C所示。在加热炉中，热硬化整个粘合剂151。由此，完成图17A和17B所示的磁头滑动器组件19A。
粘合剂151变成底填料155。形成在磁头IC芯片11下表面上的金突点51粘结到悬杆12上的金焊盘61上。磁头IC芯片11通过紫外线固化和硬化热固性粘合剂150形成的底填料155粘结到悬杆12上。
聚酰亚胺薄膜供料步骤205(参见图33A、33B和26F)
如图26F所示，根据控制器191传送的信号驱动电动机175。如图33A和33B所示，卷绕辊176沿箭头E的方向卷起带型聚酰亚胺薄膜171。然后聚酰亚胺薄膜171沿X2方向从供料辊173中送出。带型聚酰亚胺薄膜171沿X2方向移动的长度等于磁头IC芯片11的每侧长度。由此，制备用于安装下一个磁头IC芯片的新聚酰亚胺薄膜。
按照以上方式，完成芯片安装装置100F的操作。在以上的工序中，按压超声振荡步骤203需要比现有技术更短的时间周期。因此，可以比现有技术实用性更高地制造磁头滑动器组件。
由于粘结工具112如图31所示经由聚酰亚胺薄膜171向磁头IC芯片11施加压力和超声振荡，故可以获得以下两个附带效果：
1.由于通过粘结工具112按压的聚酰亚胺薄膜171由合成树脂组成，因此由于粘结工具112端面的微小凹凸使聚酰亚胺薄膜171的上表面变形。由此，粘结工具112的端面牢固地粘附到聚酰亚胺薄膜171的上表面。因此，可以省却粘结工具112端面的定向。聚酰亚胺薄膜的下表面也牢固地粘附到磁头IC芯片11的上表面上。当粘结工具112超声振荡时，磁头IC芯片11由放置点返回到原始位置。因此在磁头IC芯片11的位置上不会发生偏离。
2.覆盖磁头IC芯片11上表面的聚酰亚胺薄膜171可防止粘合剂溢流到磁头IC芯片11的上表面上。
本发明的第五实施例解决了磁头IC芯片的偏离导致有缺陷安装的问题。
图34A到34D表示本发明第五实施例的磁头滑动器组件19G。和以上的实施例相同，磁头滑动器组件19G将磁头IC芯片11设置在悬杆12G上，且粘结工具112向磁头IC芯片11施加压力和超声振荡。由此，金突点51被粘结到悬杆12G上的金焊盘61G上，而且磁头IC芯片11通过硬化的底填料155粘结到悬杆12G上。
每个金焊盘61G在粘结工具112产生的超声振荡B方向(X1-X2方向)上有长度L20，在垂直于超声振荡B的方向上有长度L21。长度L20为长度L21的四倍。因此，每个金焊盘61G在超声振荡B的方向上伸长。
图34A和34B表示设置在悬杆12G上的磁头IC芯片11。每个金突点51接触每个对应的金焊盘61G的中心。由于粘结工具112的端面112a有小的取向，所以每当粘结工具112超声振荡时，在超声振荡的一个方向上(例如，在X1方向上)，磁头IC芯片11稍微偏离图34A和34B所示的原始位置。然而在由粘结工具112施加超声振荡B的方向上伸长的金焊盘61G，可以防止各金突点51偏离各金焊盘61G。由此，金突点51被正确地粘结到金焊盘61G上。
代替粘结工具112，可以使用图20到22所示的任何一种粘结工具112C、112D和112E。
如图35A到35H以及36A到36D所示制造长的金焊盘61G。
首先，如图35A和35B所示，铜箔211被粘结到由不锈钢制成的悬杆基底部件210的上表面，由此形成铜箔悬杆212。接下来，光刻胶膜213形成在铜箔悬杆212上，如图35C和D所示。具有与长的金焊盘61G相同形状的窗口214a的光掩模214设置在光刻胶膜213上，如图35E和35F所示。然后光源215曝光悬杆212，如图35G和35H所示，由此硬化光刻胶膜213。接下来，腐蚀光刻胶而留下光刻胶部分213a，如图36A和36B所示。也腐蚀铜箔211，如图36C和36D所示，并且除去光刻胶部分213a，如图36E和36F所示。由此，长的金焊盘61G便形成在悬杆基底部件210上。
本发明的第六实施例解决了与第五实施例相同的问题。
图37B表示本发明第六实施例的磁头滑动器组件19H。磁头滑动器组件19H包括磁头IC芯片11H。所述磁头IC芯片11H具有沿四个边设置的金突点51H。为了图示，用双点划线表示磁头IC芯片11H的轮廓和粘结工具112C的轮廓。如图37A所示，磁头滑动器组件19H将磁头IC芯片11H定位在悬杆12H上。然后粘结工具112向磁头IC芯片11H施加压力和超声振荡，以将金突点51H粘结到悬杆12H上的金焊盘61H上，且磁头IC芯片11H通过硬化的底填料(未示出)粘结到悬杆12H上。
与附着到磁头IC芯片11H上的金突点51H的结构一致，沿方形的四边设置悬杆12H上的金焊盘61H。每个金焊盘16H具有与图34A到34D所示金焊盘61G相同的形状。金突点51H在X1方向和Y1方向之间有一纵方向V1-V2，等效于轴线X1-X2逆时针旋转45度。按照这种布局，可以防止金突点51H之间相互干扰。此外，设计粘结工具112在V1-V2的方向上超声振荡。
由于粘结工具112端面的轻微取向，所以每当粘结工具112超声振荡时，在一个超声振荡方向上(例如，在V1方向上)磁头IC芯片11H稍微偏离图37A所示的初始位置。然而，金突点51H不会与金焊盘61H分离，并且留在金焊盘61G上。由此，金突点51H可被正确地粘结到金焊盘61H上。
代替粘结工具112，可以使用图20、21和22所示的任何一种粘结工具112C、112D和112E。
应该指出，本发明不仅适用于以上介绍的磁头滑动器组件，也适用于在图3所示的印制电路板单元30的多芯片组件36中，以将IC芯片31安装到基板32上。

Claims (2)

1.一种将半导体芯片安装到基板上的方法，包括以下步骤：
通过按压半导体芯片，利用置于半导体芯片和基板之间的绝缘粘合剂，将形成在半导体芯片上的突点粘结到基板上形成的焊盘上；
硬化在半导体芯片和基板之间扩展出的绝缘粘合剂，
其中硬化步骤包括以下步骤：
通过加热来硬化在半导体芯片和基板之间扩展出的绝缘粘合剂的周边部分；
通过加热来硬化全部绝缘粘合剂。
2.根据权利要求1的将半导体芯片安装到基板上的方法，
其中粘结步骤还包括向半导体芯片施加超声振荡的步骤，以将形成在半导体芯片上的突点粘结到基板上形成的焊盘上。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000339648A (ja) * 1999-05-24 2000-12-08 Tdk Corp 磁気ヘッド装置の製造方法
JP2002151551A (ja) * 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US6838316B2 (en) * 2002-03-06 2005-01-04 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method using ultrasonic flip chip bonding technique
TWI230102B (en) * 2002-03-27 2005-04-01 Matsushita Electric Ind Co Ltd Component mounting method, component mounting apparatus, and ultrasonic bonding head
DE10232636A1 (de) * 2002-07-18 2004-02-12 Delo Industrieklebstoffe Gmbh & Co. Kg Verfahren und Klebstoff zur Flip-Chip-Kontaktierung
US6855578B2 (en) * 2002-08-16 2005-02-15 Texas Instruments Incorporated Vibration-assisted method for underfilling flip-chip electronic devices
US7886430B2 (en) * 2002-12-13 2011-02-15 Hewlett-Packard Development Company, L.P. Method of installing circuit board component
JP2005026579A (ja) * 2003-07-04 2005-01-27 Fujitsu Ltd ハンダバンプ付き電子部品の実装方法およびこれに用いるフラックスフィル
JP2005033053A (ja) * 2003-07-08 2005-02-03 Lintec Corp 半導体装置の製造方法及び半導体装置
US8240539B2 (en) * 2004-05-28 2012-08-14 Panasonic Corporation Joining apparatus with UV cleaning
JP4644469B2 (ja) 2004-11-09 2011-03-02 富士通株式会社 半導体チップのフリップチップ実装方法およびその実装装置
JP5044984B2 (ja) * 2005-06-29 2012-10-10 大日本印刷株式会社 Ｉｃタグ、ｉｃタグの製造方法、およびｉｃタグの製造装置、並びに、インターポーザ、インターポーザの製造方法、およびインターポーザの製造装置
JP4902229B2 (ja) * 2006-03-07 2012-03-21 ソニーケミカル＆インフォメーションデバイス株式会社 実装方法
KR100873286B1 (ko) * 2006-12-29 2008-12-11 주식회사 실트론 실리콘 잉곳의 마운팅 장치 및 그 방법
US8253033B2 (en) * 2007-09-03 2012-08-28 Panasonic Corporation Circuit board with connection layer with fillet
US8020281B2 (en) * 2008-08-19 2011-09-20 Silverbrook Research Pty Ltd Printed circuit board bonding device
US8296933B2 (en) * 2008-08-19 2012-10-30 Zamtec Limited Fastening apparatus with authentication system
US8129220B2 (en) 2009-08-24 2012-03-06 Hong Kong Polytechnic University Method and system for bonding electrical devices using an electrically conductive adhesive
JP5699498B2 (ja) 2010-09-13 2015-04-08 富士通株式会社 振動子の作製方法、振動子作製用マスク、および振動子用パッケージ
JP6009743B2 (ja) * 2011-08-09 2016-10-19 積水化学工業株式会社 半導体パッケージの製造方法
EP3046717B1 (en) * 2013-09-17 2019-12-11 ABB Schweiz AG Method for ultrasonic welding with particles trapping
US9296188B1 (en) * 2015-02-17 2016-03-29 Hutchinson Technology Incorporated Partial curing of a microactuator mounting adhesive in a disk drive suspension
JP6688725B2 (ja) * 2016-12-26 2020-04-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10446521B2 (en) * 2017-11-07 2019-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating an integrated fan-out package
WO2019147640A1 (en) * 2018-01-25 2019-08-01 Kulicke And Soffa Industries, Inc. Bonding tools for bonding machines, bonding machines for bonding semiconductor elements, and related methods
KR102424347B1 (ko) 2018-11-06 2022-07-22 삼성전자주식회사 반도체 칩의 접착 방법
JP7283407B2 (ja) * 2020-02-04 2023-05-30 株式会社デンソー 電子装置
US11804467B2 (en) * 2020-06-25 2023-10-31 Micron Technology, Inc. Radiative heat collective bonder and gangbonder

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3700155A (en) * 1970-05-20 1972-10-24 Mech El Ind Inc Apparatus for improving alignment of beam leaded bonding tools
JPS59208844A (ja) 1983-05-13 1984-11-27 Hitachi Ltd フエイスダウンボンダ−
JP2662131B2 (ja) * 1991-12-26 1997-10-08 松下電器産業株式会社 ボンディング装置
JP2813507B2 (ja) * 1992-04-23 1998-10-22 三菱電機株式会社 ボンディング方法およびボンディング装置
DE69431023T2 (de) * 1993-09-01 2003-02-06 Toshiba Kawasaki Kk Halbleiteraufbau und Verfahren zur Herstellung
KR100438256B1 (ko) * 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
KR20000005272A (ko) 1996-04-08 2000-01-25 리차드 에스. 게라드 마이크로파 에너지를 이용한 마이크로전자 부품의액체수지 캡슐 경화방버뷰
US5926694A (en) * 1996-07-11 1999-07-20 Pfu Limited Semiconductor device and a manufacturing method thereof
JP2924830B2 (ja) * 1996-11-15 1999-07-26 日本電気株式会社 半導体装置及びその製造方法
KR19980070399A (ko) 1997-02-04 1998-10-26 존에이치.무어 플립칩 부착물
US6077382A (en) * 1997-05-09 2000-06-20 Citizen Watch Co., Ltd Mounting method of semiconductor chip
JPH1187413A (ja) 1997-09-08 1999-03-30 Fujitsu Ltd 半導体ベアチップ実装方法
JP2000068327A (ja) * 1998-08-20 2000-03-03 Matsushita Electric Ind Co Ltd 部品の実装方法と装置
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP2000306957A (ja) * 1999-04-21 2000-11-02 Tdk Corp 超音波ボンディング実装方法及び超音波ボンディング装置
JP2001266417A (ja) * 2000-03-17 2001-09-28 Sony Corp 転写方法

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