DE69431023T2 - Halbleiteraufbau und Verfahren zur Herstellung - Google Patents

Halbleiteraufbau und Verfahren zur Herstellung

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Publication number
DE69431023T2
DE69431023T2 DE69431023T DE69431023T DE69431023T2 DE 69431023 T2 DE69431023 T2 DE 69431023T2 DE 69431023 T DE69431023 T DE 69431023T DE 69431023 T DE69431023 T DE 69431023T DE 69431023 T2 DE69431023 T2 DE 69431023T2
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Germany
Prior art keywords
manufacturing
semiconductor structure
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69431023T
Other languages
English (en)
Other versions
DE69431023D1 (de
Inventor
Hiroshi Iwasaki
Hideo Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP21750393A external-priority patent/JP3234062B2/ja
Priority claimed from JP5075794A external-priority patent/JP3332555B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69431023D1 publication Critical patent/DE69431023D1/de
Publication of DE69431023T2 publication Critical patent/DE69431023T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15162—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
DE69431023T 1993-09-01 1994-08-23 Halbleiteraufbau und Verfahren zur Herstellung Expired - Lifetime DE69431023T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP21750393A JP3234062B2 (ja) 1993-09-01 1993-09-01 半導体パッケージおよびその製造方法
JP31863393 1993-12-17
JP5075794A JP3332555B2 (ja) 1993-12-17 1994-03-22 半導体装置およびその製造方法

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DE69431023T2 true DE69431023T2 (de) 2003-02-06

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EP (1) EP0644587B1 (de)
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KR0172203B1 (ko) 1999-02-01
US5866950A (en) 1999-02-02
KR950010035A (ko) 1995-04-26
EP0644587B1 (de) 2002-07-24
DE69431023D1 (de) 2002-08-29

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