CN110970485A - 载子注入控制快恢复二极管结构及制造方法 - Google Patents

载子注入控制快恢复二极管结构及制造方法 Download PDF

Info

Publication number
CN110970485A
CN110970485A CN201910677818.XA CN201910677818A CN110970485A CN 110970485 A CN110970485 A CN 110970485A CN 201910677818 A CN201910677818 A CN 201910677818A CN 110970485 A CN110970485 A CN 110970485A
Authority
CN
China
Prior art keywords
region
conductivity type
doped
trench
frd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910677818.XA
Other languages
English (en)
Inventor
H·伊尔马兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aidi Semiconductor Co Ltd
Ipower Semiconductor
Original Assignee
Aidi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aidi Semiconductor Co Ltd filed Critical Aidi Semiconductor Co Ltd
Publication of CN110970485A publication Critical patent/CN110970485A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请案涉及载子注入控制快恢复二极管结构及制造方法。提供半导体装置及制造方法。所述半导体装置包含通过降低载子存储控制电荷注入的电荷注入受控CIC快恢复二极管FRD。所述装置可具有第一导电性类型半导体衬底及漂移区域，所述漂移区域包含掺杂缓冲器区域、掺杂中间区域及掺杂场停止区域或载子存储区域。所述装置还可包含：第二导电性类型屏蔽区域，其包括环绕所述缓冲器区域(或在所述缓冲器区域下方基本上横向)的深结；及第二导电性类型浅结阳极区域，其与第二导电性类型阳极电极电接触。所述深结可具有环绕所述缓冲器区域的掺杂浓度范围以横向以及垂直地耗尽缓冲器电荷以防止过早装置击穿。所述第一导电性类型可为N型，且所述第二导电性类型可为P型。

Description

载子注入控制快恢复二极管结构及制造方法
相关申请案的交叉参考
本申请案主张2018年10月1日申请的序列号为62/739,820的美国临时申请案的权益。
技术领域
本发明大体上涉及功率半导体装置，且更明确来说，涉及快恢复二极管结构。
背景技术
可继续本段中描述的方法，但其不一定是先前构想或继续的方法。因此，除非另外指示，否则不应假设本段中描述的方法中的任何者仅凭借其包含于本段中而有资格作为现有技术。
每个绝缘栅极双极型晶体管(IGBT)需要跨其集电极及发射极端子的快恢复二极管(FRD)以处置电感开关类型应用(例如电动机控制)期间的电流传导。为了最小化FRD的开关损耗且降低其电路噪声，FRD应具有较短反向恢复时间、较低峰值反向恢复电流、较软恢复电流，且还应在摄氏150度到175度之间的结温度下操作。为了降低反向恢复峰值电流及缩短恢复时间，FRD的少数载子寿命可通过使用金、铂或电子束辐照来减少。
少数载子寿命减少存在一些缺点，包含更多电压尖峰及振荡会在FRD反向恢复期间生成；泄漏电流会在阻断阶段期间增加，尤其是在较高温度(例如摄氏150度及以上)下；且正向电压降(Vf)还会由于少数载子寿命减少而增加。
发明内容
提供此发明内容以引入呈简化形式的在下文具体实施方式中进一步描述的概念的选择。此发明内容不希望识别所主张标的物的关键或本质特征，也不希望用作确定所主张标的物的范围的辅助。
FRD结构的各种实施例通过降低载子存储且在一些实施例中减少阳极的紧邻处的少数载子寿命(而非减少N区域中的少数载子寿命以避免寿命减少的不利影响)而控制电荷注入。
在一些实施例中，提供一种用于制造电荷注入受控(CIC)快恢复二极管(FRD)的方法，所述方法包括：通过外延生长在重掺杂半导体衬底的顶部上形成第一导电性类型的漂移区域，所述漂移区域支持阻断高电压且包括所述漂移区域的所述顶部区域上的缓冲器区域、轻掺杂中间区域及中等掺杂电荷存储区域；在所述漂移区域中形成具有在从2到6微米的范围内的深度的沟槽；将第二导电性类型的掺杂剂离子植入到所述沟槽中以用于形成所述第二导电性类型的屏蔽区域，所述屏蔽区域包括在所述第一导电性类型的所述缓冲器区域下方基本上横向伸展的深结；用具有轻掺杂第二导电性类型杂质的多晶硅环绕所述第一导电性类型的所述缓冲器区域填充所述沟槽；在将所述沟槽中的所述多晶硅平坦化之后，离子植入所述第二导电性类型的掺杂剂以界定轻掺杂阳极；沉积掺杂硼的磷硅酸盐玻璃层(BPSG)或磷硅酸盐玻璃层(PSG)以用于界定接点；沉积多晶硅及用具有不同掺杂级的所述第二导电性类型掺杂剂离子植入以用于至少部分控制载子注入。
附图说明
在附图的图式中通过实例且非通过限制说明实施例，其中相似参考指示类似元件，且其中：
图1说明实例现有技术FRD结构。
图2A、图2B说明本发明的实例FRD结构的各种实施例。
图3展示实例FRD结构实施例，其可实现从阴极及阳极区域两者的电荷注入控制。
图4A到图4I展示用于产生CIC FRD结构的各种实施例的实例工艺流的方面。
图5A说明根据一些实施例的具有3um半间距的2D数值模拟的650V CIC FRD横截面。
图5B说明曲线图，例如图5A中的实例中的结构的2D模拟正向电流及电压特性。
图5C说明曲线图，例如图5A中的FRD结构的2D模拟击穿特性。
图5D说明曲线图，例如具有P+多晶Si阳极及N缓冲器的功能的图5A中的实例FRD结构的2D模拟归一化FRD正向浓度。
图6A说明具有填充P+多晶Si的沟槽作为阳极以控制载子注入的FRD结构的另一实施例。
图6B说明具有填充P+多晶Si的沟槽作为通过电介质侧壁间隔件横向隔离的阳极的FRD结构的另一实施例。
图6C说明使用耗尽诱发的势垒(DIB)FRD实现电压阻断的FRD结构的另一实例实施例。
图6D说明使用耗尽诱发的势垒实现电压阻断的另一实施例。
图7A及图7B展示根据各种实施例的CIC FRD的边缘终止结构。
图8A到图8H说明根据各种实施例的具有多晶硅填充的沟槽以控制少数载子寿命的FRD的4掩模工艺的各种步骤。
图8I说明根据实例实施例的具有P多晶硅填充的沟槽的混合肖特基(Schottky)及结FRD(HSJ FRD)。
图9展示具有包含具有针对各种FRD结构不同的掺杂浓度及厚度的片段的漂移区域的外延晶片横截面的实例。
图10A到图10F展示根据一些实施例的5掩模工艺的实例步骤。
具体实施方式
虽然本技术具有多不同形式的实施例，但在图中展示且将在本文中详细描述若干特定实施例，应理解，本发明应被视为本发明的原理的范例且不希望将本发明限于所说明的实施例。本文使用的术语是仅出于描述特定实施例的目的且不希望是本发明的限制。如本文使用，单数形式“一(a/an)”及“所述”希望同样也包含复数形式，除非上下文另外明确指示。应进一步理解，当术语“包括(comprises/comprising)”、及/或“包含(includes/including)”用于本说明书中时，指定存在所述特征、整数、步骤、操作、元件及/或组件，但不排除存在或添加一或多个其它特征、整数、步骤、操作、元件、组件及/或其群组。应理解，本文参考的相似或类似元件及/或组件可贯穿图式用相似参考字符识别。应进一步理解，若干图式仅是本发明的示意性表示。因而，为了使图像清晰起见，部分组件可从其实际尺度扭曲。
本发明涉及用于提供快恢复二极管结构以通过降低载子存储(而非减少少数载子寿命以避免寿命减少的不利影响)(在一些实施例中，除了阳极的紧邻处的局部少数载子寿命减少外)控制电荷注入的***及方法的各种实施例。
图1说明实例现有技术FRD结构100。在此实例中，结构100包含N+阴极、n型场停止或载子存储区域、支持阻断高电压的轻掺杂或本征区域及阳极区域的P+。电子辐照跨FRD均匀地缩减载子寿命，这会显著增加Vf同时加速FRD的反向恢复。为了改进FRD性能，还开发局部化寿命缩减技术，例如Au、Pt扩散、中子、He+及质子植入类型技术。
图2A、图2B及图3说明本发明的实例电荷注入控制(CIC)FRD结构的各种实施例。更明确来说，图2A展示实例多晶硅填充的沟槽类型FRD结构200。图2B更明确地说明氧化物填充的沟槽类型FRD结构210。图3展示识别为300的另一实例氧化物填充的沟槽类型FRD结构。FRD结构200、210及300可各自包含掺杂N缓冲器区域202(其在阳极侧处具有从1e17Cm-3到2e14Cm-3的浓度范围)、阳极侧上的P型结(而非P+)，且使用P+型掺杂多晶硅(图2A及2B中的204、图3中的304)作为从5e19 Cm-3到5e17 Cm-3的掺杂浓度范围的阳极。在各种实施例中，为了防止由于P-N结处的重N掺杂的低击穿电压，FRD结构包含具有在从1e18 Cm-3到1E15Cm-3范围内的掺杂浓度的更深P结，其环绕N缓冲器区域以将N缓冲器电荷横向且垂直地耗尽到较低电场且防止FRD的过早击穿。
对于分别具有图2A及图2B中的阳极电荷注入控制(CIC)结构200及210的FRD，空穴浓度的注入可通过N缓冲器及P结的掺杂浓度以及阳极的掺杂浓度调整。图2A展示包含P多晶硅填充的沟槽的实例P多晶硅阳极CIC FRD，其中在206处识别一个P多晶硅填充的沟槽。图2B展示具有氧化物填充的沟槽的实例P多晶硅阳极CIC FRD，其中在208处识别一个氧化物填充的沟槽。
图3展示实例FRD结构实施例，其可实现从阴极及阳极区域两者的电荷注入控制；针对较快二极管反向恢复时间及峰值电流，将P或P+多晶硅用于阳极以控制空穴注入水平及将具有在从5e18 Cm-3到1e20 Cm-3范围内的掺杂浓度的N+多晶硅或经溅镀N+硅用于阴极以控制电子注入水平而无需使用少数载子寿命缩短。图3展示具有含P多晶硅填充的沟槽(然而，沟槽可填充氧化物)的多晶硅或经溅镀N+硅阴极及阳极CIC FRD的实例实施例。
图4A到图4I展示产生CIC FRD结构的各种实施例的实例工艺流。
图4A说明针对实例多晶硅阴极CIC FRD，工艺包含(在400处识别)在N+衬底上以nn-nn外延(epi)起始晶片。
图4A1说明针对实例多晶硅阳极CIC FRD，工艺包含(在402处识别)在N+衬底上以n-nn epi起始晶片。
图4B说明根据各种实施例的实例掩模的工艺流的方面，所述工艺流包含：(在404处识别)针对n+nn-nn-晶片的深P结进行沟槽蚀刻；蚀刻2到3微米深及0.5到1微米宽的沟槽；包含高能量硼离子植入及驱动；及沉积氧化物及化学机械平坦化(CMP)氧化物以平坦化晶片表面。
图4B1说明根据各种实施例的实例掩模的工艺流的方面，所述工艺流包含：(在406处识别)针对n+nn-n-型晶片的深P结进行沟槽蚀刻；蚀刻2到3微米深及0.5到1微米宽的沟槽；包含高能量硼离子植入及驱动；沉积氧化物及CMP氧化物以平坦化晶片表面；及在无掩模的情况下进行高能量磷光体离子植入及驱动。
图4B2说明根据各种实施例的实例掩模的工艺流的方面，所述工艺流包含：(在408处识别)对深P结进行沟槽蚀刻；蚀刻2到3微米深及0.5到1微米宽的沟槽；包含高能量硼离子植入及驱动；沉积未掺杂多晶硅及蚀刻或CMP多晶硅以平坦化晶片表面；及在无掩模的情况下进行高能量磷光体离子植入及驱动。
图4C说明根据各种实施例的实例P阳极植入掩模的工艺流的方面，所述工艺流包含：(在410处识别)从终止区域阻断硼离子植入；及进行高能量硼离子植入及驱动。
图4D说明根据各种实施例的实例接点掩模的工艺流的方面，所述工艺流包含：(在412处识别)沉积掺杂硼的磷硅酸盐玻璃层(BPSG)或磷硅酸盐玻璃层(PSG)；使用掩模敞开阴极接点窗；沉积多晶硅及用硼掺杂(例如，离子植入剂量的范围从1e13 Cm-2到5e15 Cm-2)；及激活多晶硅中的硼。
图4E说明根据各种实施例的实例金属掩模的工艺流的方面，所述工艺流包含：(在414处识别)沉积具有或不具有钛/氮化钛(Ti/TiN)缓冲器金属的铝：硅：铜(Al：SI：Cu)合金；及使用此掩模蚀刻掉金属且接着蚀刻掉多晶硅。
图4F说明根据各种实施例的实例垫掩模的工艺流，所述工艺流包含：(在416处识别)沉积具有或不具有聚酰亚胺的钝化层；使用掩模从接合垫及切割道蚀刻掉包含聚酰亚胺的钝化层。
图4G说明根据各种实施例的工艺的方面，所述工艺包含：(在418处识别)针对在垫掩模之后的多晶硅阴极CIC FRD的阳极电极形成，研磨晶片，如果N+衬底及沉积背侧金属钛：镍：银(Ti：Ni：Ag)合金或金(Au)以形成阳极电极。在各种实施例中，执行烧结以完成晶片的制造。如所属领域中众所周知，烧结可包含进行合金化处理，例如，在氮环境中在扩散罐内部进行摄氏400度金属合金化处理步骤以避免金属表面氧化。
图4G1说明根据各种实施例的工艺的方面，所述工艺包含：(在420处识别)针对在垫掩模之后的多晶硅阴极CIC FRD的阴极电极形成，研磨晶片，如果N+衬底及沉积背侧金属Ti/Ni/Ag或金以形成阴极电极；及具有用未掺杂多晶硅填充沟槽的最终结构。
图4H说明根据各种实施例的工艺的方面，所述工艺包含：(在422处识别)针对在晶片减薄及背侧蚀刻之后的多晶硅阳极及阴极CIC FRD的阳极电极形成；沉积氧化物及从阳极接点的背侧蚀刻掉氧化物；沉积N+原位掺杂多晶Si及沉积背侧金属Ti/Ni/Ag或金以形成阳极电极。
图4I说明根据各种实施例的工艺的方面，所述工艺包含：(在424处识别)针对在晶片减薄及背侧蚀刻之后的多晶硅阳极及阴极CIC FRD的阴极电极形成；沉积N+原位掺杂多晶Si及沉积背侧金属Ti/Ni/Ag或Au(金)以形成阴极电极。
图5A以500说明包含根据一些实施例的具有3微米半间距的2D数值模拟的650VCIC FRD横截面502、504及506的曲线图。
图5B说明曲线图508，例如图5A中的实例中的结构的2D模拟正向电流及电压特性。
图5C说明曲线图510，例如图5A中的FRD结构的2D模拟击穿特性。
图5D以512说明包含曲线图514及516的曲线图，例如具有P+多晶Si阳极及N缓冲器的功能的图5A中的实例FRD结构的2D模拟归一化FRD正向浓度。
图6A说明具有填充P+多晶Si的沟槽作为阳极以控制载子注入的FRD结构的另一实例实施例600。
在各种实施例中，代替晶体硅使用多晶硅作为阳极会降低P+多晶硅阳极附近的少数载子寿命。
图6B说明具有填充P+多晶Si的沟槽作为通过电介质侧壁间隔件横向隔离的阳极的FRD结构的另一实例实施例602。在一些实施例中，形成侧壁间隔件包含：在沟槽内部沉积或热生长氧化物；及在填充沟槽之前从沟槽的底部反应离子蚀刻(RIE)蚀刻氧化物。
在各种实施例中，用P+多晶硅填充沟槽降低P+多晶硅及P阳极区域附近的少数载子寿命而不会增加FRD在高电压阻断模式期间的泄漏，这是因为耗尽不会延伸到高度有缺陷的多晶硅区域，这是受P屏蔽件(垂直地)及P阳极保护。
图6C说明使用耗尽诱发的势垒(DIB)FRD实现高电压阻断的FRD结构的另一实例实施例604。在此实例中，用P+多晶Si填充沟槽，因为阳极通过电介质侧壁间隔件横向隔离。实例实施例604使用填充P+多晶Si的沟槽作为阳极以注入电连接到阳极电极的空穴及n+区域。在跨阳极及阳极电极施加的零偏压电压下，针对此实例，在填充多晶Si的沟槽的底部处的P阳极之间存在n漂移区域。针对此实例中的此完全耗尽的方面，结构像增强模式JFET那样起作用，其中：耗尽区域在连接到阳极电极及阴极电极的表面处的n+区域之间创建诱发的势垒、耗尽诱发的势垒(DIB)以确保在反向偏置模式期间阻断高电压。根据此实例实施例，在正向偏压模式期间，多晶硅填充的沟槽的底部处的P阳极之间的耗尽宽度会缩减且JFET沟道接通从而允许来自阴极电极的电子将由连接到阳极电极的n+区域收集(除了注入到P阳极区域中的电极外)。在实例实施例中，一些电子远离P阳极转向n+区域的事实可最小化电子及空穴对(EHP)或仅P阳极区域的附近的电荷存储，这将减小FRD的反向恢复期间的时间及峰值电流。
即使图6C展示具有侧壁电介质间隔件的填充P+多晶Si的沟槽的实例，但DIB FRD可通过用沟槽侧壁上的角度植入P区域取代电介质侧壁间隔件以防止耗尽区域以达到P+多晶硅来构造，如图6D中展示。
图6D说明使用耗尽诱发的势垒实现电压阻断的另一实施例606。在此实例实施例中，填充有P+多晶Si的沟槽由P类型沟槽侧壁围封。
图7A及图7B分别展示根据各种实施例的CIC FRD的边缘终止结构700及702。
图8A到图8H说明根据各种实施例的控制少数载子寿命的具有多晶硅填充的沟槽的FRD的实例4掩模工艺800的各个步骤。图8A说明实例4掩模工艺包含：掩模1：沟槽掩模/P阳极植入；掩模2：接点掩模(氧化物沉积及接点开口)；掩模3：P+多晶硅/金属掩模；及掩模4：垫掩模(沉积SiO2/Si3N4及聚酰亚胺及垫开口)。
图8B说明实例掩模1，其是具有2到4微米深度及0.5到1.0微米宽沟槽的经由硬掩模(SiO2/Si3Ni4)的沟槽掩模(有源FRD区域)。在沟槽蚀刻之后，高能量硼可经植入以形成深P阳极。在此实例实施例中沟槽填充有未掺杂或p掺杂多晶Si且被平坦化，其中移除了沟槽硬掩模。
图8C说明实例掩模1：沟槽掩模(终止区域)。在此实例过程中，存在经由硬掩模(SiO2/Si3Ni4)形成的2到4微米深度及0.5到1.0微米宽沟槽；硼植入范围从1E12到2e13Cm-2的剂量，具有范围从30Kev高到2MeV的多个能量级以形成深P区域；角度植入以掺杂沟槽侧壁P类型。沟槽可填充有未掺杂或p掺杂多晶Si，以及平坦化及移除沟槽硬掩模。
图8D1展示图8A的实例掩模2，其是接点掩模(有源FRD区域)。在此实例中，此包含根据一些实施例沉积BPSG及界定接点区域。
图8D2展示根据替代性实施例的图8A的实例掩模2，其是接点掩模(有源FRD区域)。针对这些替代实施例，工艺包含：针对浅P阳极，沉积BPSG及界定接点区域，以及植入硼。
图8E展示根据一些实施例的是节点掩模(终止区域)的实例掩模2。针对图8E，工艺包含：沉积BPSG及界定接点区域。
图8F1说明根据一些实施例的是多晶硅/金属掩模(有源FRD区域)的图8A的实例掩模3。针对图8F1中的实例，工艺包含沉积多晶Si及植入硼作为阳极以控制空穴注入，加沉积金属及从经界定区域蚀刻掉金属及多晶Si。
图8F2展示有源FRD区域的替代性实施例的实例掩模3，多晶硅/金属掩模。针对图8F2中的实例，工艺包含沉积多晶Si及植入硼作为阳极以控制空穴注入，及沉积金属及从经界定区域蚀刻掉金属及多晶Si。
图8F3展示有源FRD区域的另一替代性实施例的另一实例掩模3，多晶硅/金属掩模。针对图8F3中的实例，工艺包含用多晶Si填充沟槽，在掩模1之后平坦化及植入硼作为阳极以控制空穴注入；沉积金属(Al：Si：Cu)及蚀刻掉金属。
图8G说明实例掩模3，多晶硅/金属掩模(终止区域)。针对图8G中的实例，工艺包含：沉积多晶Si及植入硼作为阳极，及沉积金属及从经界定区域蚀刻掉金属及多晶Si。
图8H说明根据一些实施例的图8A的掩模4，钝化掩模(终止区域)。针对图8H中的实例钝化掩模，工艺包含沉积多晶Si及植入硼作为阳极，及沉积金属及从经界定区域蚀刻掉金属及多晶Si。
图8I说明根据实例实施例的具有P多晶硅填充的沟槽的混合肖特基(Schottky)及结FRD(HSJ FRD)。针对图8I中的实例，根据各种实施例，工艺包含：在接点掩模在多晶硅填充的沟槽及n个缓冲器区域中敞开之后，植入在从1e11到5e12Cm-2的范围内的硼剂量以调整肖特基势垒高度；沉积Ti/TiN/W或Ti/Ni类型肖特基金属；沉积金属(Al：Si：Cu)及蚀刻掉金属，及4掩模工艺。
在各种实施例中，除了通过P+多晶Si阳极掺杂、N+多晶Si阴极及N缓冲器掺杂浓度控制空穴及电子注入外，局部化少数载子寿命降低可通过创建多晶硅填充的沟槽作为重新组合中心来实现。工艺流如在针对通过使用P多晶硅填充的沟槽类型的各种FRD结构降低的少数载子寿命的图8A到8H中的实例中展示。根据各种实施例，局部化较低少数载子寿命的益处的一者是减小阳极区域的附近的载子存储及加速FRD从接通状态到断开状态的反向恢复而不会增加高电压泄漏，这是因为耗尽不会延伸到具有降低的少数载子寿命的区域，换句话来说，多晶硅区域。
图9展示具有包含具有针对各种FRD结构不同的掺杂浓度及厚度的片段的漂移区域的外延晶片横截面的实例。根据实例实施例，横截面可包含：0.5到2微米厚的具有在1e14Cm-3到5e16Cm-3范围内的掺杂的N缓冲器区域；N缓冲器与N存储区域之间的N漂移区域，含有具有从上部朝向N+衬底增加的掺杂级的两个或两个以上子区域。
图10A到图10F展示5掩模工艺的实例步骤。根据各种实施例，此实例5掩模工艺具有FRD，其具有P+多晶Si填充的沟槽及形成于有源FRD区域中的N缓冲器区域但使其免于高电压终止区域以确保FRD击穿发生于有源区域内，而非发生于高电压终止中。
图10A中的实例的5掩模工艺包含：掩模1：N缓冲器掩模；掩模2：沟槽掩模/P阳极植入；掩模3：接点掩模；掩模4：金属掩模；及掩模5：垫掩模。
图10B说明根据各种实施例的5掩模工艺的掩模1的工艺的方面。在图10B中的实例中，N缓冲器经由掩模1植入以阻断终止区域；通过磷光体植入具有2到4微米厚的具有从1e14Cm-3到5e16Cm-3范围内的掺杂的N缓冲器区域。
图10C说明根据各种实施例的5掩模工艺的掩模2的工艺的方面。在图10C中的实例中，掩模2是沟槽掩模(有源FRD区域)。针对图10C中的实例掩模2，工艺包含经由硬掩模(SiO2/Si3Ni4)形成2到4微米深度及0.5到1.0微米宽的沟槽；在沟槽蚀刻之后，植入高能量硼以形成深P阳极；及用掺杂多晶Si掺杂沟槽及平坦化及移除沟槽硬掩模。
图10D说明根据各种实施例的5掩模工艺的掩模3的工艺的方面。在图10D中的实例中，掩模3是接点掩模(有源FRD区域)。针对图10D中的实例掩模3，根据各种实施例，工艺包含沉积0.4到1.0微米厚BPSG；在沟槽蚀刻之后，植入高能量硼以形成深P阳极；经由掩模3界定接点开口；及在接点掩模、金属及垫工艺步骤完成之后进行这些步骤。
图10E说明根据各种实施例的5掩模工艺的掩模4的工艺的方面。在图10E中的实例中，掩模4是金属掩模(有源FRD区域)。针对图10E中的实例掩模4，工艺包含沉积0.4到1.0微米厚的BPSG；在沟槽蚀刻之后，植入高能量硼以形成深P阳极；经由掩模3界定接点开口；及在接点掩模、金属及垫工艺步骤完成之后进行这些步骤。
图10F说明根据各种实施例的5掩模工艺的掩模5的工艺的方面。在图10F中的实例中，掩模5是垫掩模(HV终止区域)。针对图10F中的实例掩模5，工艺包含沉积0.5到1.0微米厚的SiO2/Si3N4及5到10微米厚的聚酰亚胺作为钝化层；经由掩模5界定垫；其中根据各种实施例终止将具有更多的浮动场环。
出于说明及描述的目的，呈现本发明的描述，但其不希望是详尽的或限于呈所揭示形式的本发明。所属领域的一般技术人员应明白未背离本发明的范围及精神的许多修改及变化。选定及描述示范性实施例以便最好地解释本发明的原理及其实际应用，且使所属领域的一般技术人员能够理解适合预期的特定用途的本发明的各种实施例的各种修改。

Claims (23)

1.一种半导体装置，其包括：
第一导电性类型半导体衬底；
漂移区域，其形成在所述第一导电性类型半导体衬底的顶部上以支持阻断高电压，所述漂移区域是第一导电性类型，所述漂移区域包括：
顶部上的中等掺杂缓冲器区域，
轻掺杂中间区域，及
中等掺杂场停止区域或载子存储区域；
第二导电性类型的屏蔽区域，所述屏蔽区域包括环绕所述漂移区域的所述中等掺杂缓冲器区域的深结；及
第二导电性类型浅结阳极区域，其与所述第二导电性类型的阳极电极电接触。
2.根据权利要求1所述的半导体装置，其中所述半导体装置是电荷注入控制CIC快恢复二极管FRD，其用于通过降低载子存储而非减少少数载子寿命控制电荷注入。
3.根据权利要求1所述的半导体装置，其中所述屏蔽区域进一步包括所述第二导电性类型的多晶硅，所述深结及所述第二导电性类型多晶硅环绕所述中等掺杂缓冲器区域。
4.根据权利要求1所述的半导体装置，其中所述屏蔽区域进一步包括氧化物填充的沟槽，所述深结及所述氧化物填充的沟槽环绕所述中等掺杂缓冲器区域。
5.根据权利要求1所述的半导体装置，其进一步包括深屏蔽结，所述深屏蔽结在所述第一导电性类型缓冲器区域下方基本上横向伸展。
6.根据权利要求1所述的半导体装置，其中：
所述中等掺杂缓冲器区域具有在从1e17 Cm-3到2e14 Cm-3范围内的掺杂浓度；
所述轻掺杂中间区域具有在从1e13 Cm-3到5e14 Cm-3范围内的掺杂浓度；且
所述中等掺杂场停止区域或载子存储区域具有在从1e17 Cm-3到2e14 Cm-3范围内的掺杂浓度。
7.根据权利要求1所述的半导体装置，其进一步包括小于所述第二导电性类型浅结阳极区域的阳极接点，所述阳极接点用于连接到所述阳极电极，所述阳极电极是第二导电性类型重掺杂多晶硅阳极电极。
8.根据权利要求1所述的半导体装置，其进一步包括用于连接到所述阳极电极的阳极接点，所述阳极接点的大小基本上等于所述第二导电性类型浅结阳极区域。
9.根据权利要求1所述的半导体装置，其进一步包括与所述第一导电性衬底电接触的阴极电极。
10.根据权利要求1所述的半导体装置，其中所述第一导电性类型是N型，且所述第二导电性类型是P型。
11.根据权利要求1所述的半导体装置，其中所述漂移区域的所述轻掺杂中间区域包含针对各种FRD结构具有不同掺杂浓度及厚度的片段。
12.一种具有顶部表面及底部表面的半导体装置，其包括：
第一导电性类型的漂移区域，所述漂移区域包括所述顶部处的缓冲器区域、轻掺杂中间区域及中等掺杂电荷存储区域，所述漂移区域用于阻断电压且形成在所述第一导电性类型的半导体衬底的顶部上；
第二导电性类型的屏蔽区域，所述屏蔽区域包括所述第二导电性类型的多晶硅填充的沟槽，所述多晶硅填充的沟槽在环绕所述漂移区域的所述缓冲器部分的深结的顶部上，所述深结在所述缓冲器区域下方基本上横向伸展；
所述第二导电性类型多晶硅的阳极区域，其与阳极电极电接触；及
所述第一导电性类型的衬底，其与阴极电极电接触。
13.根据权利要求12所述的半导体装置，
其中所述第二导电性类型的所述多晶硅填充的沟槽在环绕所述缓冲器区域的所述深结的顶部及所述漂移区域的上部上，且
其中所述第二导电性类型的所述多晶硅填充的沟槽与所述阳极电极电接触。
14.一种用于通过降低载子存储控制电荷注入的电荷注入控制CIC快恢复二极管FRD半导体装置，所述CIC FRD半导体装置具有顶部表面及底部表面及有源FRD区域，所述CIC FRD半导体装置包括：
漂移区域，其支持阻断高电压，所述漂移区域是第一导电性类型，所述漂移区域包括：
缓冲器区域，其在仅具有所述有源FRD区域的中等掺杂的顶部上，
轻掺杂中间区域，及
中等掺杂电荷存储区域，所述漂移区域形成在第一导电性类型的半导体衬底的顶部上；
第二导电性类型的屏蔽区域，所述屏蔽区域包括环绕所述缓冲器区域深结的顶部及所述漂移区域的所述上部上的所述第二导电性类型的所述深结及多晶硅填充的沟槽，所述屏蔽区域的所述深结在所述缓冲器区域下方基本上横向伸展；
所述第二导电性类型的多晶硅填充的沟槽，其与阳极电极电接触；
高电压终止区域，其环绕所述有源FRD区，所述高电压终止区域包括所述第二导电性类型屏蔽区域的顶部上的额外多晶硅填充的沟槽的多个浮动环，增加与除了中等掺杂缓冲器区域外的所述缓冲器区域的间隔；及
所述第一导电性类型的衬底，其与阴极电极接触；且
所述CIC FRD半导体装置用于通过降低载子存储而非减少少数载子寿命控制电荷注入；
其中所述第一导电性类型是N型，且所述第二导电性类型是P型。
15.根据权利要求14所述的电荷注入控制CIC快恢复二极管FRD半导体装置，其进一步包括电介质间隔件，所述电介质间隔件横向隔离所述多晶硅填充的沟槽。
16.一种具有顶部表面及底部表面的半导体装置，其包括：
第一导电性类型的漂移区域，所述漂移区域包括：
缓冲器区域，其在顶部上，
轻掺杂中间区域，及
中等掺杂电荷存储区域，所述漂移区域用于阻断电压且形成在所述第一导电性类型的半导体衬底的顶部上；
第二导电性类型的屏蔽区域，所述屏蔽区域包括环绕所述缓冲器区域的深结的顶部上的所述第二导电性类型的所述深结及多晶硅填充的沟槽，所述深结在所述缓冲器区域下方基本上横向伸展；
肖特基接点，其形成在在两个或所有侧上由屏蔽区域环绕的所述缓冲器区域的所述表面上以用于形成混合肖特基及结快恢复二极管HSJ FRD，
所述第二导电性类型多晶硅的阳极区域，其与阳极电极电接触；及
所述第一导电性类型的衬底，其与阴极电极电接触；
其中所述第一导电性类型是N型，且所述第二导电性类型是P型。
17.一种制造电荷注入受控CIC快恢复二极管FRD的方法，所述方法包括：
通过外延生长在重掺杂半导体衬底的顶部上形成第一导电性类型的漂移区域，所述漂移区域支持阻断高电压且包括所述漂移区域的所述顶部区域上的缓冲器区域、轻掺杂中间区域及中等掺杂电荷存储区域；
在所述漂移区域中形成具有在从2到6微米范围内的深度的沟槽；
将第二导电性类型的掺杂剂离子植入到所述沟槽中以用于形成所述第二导电性类型的屏蔽区域，所述屏蔽区域包括在所述第一导电性类型的所述缓冲器区域下方基本上横向伸展的深结；
用具有轻掺杂第二导电性类型杂质的多晶硅环绕所述第一导电性类型的所述缓冲器区域填充所述沟槽；
在将所述沟槽中的所述多晶硅平坦化之后，离子植入所述第二导电性类型的掺杂剂以界定轻掺杂阳极；
沉积掺杂硼的磷硅酸盐玻璃层BPSG或磷硅酸盐玻璃层PSG以用于界定接点；
沉积多晶硅及用具有不同掺杂级的所述第二导电性类型掺杂剂离子植入以用于至少部分控制载子注入。
18.一种制造电荷注入受控CIC快恢复二极管FRD的方法，所述方法包括：
通过外延生长在重掺杂半导体衬底的顶部上形成第一导电性类型的漂移区域，所述漂移区域支持阻断高电压且包括：
所述漂移区域的所述顶部区域上的中等掺杂缓冲器区域，
轻掺杂中间区域，及
中等掺杂场停止区域；
在所述漂移区域中形成具有在从2到6微米范围内的深度的沟槽；
将第二导电性类型的掺杂剂离子植入到所述沟槽中以用于形成所述第二导电性类型的屏蔽区域，所述屏蔽区域包括在所述轻掺杂中间区域中基本上横向扩展的深结；
用环绕所述漂移区域的中等掺杂缓冲器区域的电介质层填充沟槽；
形成所述第二导电性类型的浅且轻掺杂结阳极区域；
在沉积及界定接点区域之后，沉积通过离子植入掺杂的多晶硅层作为所述第二导电性类型的阳极；
沉积前侧金属及钝化层；及
研磨FRD晶片背侧及蚀刻以减薄所述晶片及沉积背侧金属钛:镍:银Ti:Ni:Ag合金或金Au以形成至少一阳极电极；
其中所述第一导电性类型是N型，且所述第二导电性类型是P型。
19.一种制造电荷注入受控CIC快恢复二极管FRD的方法，所述方法包括：
在轻掺杂半导体衬底的顶部上形成第一导电性类型的漂移区域，所述漂移区域支持阻断高电压且包括：
所述漂移区域的所述顶部区域上的缓冲器区域，
轻掺杂中间区域，及
中等掺杂场停止区域；
在所述漂移区域中形成具有在从2到6微米范围内的深度的沟槽；
将第二导电性类型的掺杂剂离子植入到所述沟槽中以用于形成所述第二导电性类型的屏蔽区域，所述屏蔽区域包括在所述轻掺杂中间区域中基本上横向扩展的深结；
填充沟槽；
形成所述第二导电性类型的浅结阳极区域；
在沉积及界定接点区域之后，沉积通过离子植入掺杂的多晶硅层作为所述第二导电性类型的阳极；
沉积前侧金属及钝化层；
研磨FRD晶片背侧及蚀刻以将所述晶片向下减薄到经预先确定的厚度；
将N+硅或N+多晶Si作为阴极溅镀到所述晶片背侧的完整或特定部分，将电介质层沉积到所述晶片背侧，其中在所述N+硅或N+多晶Si的所述溅镀之前阴极接点经由掩模断开；及
将金属Ti:Ni:Ag或Au沉积到所述晶片背侧及进行烧结以用于完成用于所述FRD的所述晶片的制造；
其中所述第一导电性类型是N型，且所述第二导电性类型是P型。
20.根据权利要求19所述的方法，
其中所述漂移区域的所述缓冲器区域经中等掺杂；且
其中所述沟槽用所述第二导电性类型多晶硅环绕所述中等掺杂缓冲器区域填充。
21.根据权利要求19所述的方法，
其中所述漂移区域的所述缓冲器区域经高级掺杂；且
其中所述沟槽用电介质(SiO2)及CMP电介质层填充以平坦化环绕所述缓冲器区域的所述晶片的表面。
22.一种制造电荷注入受控CIC快恢复二极管FRD的方法，所述方法包括：
通过外延生长在重掺杂半导体衬底的顶部上形成第一导电性类型的漂移区域，所述漂移区域支持阻断高电压且包括：
所述漂移区域的所述顶部区域上的中等掺杂缓冲器区域，
轻掺杂中间区域，及
中等掺杂场停止区域；
在所述漂移区域中形成具有在从2到6微米范围内的深度的沟槽；
将第二导电性类型的掺杂剂离子植入到所述沟槽中以用于形成所述第二导电性类型的屏蔽区域，所述屏蔽区域包括在所述轻掺杂中间区域中基本上横向扩展的深结；
用通过离子植入形成的所述第二导电性类型的多晶硅环绕所述中等掺杂缓冲器区域的两个或所有侧填充沟槽；
与所述第二导电性类型多晶硅电接触的阳极电极填充所述沟槽；
改变填充所述沟槽的所述多晶硅的所述掺杂浓度以至少部分控制所述载子注入及所述FRD的所得反向恢复时间；
沉积BPSG或PSG以用于界定接点区域；
沉积金属及钝化层；及
研磨FRD晶片背侧及蚀刻以将所述晶片向下减薄到经预先确定的厚度及沉积背侧金属Ti:Ni:Ag合金或Au。
23.根据权利要求22所述的方法，其进一步包括形成侧壁间隔物，所述形成包含在所述沟槽内部沉积或热生长氧化物，在填充所述沟槽之前从所述沟槽的所述底部反应离子蚀刻RIE蚀刻所述氧化物。
CN201910677818.XA 2018-10-01 2019-07-25 载子注入控制快恢复二极管结构及制造方法 Pending CN110970485A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862739820P 2018-10-01 2018-10-01
US62/739,820 2018-10-01
US16/450,351 US11069770B2 (en) 2018-10-01 2019-06-24 Carrier injection control fast recovery diode structures
US16/450,351 2019-06-24

Publications (1)

Publication Number Publication Date
CN110970485A true CN110970485A (zh) 2020-04-07

Family

ID=69946161

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910677818.XA Pending CN110970485A (zh) 2018-10-01 2019-07-25 载子注入控制快恢复二极管结构及制造方法

Country Status (2)

Country Link
US (2) US11069770B2 (zh)
CN (1) CN110970485A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069770B2 (en) 2018-10-01 2021-07-20 Ipower Semiconductor Carrier injection control fast recovery diode structures
CN113555416A (zh) * 2021-09-22 2021-10-26 四川上特科技有限公司 一种功率二极管器件
CN115117149A (zh) * 2022-08-23 2022-09-27 深圳芯能半导体技术有限公司 一种基于湿法刻蚀工艺的快恢复二极管及其制备方法
CN115295613A (zh) * 2022-10-08 2022-11-04 烟台台芯电子科技有限公司 一种快恢复二极管结构及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115148787B (zh) * 2022-06-30 2023-09-22 扬州国宇电子有限公司 一种抗单粒子烧毁效应的快恢复二极管芯片及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679966A (en) * 1995-10-05 1997-10-21 North Carolina State University Depleted base transistor with high forward voltage blocking capability
JP2000323488A (ja) * 1999-05-10 2000-11-24 Fuji Electric Co Ltd ダイオードおよびその製造方法
JP2012182463A (ja) * 2005-07-27 2012-09-20 Infineon Technologies Austria Ag ドリフト領域とドリフト制御領域とを有する半導体素子
US20140027841A1 (en) * 2012-07-30 2014-01-30 Alpha And Omega Semiconductor Incorporated High voltage field balance metal oxide field effect transistor (fbm)
US20150162432A1 (en) * 2013-02-13 2015-06-11 Fuji Electric Co., Ltd. Semiconductor device
US20150364584A1 (en) * 2014-06-12 2015-12-17 Cree, Inc. Igbt with bidirectional conduction
US20170213908A1 (en) * 2014-07-25 2017-07-27 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same

Family Cites Families (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426541B2 (en) * 2000-07-20 2002-07-30 Apd Semiconductor, Inc. Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication
JP2005340626A (ja) * 2004-05-28 2005-12-08 Toshiba Corp 半導体装置
JP4414863B2 (ja) * 2004-10-29 2010-02-10 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
US20070004116A1 (en) * 2005-06-06 2007-01-04 M-Mos Semiconductor Sdn. Bhd. Trenched MOSFET termination with tungsten plug structures
US7323389B2 (en) * 2005-07-27 2008-01-29 Freescale Semiconductor, Inc. Method of forming a FINFET structure
US7687851B2 (en) * 2005-11-23 2010-03-30 M-Mos Semiconductor Sdn. Bhd. High density trench MOSFET with reduced on-resistance
US9368614B2 (en) * 2008-08-20 2016-06-14 Alpha And Omega Semiconductor Incorporated Flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure
JP4453671B2 (ja) * 2006-03-08 2010-04-21 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
US7633120B2 (en) * 2006-08-08 2009-12-15 Alph & Omega Semiconductor, Ltd. Inverted-trench grounded-source field effect transistor (FET) structure using highly conductive substrates
TW200903806A (en) * 2007-07-11 2009-01-16 Promos Technologies Inc Power MOSFET structure and manufacturing method for the same
CN102318045B (zh) * 2008-02-14 2014-08-06 马克斯半导体股份有限公司 改良式击穿电压的边缘端点
JP2011512677A (ja) * 2008-02-14 2011-04-21 マックスパワー・セミコンダクター・インコーポレイテッド 半導体素子構造及び関連プロセス
US8704295B1 (en) * 2008-02-14 2014-04-22 Maxpower Semiconductor, Inc. Schottky and MOSFET+Schottky structures, devices, and methods
US7893488B2 (en) * 2008-08-20 2011-02-22 Alpha & Omega Semiconductor, Inc. Charged balanced devices with shielded gate trench
US8022474B2 (en) * 2008-09-30 2011-09-20 Infineon Technologies Austria Ag Semiconductor device
US8653589B2 (en) * 2009-04-15 2014-02-18 Force Mos Technology Co., Ltd. Low Qgd trench MOSFET integrated with schottky rectifier
US8492773B2 (en) * 2010-04-23 2013-07-23 Intersil Americas Inc. Power devices with integrated protection devices: structures and methods
US9111769B2 (en) * 2011-05-18 2015-08-18 Rohm Co., Ltd. Semiconductor device and method for producing same
US8680607B2 (en) * 2011-06-20 2014-03-25 Maxpower Semiconductor, Inc. Trench gated power device with multiple trench width and its fabrication process
US8916951B2 (en) * 2011-09-23 2014-12-23 Alpha And Omega Semiconductor Incorporated Lateral PNP bipolar transistor formed with multiple epitaxial layers
US20130113038A1 (en) * 2011-11-08 2013-05-09 Feei Cherng Enterprise Co., Ltd. Trench mosfet with split trenched gate structures in cell corners for gate charge reduction
US9082914B2 (en) * 2012-01-13 2015-07-14 Gaurdian Industries Corp. Photovoltaic module including high contact angle coating on one or more outer surfaces thereof, and/or methods of making the same
US8785278B2 (en) * 2012-02-02 2014-07-22 Alpha And Omega Semiconductor Incorporated Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
DE112013001487T5 (de) * 2012-03-16 2014-12-04 Fuji Electric Co., Ltd. Halbleitervorrichtung
US9299819B2 (en) * 2012-03-28 2016-03-29 Infineon Technologies Americas Corp. Deep gate trench IGBT
US9018701B2 (en) * 2012-08-14 2015-04-28 Force Mos Technology Co., Ltd. Avalanche capability improvement in power semiconductor devices using three masks process
WO2014122919A1 (ja) * 2013-02-05 2014-08-14 三菱電機株式会社 絶縁ゲート型炭化珪素半導体装置及びその製造方法
US9105494B2 (en) * 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
CN105493291A (zh) * 2013-06-06 2016-04-13 美国联合碳化硅公司 沟槽屏蔽连接结型场效应晶体管
US9099320B2 (en) * 2013-09-19 2015-08-04 Force Mos Technology Co., Ltd. Super-junction structures having implanted regions surrounding an N epitaxial layer in deep trench
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
US9093522B1 (en) * 2014-02-04 2015-07-28 Maxpower Semiconductor, Inc. Vertical power MOSFET with planar channel and vertical field plate
US9184248B2 (en) * 2014-02-04 2015-11-10 Maxpower Semiconductor Inc. Vertical power MOSFET having planar channel and its method of fabrication
US9761702B2 (en) * 2014-02-04 2017-09-12 MaxPower Semiconductor Power MOSFET having planar channel, vertical current path, and top drain electrode
GB2530284A (en) * 2014-09-17 2016-03-23 Anvil Semiconductors Ltd High voltage semiconductor devices
DE102015103067B3 (de) * 2015-03-03 2016-09-01 Infineon Technologies Ag Halbleitervorrichtung mit trenchgatestrukturen in einem halbleiterkörper mit hexagonalem kristallgitter
US9929260B2 (en) * 2015-05-15 2018-03-27 Fuji Electric Co., Ltd. IGBT semiconductor device
JP6472714B2 (ja) * 2015-06-03 2019-02-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6633867B2 (ja) * 2015-08-21 2020-01-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE112016003510B4 (de) * 2015-10-16 2023-11-16 Fuji Electric Co., Ltd. HALBLEITERVORRlCHTUNG UND VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG
US9825128B2 (en) * 2015-10-20 2017-11-21 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings
JP6759563B2 (ja) * 2015-11-16 2020-09-23 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2017099096A1 (ja) * 2015-12-11 2017-06-15 富士電機株式会社 半導体装置
US10164078B2 (en) * 2016-03-18 2018-12-25 Infineon Technologies Americas Corp. Bipolar semiconductor device with multi-trench enhancement regions
US20180366569A1 (en) * 2016-06-10 2018-12-20 Maxpower Semiconductor Inc. Trench-Gated Heterostructure and Double-Heterostructure Active Devices
US20180358449A1 (en) * 2017-06-12 2018-12-13 Maxpower Semiconductor Inc. Fabrication of Trench-Gated Wide-Bandgap Devices
JP6617657B2 (ja) * 2016-07-29 2019-12-11 富士電機株式会社 炭化ケイ素半導体装置および炭化ケイ素半導体装置の製造方法
WO2018030444A1 (ja) * 2016-08-12 2018-02-15 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6805655B2 (ja) * 2016-09-07 2020-12-23 富士電機株式会社 半導体装置
JP7182850B2 (ja) * 2016-11-16 2022-12-05 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP6648838B2 (ja) * 2016-11-17 2020-02-14 富士電機株式会社 半導体装置
JP6855793B2 (ja) * 2016-12-28 2021-04-07 富士電機株式会社 半導体装置
JP7201336B2 (ja) * 2017-05-17 2023-01-10 ローム株式会社 半導体装置
JP6871058B2 (ja) * 2017-05-22 2021-05-12 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
WO2018220879A1 (ja) * 2017-05-31 2018-12-06 富士電機株式会社 半導体装置
JP6958011B2 (ja) * 2017-06-15 2021-11-02 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6958093B2 (ja) * 2017-08-09 2021-11-02 富士電機株式会社 半導体装置
JP6926869B2 (ja) * 2017-09-13 2021-08-25 富士電機株式会社 半導体装置
JP6992388B2 (ja) * 2017-10-05 2022-01-13 富士電機株式会社 半導体装置
JP7067021B2 (ja) * 2017-11-07 2022-05-16 富士電機株式会社 絶縁ゲート型半導体装置及びその製造方法
JP6925250B2 (ja) * 2017-12-08 2021-08-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP7006280B2 (ja) * 2018-01-09 2022-01-24 富士電機株式会社 半導体装置
CN110419111B (zh) * 2018-01-16 2023-08-15 艾鲍尔半导体 自对准且稳健的绝缘栅双极晶体管器件
CN111602250B (zh) * 2018-02-07 2023-08-11 艾鲍尔半导体 具有用于场截止和反向传导的三维背侧结构的igbt器件
JP6947281B2 (ja) * 2018-02-14 2021-10-13 富士電機株式会社 半導体装置
US10777661B2 (en) * 2018-03-01 2020-09-15 Ipower Semiconductor Method of manufacturing shielded gate trench MOSFET devices
CN111727491B (zh) * 2018-03-01 2022-06-07 艾鲍尔半导体 自对准沟槽mosfet的结构和方法
US10937901B2 (en) * 2018-03-14 2021-03-02 Fuji Electric Co., Ltd. Insulated gate semiconductor device with injuction supression structure and method of manufacturing same
US10714574B2 (en) * 2018-05-08 2020-07-14 Ipower Semiconductor Shielded trench devices
JP7135445B2 (ja) * 2018-05-29 2022-09-13 富士電機株式会社 半導体装置
JP7259215B2 (ja) * 2018-06-01 2023-04-18 富士電機株式会社 絶縁ゲート型半導体装置及び絶縁ゲート型半導体装置の製造方法
US10680095B2 (en) * 2018-06-15 2020-06-09 Semiconductor Components Industries, Llc Power device having super junction and schottky diode
JP7172216B2 (ja) * 2018-07-13 2022-11-16 富士電機株式会社 半導体装置および半導体回路装置
US11069770B2 (en) 2018-10-01 2021-07-20 Ipower Semiconductor Carrier injection control fast recovery diode structures

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679966A (en) * 1995-10-05 1997-10-21 North Carolina State University Depleted base transistor with high forward voltage blocking capability
JP2000323488A (ja) * 1999-05-10 2000-11-24 Fuji Electric Co Ltd ダイオードおよびその製造方法
JP2012182463A (ja) * 2005-07-27 2012-09-20 Infineon Technologies Austria Ag ドリフト領域とドリフト制御領域とを有する半導体素子
US20140027841A1 (en) * 2012-07-30 2014-01-30 Alpha And Omega Semiconductor Incorporated High voltage field balance metal oxide field effect transistor (fbm)
US20150162432A1 (en) * 2013-02-13 2015-06-11 Fuji Electric Co., Ltd. Semiconductor device
US20150364584A1 (en) * 2014-06-12 2015-12-17 Cree, Inc. Igbt with bidirectional conduction
US20170213908A1 (en) * 2014-07-25 2017-07-27 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069770B2 (en) 2018-10-01 2021-07-20 Ipower Semiconductor Carrier injection control fast recovery diode structures
CN113555416A (zh) * 2021-09-22 2021-10-26 四川上特科技有限公司 一种功率二极管器件
CN113555416B (zh) * 2021-09-22 2021-12-31 四川上特科技有限公司 一种功率二极管器件
CN115117149A (zh) * 2022-08-23 2022-09-27 深圳芯能半导体技术有限公司 一种基于湿法刻蚀工艺的快恢复二极管及其制备方法
CN115117149B (zh) * 2022-08-23 2022-11-29 深圳芯能半导体技术有限公司 一种基于湿法刻蚀工艺的快恢复二极管及其制备方法
CN115295613A (zh) * 2022-10-08 2022-11-04 烟台台芯电子科技有限公司 一种快恢复二极管结构及其制造方法

Also Published As

Publication number Publication date
US20200105866A1 (en) 2020-04-02
US11069770B2 (en) 2021-07-20
US20220013627A1 (en) 2022-01-13

Similar Documents

Publication Publication Date Title
US11837629B2 (en) Power semiconductor devices having gate trenches and buried edge terminations and related methods
TWI566422B (zh) 改良之蕭基整流器
US9653568B2 (en) Method of manufacturing an insulated gate bipolar transistor with mesa sections between cell trench structures
US11069770B2 (en) Carrier injection control fast recovery diode structures
JP5439763B2 (ja) 半導体装置および半導体装置の製造方法
US20210057557A1 (en) Igbt devices with 3d backside structures for field stop and reverse conduction
US20080246055A1 (en) Semiconductor component including a monocrystalline semiconductor body and method
EP2920816B1 (en) Method of manufacturing trench-based schottky diode with improved trench protection
CN110970491B (zh) 场终止绝缘栅双极型晶体管中的背侧掺杂激活
WO2005065140A2 (en) Method of manufacturing a superjunction device with conventional terminations
US8264036B2 (en) Power semiconductor device with low on-state voltage and method of manufacturing the same
US9929285B2 (en) Super-junction schottky diode
CN215527729U (zh) 功率器件
CN107591454B (zh) 半导体器件和用于形成半导体器件的方法
US10186573B2 (en) Lateral power MOSFET with non-horizontal RESURF structure
US20220013625A1 (en) Vertical power semiconductor device and manufacturing method
CN216980575U (zh) 一种快速恢复二极管
JP4770729B2 (ja) 半導体装置
CN117253903A (zh) 半导体功率器件的终端保护结构及其制造方法
CN117423723A (zh) 可提升超结结构雪崩耐量的功率器件及制备方法
CN117153863A (zh) 半导体功率器件的终端保护结构的制造方法
CN114078963A (zh) 半导体装置及半导体装置的制造方法
JP2009152522A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200407