JP7259215B2 - 絶縁ゲート型半導体装置及び絶縁ゲート型半導体装置の製造方法 - Google Patents
絶縁ゲート型半導体装置及び絶縁ゲート型半導体装置の製造方法 Download PDFInfo
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- JP7259215B2 JP7259215B2 JP2018106459A JP2018106459A JP7259215B2 JP 7259215 B2 JP7259215 B2 JP 7259215B2 JP 2018106459 A JP2018106459 A JP 2018106459A JP 2018106459 A JP2018106459 A JP 2018106459A JP 7259215 B2 JP7259215 B2 JP 7259215B2
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Description
本発明の実施形態に係る絶縁ゲート型半導体装置はトレンチゲート型MISFETであり、図1に示すように、第1導電型(n-型)のドリフト層2、及び第2導電型(p型)のベース領域6a、6bを備える。ドリフト層2及びベース領域6a、6bは、以下に説明するソース領域8a等の他の半導体領域を含めて、六方晶系の半導体結晶を基礎とする。ベース領域6a、6bはドリフト層2に注入されるキャリアの注入を制御する領域である。ドリフト層2は、ベース領域6a、6bから注入されたキャリアがドリフト電界で走行する領域である。ドリフト層2とベース領域6a、6bとの間には、ドリフト層2よりも高不純物密度のn型の電流拡散層3が設けられる。電流拡散層3はドリフト層2に注入されるキャリアの広がり抵抗を低減させる機能を有する。なお、電流拡散層3が無く、電流拡散層3の上面の位置でドリフト層2の上面がベース領域6a,6bに接していてもよい。
Ph=2(Wa+a)
となる。JFET幅Waは、オン抵抗の増加を抑制するため一定以上確保する必要がある。例えば、第1比較例のJFET幅Waと実施形態のJFET幅Wjとが同程度とすれば、第1比較例のセルピッチPhは実施形態のセルピッチPの2倍程度と大きくなってしまう。
Ph=2(Ws+a)
となる。JFET幅Wsを、例えば、実施形態のJFET幅Wjと同程度とすれば、第2比較例のセルピッチPsは実施形態のセルピッチPの2倍程度と大きくなってしまう。
次に、図13~図20を用いて、実施形態に係る絶縁ゲート型半導体装置の製造方法を、トレンチゲート型MISFETの場合を一例に説明する。図14~図19の各図には、(a)レイアウト平面図、及び(b)レイアウト平面図に示した2点差線から垂直に切った断面図を示している。なお、以下に述べるトレンチゲート型MISFETの製造方法は一例であり、特許請求の範囲に記載した趣旨の範囲であれば、この変形例を含めて、これ以外の種々の製造方法により実現可能であることは勿論である。
実施形態の第1変形例に係る絶縁ゲート型半導体装置は、図25に示すように、ユニットセル22aに、互いに平行な一対の辺を<11-20>方向に長くした長方六角形を上面パターンとする六角柱状の活性セル柱20a及びコンタクトセル柱21aを有する点が実施形態と異なる。図25に上面の形状を示した扁平な六角柱状も六角錐台等の形状が示す傾斜したトレンチ側壁面を有した立体形状であってもよい。活性セル柱20a及びコンタクトセル柱21aは、トレンチ9aにより区画される。活性セル柱20aは、ソース領域8aを有する。他の構成は、実施形態に係る絶縁ゲート型半導体装置と同様であるので、重複した説明を省略する。
実施形態の第2変形例に係る絶縁ゲート型半導体装置は、図27に示すように、四角柱状の活性セル柱20r及び四角柱状のコンタクトセル柱21rが<11-20>方向に1列に設けられたユニットセル22rを有する点が実施形態と異なる。図27の上面が矩形をなす「四角柱状」も、四角錐台等の形状が示す傾斜したトレンチ側壁面を有した立体形状であってもよい。トレンチ9rの側壁面は、<11-20>方向に平行なm面と、<11-20>方向に直交するa面である。図11に示したように、<11-20>方向側の側壁面は移動度が小さい。したがって、第1コンタクト領域7aを<11-20>方向に向かう側に設けて、移動度の低いチャネルをつぶしている。他の構成は、実施形態及び第1変形例に係る絶縁ゲート型半導体装置と同様であるので、重複した説明を省略する。この時、第1コンタクト領域7aの幅は、セル柱の一辺の長さ(ソース領域8aの幅+第1コンタクト領域7aの幅)に対して20~40%程度が好ましい。
実施形態の第3変形例に係る絶縁ゲート型半導体装置は、図30に示すように、八角柱状の活性セル柱20v及び立方体状のコンタクトセル柱21vが設けられたユニットセル22vを有する点が実施形態と異なる。図30に示した上面が八角形をなす「八角柱状」も、八角錐台等の形状が示す傾斜したトレンチ側壁面を有した立体形状であってもよい。同様に、図30の上面が正方形をなす「立方体状」も、四角錐台等の形状が示す傾斜したトレンチ側壁面を有した立体形状であってもよい。正八角形の活性セル柱20vの互いに平行な辺が<11-20>方向に平行に配置される。トレンチ9vの側壁面は、図30において活性セル柱の下側の面を(1-100)面とすれば、図12に示したドレイン電流比と回転角度の関係を示す図12が適用できる。図12に示すように、回転角度が90°のとき、移動度が最も低くなる。したがって、第1コンタクト領域7aを<11-20>方向に向かう側の側壁面に設けて、移動度の低いチャネルをつぶしている。他の構成は、実施形態、並びに第1及び第2変形例に係る絶縁ゲート型半導体装置と同様であるので、重複した説明を省略する。
図32~図36に、実施形態、及び第1~第3変形例に係る絶縁ゲート型半導体装置と、従来構造の絶縁ゲート型半導体装置との特性の比較を行った結果を示す。なお、第1制御部コンタクト領域の面積減少によるボディダイオードの順方向電圧Vfの増加や、最小加工寸法については考慮していない。六角形の活性セルについて、実施形態に係る構造を「六角片側つぶし」、第1変形例に係る構造を「長方六角つぶし」、第2変形例に係る構造を「四角片側つぶし」、第3変形例に係る構造を「八角片側つぶし」と表記する。つぶしがない従来構造として、「六角チャネル」、「四角チャネル」、及び「ストライプ」と表記する。チャネル密度として、ユニットセル内の総チャネル幅をユニットセル面積で規格化している。つぶし幅については、六角形活性セルについては、図3に示したように、<11-20>方向の側の2つの頂点を結ぶ位置を100%とする。矩形(四角)活性セルでは、<11-20>方向側の辺から0.2μmの位置を100%とする。
上記のように、本発明は実施形態及び第1~第3変形例によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
2…ドリフト層
3…電流拡散層
4a…ゲート底保護領域
4b…第1埋込領域
4b,5…ベース底埋込領域
5…第2埋込領域
6a、6b…ベース領域
7a…第1コンタクト領域
7b…第2コンタクト領域
8a…ソース領域
9…トレンチ
10,11…絶縁ゲート型電極構造
10…ゲート絶縁膜
11…ゲート電極
12…層間絶縁膜
13…ソースコンタクト層
14…バリアメタル層
15…ソース電極
16…ドレイン電極
20…活性セル柱
21…コンタクトセル柱
22…ユニットセル
Claims (12)
- 第1導電型のドリフト層と、
前記ドリフト層の表面に配置された第2導電型のベース領域と、
前記ベース領域の表面に選択的に設けられた、前記ドリフト層よりも不純物密度の高い第1導電型のソース領域と、
前記ベース領域の表面に選択的に設けられた、前記ベース領域よりも不純物密度の高い第2導電型の第1コンタクト領域と、
前記ソース領域,前記第1コンタクト領域、および前記ベース領域を貫通するトレンチによって区画され、格子状に配列された複数のセル柱と、
前記トレンチの内側に設けられた絶縁ゲート型電極構造と、を備え、
前記セル柱は前記ソース領域,前記第1コンタクト領域、および前記ベース領域を備えており、
前記セル柱は、前記第1コンタクト領域と前記ソース領域とが、前記セル柱に1つずつ設けられた活性セル柱を有し、
前記セル柱の上部表面は、<0001>方向に対して<11-20>方向に2°以上、8°以下のオフ角を有し、
前記セル柱の高さ方向に垂直な断面は六角形であり、該六角形の互いに平行な1組の辺が<11-20>方向に延伸し、
前記活性セル柱における前記第1コンタクト領域と前記ソース領域との境界は、前記ベース領域の上部において、<1-100>方向に伸びることを特徴とする絶縁ゲート型半導体装置。 - 前記ドリフト層が、六方晶系半導体であることを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 前記セル柱が、前記セル柱の中心をつなぐ直線が規則性をもって交差するよう配列される請求項1又は2に記載の絶縁ゲート型半導体装置。
- 前記トレンチの底部に接して埋め込まれた、前記ベース領域よりも高不純物密度の第2導電型のゲート底保護領域を更に備えることを特徴とする請求項1~3のいずれか1項に記載の絶縁ゲート型半導体装置。
- 前記セル柱は、
前記セル柱の上部表面の外周に接するように前記ベース領域に設けられた、前記ベース領域よりも不純物密度の高い第2導電型の第2コンタクト領域と、
前記ベース領域と、
前記ベース領域の底部に設けられ、前記第2コンタクト領域と前記ゲート底保護領域を電気的に接続するベース底埋込領域と、
を備えたコンタクトセル柱をさらに有することを特徴とする請求項4に記載の絶縁ゲート型半導体装置。 - 前記第2コンタクト領域は、前記コンタクトセル柱の外周のすべてに接することを特徴とする請求項5に記載の絶縁ゲート型半導体装置。
- 第1導電型のドリフト層の表面に、第2導電型のベース領域を形成する工程と、
前記ベース領域の表面に、前記ドリフト層よりも高不純物密度の第1導電型のソース領域を形成する工程と、
前記ベース領域の表面に、前記ベース領域よりも高不純物密度の第2導電型の第1コンタクト領域を形成する工程と、
前記ソース領域,前記第1コンタクト領域、および前記ベース領域を貫通するトレンチを形成することにより、格子状に配列された複数のセル柱を区画する工程と、
前記トレンチの内側にゲート絶縁膜とゲート電極からなる絶縁ゲート型電極構造を形成する工程と、
を備え、
前記セル柱は前記ソース領域,前記第1コンタクト領域、および前記ベース領域を備えるように形成され、
前記セル柱は、前記第1コンタクト領域と前記ソース領域とが、前記セル柱に1つずつ設けられた活性セル柱を有するように形成され、
前記セル柱の上部表面は、<0001>方向に対して<11-20>方向に2°以上、8°以下のオフ角を有し、
前記セル柱の高さ方向に垂直な断面は六角形であり、該六角形の互いに平行な1組の辺が<11-20>方向に延伸し、
前記活性セル柱における前記第1コンタクト領域と前記ソース領域との境界は、前記ベース領域の上部において、<1-100>方向に伸びるように形成されることを特徴とする絶縁ゲート型半導体装置の製造方法。 - 前記ドリフト層が、六方晶系半導体であることを特徴とする請求項7に記載の絶縁ゲート型半導体装置の製造方法。
- 前記トレンチの底部に接して埋め込まれた、前記ベース領域よりも高不純物密度の第2導電型のゲート底保護領域を形成する工程を更に備えることを特徴とする請求項7又は8に記載の絶縁ゲート型半導体装置の製造方法。
- 前記セル柱の外周に接するように前記ベース領域の上部表面に設けられた、前記ベース領域よりも不純物密度の高い第2導電型の第2コンタクト領域を形成する工程と、
前記第2コンタクト領域の下部に、前記第2コンタクト領域と前記ゲート底保護領域を電気的に接続するベース底埋込領域を形成する工程と、をさらに備え、
前記セル柱は、前記第2コンタクト領域、前記ベース底埋込領域、および前記ベース領域を備えたコンタクトセル柱をさらに有するように形成されることを特徴とする請求項9に記載の絶縁ゲート型半導体装置の製造方法。 - 前記第2コンタクト領域は、前記コンタクトセル柱の外周のすべてに接するように形成されることを特徴とする請求項10に記載の絶縁ゲート型半導体装置の製造方法。
- 前記第1コンタクト領域を形成する工程において、前記第1コンタクト領域はストライプ状に形成されることを特徴とする請求項7又は8に記載の絶縁ゲート型半導体装置の製造方法。
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