CN108369933B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN108369933B CN108369933B CN201680071859.9A CN201680071859A CN108369933B CN 108369933 B CN108369933 B CN 108369933B CN 201680071859 A CN201680071859 A CN 201680071859A CN 108369933 B CN108369933 B CN 108369933B
- Authority
- CN
- China
- Prior art keywords
- electrode
- plate
- frame
- shaped
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 35
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 55
- 239000000919 ceramic Substances 0.000 description 29
- 230000000694 effects Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 15
- 239000010949 copper Substances 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 238000007789 sealing Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 238000000465 moulding Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000001721 transfer moulding Methods 0.000 description 5
- 239000004734 Polyphenylene sulfide Substances 0.000 description 4
- 229920000069 polyphenylene sulfide Polymers 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920002050 silicone resin Polymers 0.000 description 4
- 238000009736 wetting Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/2912—Antimony [Sb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/83424—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种半导体装置(100),具备板状电极(61)及半导体元件(21、22),并具有将半导体元件中的表面电极与板状电极利用接合材料(32)进行接合的接合部(32A),其中,板状电极在与半导体元件相对的相对面(614)上,具有将接合部包围且对上述接合材料具有耐热性的框状构件(52)。
Description
技术领域
本发明涉及半导体装置及其制造方法,尤其是涉及具备电力用半导体元件的作为电源模块的半导体装置及其制造方法。
背景技术
电力用半导体装置,即电源模块从产业用设备到家电及信息终端设备,不断向所有产品普及。尤其是对于搭载于家电的电源模块,要求小型轻量化以及能够对应多品种的高生产性及高可靠性。
另外,在动作温度高且转换效率优异这一点上,电源模块也要求能够应用于今后极有可能成为主流的SiC半导体的封装方式。
在先技术文献
专利文献
专利文献1:日本国特许4640345号
专利文献2:日本国特许4579314号
发明内容
发明的概要
发明要解决的课题
电源模块具有这样的特征,即,其是一种在高电压下处理大电流的半导体,为了形成大电流电路,通常,通过对电源半导体元件的表面电极配设多根达到的粗的铝等的线材来形成电路。相对于此,为了增大电流容量,将板状电极配置在电源半导体元件上并通过焊锡等直接接合于表面电极的方式不断普及。
在这样的直接接合方式中,向主要由铜等构成的板状电极与电源半导体元件的表面电极之间供给焊锡来形成接合部。作为该接合部的形成方法,可考虑将板状的焊锡预先夹设于两电极之间,或者使熔融的焊锡流入等方法。
然而,无论是哪种方法,如果焊锡仅在板状电极浸润扩展,则在与电源半导体元件的表面电极之间将无法形成接合部,导致断路故障。另外,相反地,在焊锡的量过剩的情况下,或者在板状电极与表面电极的间隔窄的情况下,剩余的焊锡会溢出,可能会引起绝缘不良。
针对这样的不良情况,需要充分地进行产品检查,有时会招致生产性的下降。另一方面,为了防止断路故障或绝缘不良,需要(i)使供给的焊锡的量恒定,(ii)使板状电极与电源半导体元件的间隔恒定,并且(iii)限制板状电极中的焊锡浸润区域。
本发明的目的在于提供一种能够减少上述那样的不良情况的发生并且相比以往能够提高生产性及品质的半导体装置及其制造方法。
用于解决课题的方案
为了实现上述目的,本发明如下构成。
即,本发明的一个形态的半导体装置具备板状电极及半导体元件,并具有将上述半导体元件中的表面电极与上述板状电极利用接合材料进行接合的接合部,其特征在于,上述板状电极在与上述半导体元件相对的相对面上,具备将上述接合部包围且对上述接合材料具有耐热性的框状构件。
发明的效果
根据本发明的一个形态的半导体装置,通过在板状电极设置框状构件,能够限制形成接合部的接合材料在板状电极处超过必要限度地扩展的情况。由此,能够可靠地形成接合部,能够防止断路故障的发生。而且,即使在接合材料的量过剩的情况下,也能够防止导致绝缘不良的情况。
附图说明
图1A是将实施方式1的电源模块按照其制造过程表示的概念图,是表示电源模块包含的陶瓷基板的构造的图。
图1B是将实施方式1的电源模块按照其制造过程表示的概念图,是表示在保持有板状电极的壳体上安装了陶瓷基板的状态的图。
图1C是表示将图1B所示的电源半导体元件的表面电极与板状电极进行了焊锡接合的状态的图,是图2A所示的A-A部的剖视图。
图1D是表示对图1C所示的电源模块进行了树脂密封的状态的图。
图1E是表示图1A至图1D所示的电源模块的变形例的概念图。
图1F是类似于图1C的图,是用于说明电源半导体元件的表面电极与框状构件未紧贴时的接合状态的剖视图。
图1G是表示图1A至图1D所示的电源模块的变形例的概念图。
图1H是表示将图1G所示的框状构件及辅助框状构件组合的状态的概念图。
图2A是表示图1C所示的电源模块中的板状电极的辅助框状构件的立体图。
图2B是表示图1B所示的电源模块中的板状电极的框状构件的立体图,是省略了电源半导体元件及陶瓷基板的图示的图。
图3A是将实施方式2的电源模块按照其制造过程表示的概念图,是表示在壳体上安装有陶瓷基板的状态的图。
图3B是表示在图3A所示的电源模块中安装陶瓷基板的方法的图。
图3C是表示在图3B所示的电源模块中将电源半导体元件的表面电极与板状电极进行了焊锡接合的状态的图。
图3D是表示在图3C所示的电源模块中进行了树脂密封的状态的图。
图4是实施方式3的电源模块的概念图。
具体实施方式
以下参照附图对作为实施方式的半导体装置及其制造方法进行说明。需要说明的是,在各图中,对于相同或同样的结构部分,标注相同的符号。而且,以下的说明为了避免不必要的冗长化并使本领域技术人员便于理解,有时省略已经周知的事项的详细说明以及对于实质上相同的结构的重复说明。而且,以下的说明及附图的内容不限定权利要求书所记载的主题。
另外,在以下的实施方式中,虽然作为半导体装置而采用电源模块即电力用半导体装置为例进行说明,但是本公开并不限定于电力用半导体装置。即,本公开能够适用于具有如下方式的半导体装置,即,与半导体元件的表面电极相对地配置板状电极并利用接合材料接合两电极之间的方式。
实施方式1.
图1A至图1H(有时总称记作图1)是表示实施方式1的电源模块100的概略结构的概念图。对电源模块100的概略结构进行说明,电源模块100具有板状电极61及相当于半导体元件的一例的电源半导体元件(下述的IGBT22等),并具有利用接合材料接合电源半导体元件中的表面电极与板状电极61而形成的接合部。此外,板状电极61具有框状构件52。以下对这样的电源模块100进行更详细的说明。
作为电源半导体元件,在本实施方式中,例示有作为一例的15mm×15mm×厚度0.25mm尺寸的IGBT(Insulated Gate Bipolar Transistor)22以及作为另一例的13mm×15mm×厚度0.25mm尺寸的二极管21。而且,IGBT22具有表面主电极221,二极管21具有表面主电极211。需要说明的是,表面主电极包含于表面电极,相当于表面电极之中的主要的电极。
安装有这些二极管21及IGBT22的、相当于绝缘基板的一例的陶瓷基板10,作为一例具有25mm×50mm的尺寸,通过在陶瓷基材11上层叠表面导体层13及背面导体层12而构成。在此,陶瓷基材11例如为氧化铝,作为一例具有25mm×50mm×厚度0.635mm的尺寸,表面导体层13及背面导体层12例如都为铜制,作为一例具有21mm×46mm×厚度0.4mm的尺寸。
如图1A所示,在这样的陶瓷基板10的表面导体层13上,使用相当于接合材料的一例的焊锡(熔点219℃)31,对二极管21及IGBT22中的各背面电极进行芯片焊接。作为焊锡31,使用例如Sn-Ag-Cu焊锡。
安装有二极管21及IGBT22的陶瓷基板10如图1B所示,使用粘结剂8(硅酮树脂制)将陶瓷基板10的周围固定在相当于该电源模块100的框体的壳体51上。
壳体51为PPS(Poly Phenylene Sulfide Resin)树脂制,在壳体51中嵌入模制形成并保持有以下详细说明的板状电极61及信号电极62等。
板状电极61及信号电极62都为铜制,板状电极61作为一例具有宽度12mm×厚度0.7mm的尺寸,信号电极62作为一例具有宽度2mm×厚度0.4mm的尺寸。而且,在板状电极61的一端形成有螺纹紧固端子611,该螺纹紧固端子611使用埋设于壳体51的侧壁中的螺母来紧固连结。
此外,板状电极61具有贯通该板状电极61的两个贯通部612。贯通部612是在接合IGBT22及二极管21的各表面主电极221、211与板状电极61时能够使本实施方式中的熔融的焊锡通过的孔,对应于IGBT22的表面主电极221(尺寸:12mm×12mm)及二极管21的表面主电极211(尺寸:12mm×12mm)各自的大致中心来设置。在本实施方式中,贯通部612作为一例具有直径2.5mm的尺寸。需要说明的是,贯通部612的尺寸可以根据IGBT22等电源半导体元件的表面主电极的尺寸来决定。
对应于这样的贯通部612,板状电极61在与IGBT22等电源半导体元件相对的相对面614上还具有框状构件52,在相对面614的相反侧的背面615具有辅助框状构件53。
如图2A及图2B(有时总称记作图2。)所示,框状构件52及辅助框状构件53具有将板状电极61从其厚度方向夹持并与壳体51连接的连接部530。由此,框状构件52及辅助框状构件53经由连接部530,通过与壳体51相同的材料,利用与成型壳体51并嵌入模制形成板状电极61的工序相同的工序,与壳体51一体形成。需要说明的是,对于框状构件52及辅助框状构件53的形状等,以下进行详细说明。
通过这样将框状构件52及辅助框状构件53与壳体51一起形成,能够抑制部件个数的增加,并能够将板状电极61更牢固地保持于壳体51,因此能够提高板状电极61的位置精度,能够抑制板状电极61与电源半导体元件的间隔的偏差。
对于这样在形成框状构件52及辅助框状构件53的同时嵌入模制有板状电极61的壳体51,将安装有二极管21及IGBT22的陶瓷基板10如上所述粘结于其上。
此外,如图1C所示,通过板状电极61的贯通部612,向板状电极61与IGBT22的表面主电极221以及与二极管21的表面主电极211之间分别注入熔融的焊锡32。该焊锡32例如为Sn-Ag-Cu,熔点为219℃。由此,板状电极61与IGBT22的表面主电极221及二极管21的表面主电极211通过焊锡32而接合。而且,使用例如直径为0.2mm的铝制线材4,将IGBT22的信号端子222与信号电极62之间进行引线接合连接。
并且,如图1D所示,将硅酮树脂制的封固用凝胶7注入壳体51内来进行绝缘封固。
如以上所述构成的电源模块100能够发挥以下说明的效果。
即,如图1B及图2B所示,板状电极61所具有的框状构件52具有:与IGBT22及二极管21的表面主电极221、211相接的面上的第一开口部521;与板状电极61相接的面上的第二开口部522。在此,第一开口部521及第二开口部522都是板状电极61的贯通部612位于各自的中央部分的开口部。
第一开口部521作为一例而具有11mm×11mm的尺寸,是具有例如半径3mm的圆弧形状的四个角的大致方形形状,第二开口部522作为一例而具有8mm×8mm的尺寸,是具有例如半径2mm的圆弧形状的四个角的大致方形形状。由此,框状构件52具有研钵形状部523。该研钵形状部523的深度作为一例而为0.5mm。向该研钵形状部523的内侧注入焊锡32,形成焊锡接合部32A(图1C至图1F)。这样,框状构件52是将由焊锡32形成的接合部32A包围的构件,而且,是对焊锡32具有耐热性的构件。
由于具有这样的框状构件52,通过了板状电极61的贯通部612的焊锡32向由框状构件52形成的研钵形状部523内注入,由研钵形状部523来限制移动。由此,在将IGBT22及二极管21的各表面主电极221、211与板状电极61接合时,能够防止熔融的焊锡仅向板状电极61浸润而发生断路故障的情况。而且,即使在例如焊锡32那样的接合材料的量过剩的情况下也能够防止绝缘不良的情况。其结果是,能够减少电源模块100的不良情况的产生,与以往相比能够实现电源模块的生产性及品质的提高。
另外,第一开口部521如上所述为在四个角具有圆弧形状的11mm×11mm的尺寸,IGBT22及二极管21中的表面主电极221、211的尺寸在本实施方式中如上所述都为12mm×12mm,因此与表面主电极相接的第一开口部521的尺寸小于表面主电极221、211的尺寸。
因此,在将IGBT22及二极管21的各表面主电极221、211与板状电极61进行接合时,在框状构件52紧贴于各表面主电极221、211的情况下,熔融的焊锡无法浸润扩展至表面主电极221、211的端部。
由此,能够防止集中于焊锡32的接合部32A的端部的接合应力在容易产生剥离的表面主电极221、211的端部重叠的情况,容易确保接合可靠性、甚至电源模块100的可靠性。此外,能够可靠地形成焊锡32的接合部32A,并能够防止断路故障的发生。其结果是,能够减少电源模块100中的不良情况的发生,与以往相比能够实现电源模块的生产性及品质的提高。
另外,在框状构件52与半导体元件的表面主电极、例如IGBT22及二极管21的各表面主电极221、211未完全紧贴的情况下,如图1F所示,薄的焊锡的层321存在于表面主电极的周围。该部分能够用作为对配置于半导体元件的表面的晶体管电路进行有效利用的电气路径,且由于其极薄,因此能够防止接合应力传播至表面主电极的端部的情况。
另外,在研钵形状部523的内侧形成的焊锡接合部32A处,也形成为下端扩展的圆角形状,因此能够使接合应力分散。由此与周围陡立的接合部相比,焊锡接合部32A能够得到高的接合可靠性。
另外,如上所述,由于研钵形状部523的四个角带有圆角,因此形成的焊锡接合部32A的四个角也带有圆角。由此,在焊锡接合部32A,能抑制接合应力的集中,能够延缓裂纹的产生。
此外,相对于半导体元件的表面主电极的尺寸的、框状构件52的第一开口部521的尺寸,考虑到制造时的部件的位置偏差或构件的尺寸公差,在其一条边处如果为表面主电极的长边的5%以上那么小,则可认为能够发挥上述的接合应力集中抑制效果。另一方面,如果第一开口部521的尺寸过小,则表面主电极的晶体管利用效率下降,因此优选为表面主电极的长边的至多40%以下。在此,上述晶体管利用效率是指形成于半导体元件表面的晶体管中的电流流动而被实际驱动的晶体管的比例。
另外,也能够发挥以下的效果。
即,如图1B及图2A所示,板状电极61的背面615所具备的辅助框状构件53具有与板状电极61相接的面上的第三开口部531和辅助框状构件53的表面上的第四开口部532。第三开口部531及第四开口部532都与板状电极61的贯通部612呈同心状地设置。
第三开口部531作为一例而具有直径2.2mm的尺寸,第四开口部532作为一例而具有直径5.0mm的尺寸,由此,辅助框状构件53具有圆锥台形状部533。该圆锥台形状部533的深度作为一例而为0.5mm。
另一方面,板状电极61的贯通部612如上所述具有直径2.5mm的尺寸。由此,第三开口部531的尺寸小于贯通部612的尺寸。通过使第三开口部531的尺寸比贯通部612小,能够抑制向框状构件52的上述研钵形状部523内注入的焊锡32进入板状电极61的背面615侧的情况,能够抑制焊锡32向背面615的浸润。由此,能够抑制焊锡32的供给时的溢出。
此外,辅助框状构件53中的具有第三开口部531及第四开口部532的部分如上所述为圆锥台形状部533。由此,例如,在以所需的长度将圆柱形状的“钎焊丝”从第四开口部532侧投入的情况下,圆锥台形状部533能够发挥钎焊丝的引导功能。
另外,在通过使熔融的焊锡流入来形成接合部32A的情况下,圆锥台形状部533也能够作为引导部发挥功能。
对于电源模块100中的上述结构,也可以采用以下的变形例。
关于陶瓷基板10,在本实施方式中使用了氧化铝陶瓷基板,但也可以是氮化铝或氮化硅等的陶瓷基板,也能够得到与上述同样的效果。而且,虽然使用铜作为表面导体层13及背面导体层12,,但也可以使用铝导体层,也能够得到与上述同样的效果。
另外,对于板状电极61及信号电极62,虽然在本实施方式中使用了铜制电极,但也可以使用铝制或者CIC(综合夹心板(copper invar copper))制电极,也能够得到与上述同样的效果。此外,虽然将板状电极61的一端作为外部电极而设为螺纹紧固端子611,但这是一例,也可以排除螺母而设为焊接端子,也能够得到与上述同样的效果。
另外,虽然在板状电极61上形成了孔作为贯通部612,但也可以形成狭缝,或者对于一个电源半导体元件形成多个贯通部,也能够得到与上述同样的效果。
另外,在本实施方式中,虽然IGBT22等电源半导体元件与陶瓷基板10的芯片焊接使用了Sn-Ag-Cu焊锡31,但也可以使用Sn-Cu类或Sn-Sb类等其他的焊锡材料。此外,也可以使用例如使Ag填料分散于环氧树脂的导电性粘结剂、或者使用了例如Ag纳米颗粒的低温烧制接合材料作为接合材料,也能够得到与上述同样的效果。
另外,在本实施方式中,虽然使用了PPS作为壳体51的材料,但也可以使用LCP(液晶聚合物:liquid-crystal polymer),也能够期待耐热性的进一步提高。
另外,在本实施方式中,虽然使用了硅酮树脂作为封固用凝胶7,但也可以使用环氧制直接灌封材料,也能够得到与上述同样的效果。
另外,如图1E所示,也可以取代基于铝制线材4的引线接合,利用使信号电极62延伸的导线621,对与IGBT22的信号端子222之间进行焊锡接合,也能够得到与上述同样的效果。
另外,在本实施方式中,对于框状构件52及辅助框状构件53,虽然使用与壳体51相同的PPS在嵌入模制形成时形成,但也可以通过3D打印机或者分配器涂布等,使用具有耐热性的其他的树脂来形成,能得到与上述同样的效果。
另外,在本实施方式中,如上所述,框状构件52及辅助框状构件53使用与壳体51相同的PPS在嵌入模制形成时与壳体51一体形成,但也可以如图1G所示,将框状构件52及辅助框状构件53作为分割成不同的部件的独立部件进行组装。即,另行分别制作形成框状构件52的多个部件52A以及形成辅助框状构件53的多个部件53A。然后,通过粘结、热压接或嵌合等方法将部件52A及部件53A的各独立部件固定于板状电极61或壳体51,如图1H所示,分别形成框状构件52及辅助框状构件53。
通过采用这样的手法,具有如下优点,即,即使在例如壳体的尺寸大型化而嵌入模制成型困难的情况下也能够分别形成框状构件52及辅助框状构件53。
当纵横尺寸比(相对于注入宽度的进深)增大时,在嵌入模制时容易产生填充不良,通常在纵横尺寸比超过20时,会对填充性产生影响。由此,连接部530相当于用于将框状构件52及辅助框状构件53与壳体51一起成型的部分,相对于连接部530(图2A、图2B)的沿箭头B的宽度尺寸,在壳体51的长边的长度超过了20倍的情况下,采用部件52A及部件53A的手法具有生产性良好的优点。
实施方式2.
参照图3A至图3D(有时总称记作图3。)说明实施方式2的电源模块102。
本实施方式2的电源模块102具有与上述实施方式1的电源模块100基本上同样的结构。电源模块102与电源模块100的主要不同点在于板状电极61还具有间隔件54这一点、焊锡接合使用回流焊炉进行这一点等。
因此,以下主要对两者不同的结构部分进行说明,对于共同的结构部分则省略其说明。需要说明的是,在图3A至图3C中,使图1B及图1C中的图示上下颠倒而进行显示。
图3A图示出将保持有板状电极61等的壳体51翻过来后的状态。在本实施方式2中,如图3A所示,板状电极61具有间隔件54。间隔件54配置在板状电极61与陶瓷基板10之间,用于限定板状电极61与陶瓷基板10的间隔。在本实施方式中,实施方式1中说明的框状构件52具有间隔件54,间隔件54与框状构件52利用同一工序形成。间隔件54形成在间隔件54的主体部分不与IGBT22及二极管21接触,且间隔件54的前端与陶瓷基板10抵接那样的框状构件52的部位。
另外,在实施方式2的电源模块102中,如图3A所示,在框状构件52的研钵形状部523载置有板状焊锡320。板状焊锡320例如为直径8mm、厚度0.5mm。
此外,如图3B所示,在2个间隔件54之间能够收容IGBT22或二极管21,以使表面主电极221、211面对框状构件52的研钵形状部523的状态将IGBT22及二极管21配置于各框状构件52。此外,在IGBT22及二极管21的各背面电极处,以与各电源半导体元件例如相同的尺寸载置厚度0.1mm的板状焊锡310。
此外,以面对板状焊锡310的方式配置陶瓷基板10的表面导体层13,陶瓷基板10载置于在壳体51上形成的突起511。此时,对于板状电极61的间隔件54,在本实施方式中与框状构件52一起形成的间隔件54的前端与陶瓷基板10抵接。而且,陶瓷基板10的周围利用粘结剂8而固定于壳体51。
在如以上那样构成的状态下利用回流焊炉进行加热,由此如图3C所示,陶瓷基板10的表面导体层13与IGBT22及二极管21通过基于板状焊锡310的焊锡接合部而接合,IGBT22及二极管21的表面主电极221、211与板状电极61之间通过基于板状焊锡320的接合部32A而接合。
并且,如图3D所示,将整体翻转,使用例如直径0.2mm的铝制线材4,对IGBT22的信号端子222与信号电极62之间进行引线接合。进而,将例如硅酮树脂制的封固用凝胶7注入壳体51来进行绝缘封固。
在以上说明的本实施方式2的电源模块102中,由于具有框状构件52及辅助框状构件53,因此也能够得到与实施方式1中的电源模块100发挥的效果同样的效果。
此外,在本实施方式2的电源模块102中,由于板状电极61具有间隔件54,因此能够限定陶瓷基板10与IGBT22等电源半导体元件之间的焊锡31的接合部、以及IGBT22等电源半导体元件与板状电极61之间的焊锡的接合部32A的高度。因此,本实施方式2的电源模块102能够发挥如下的效果,即,通过间隔件54能够进一步抑制因作为接合材料的例如焊锡的溢出而引起的绝缘不良。
另外,在实施方式1中说明的变形例也能够适用于本实施方式2的电源模块102。在此,对于电源模块102中的间隔件54,即使通过3D打印机或者分配器涂布等、使用具有耐热性的其他的树脂形成,也能够得到同样的效果。
另外,在本实施方式中,在将电源模块102投入回流焊炉之后使其整体翻转而进行引线接合等,但是也可以通过对位置偏移采取措施而在投入回流焊炉之前使电源模块102翻转。
实施方式3.
参照图4对实施方式3的电源模块103进行说明。
本实施方式3的电源模块103具有与上述实施方式1、2的电源模块100、102基本上同样的结构。电源模块103与电源模块102的主要不同点在于不是基于回流焊炉来进行焊锡接合而是基于熔融的焊锡的注入这一点、以及不使用壳体51而利用传递模塑来成型这一点等。因此,使用具有与板状电极61不同形状的板状电极66。
因此,以下主要说明不同的结构部分,对于共同的结构部分省略其说明。
板状电极66相当于在实施方式2中说明的具有间隔件54的板状电极61,但是如上所述其用于不使用壳体51而进行传递模塑成型。由此,板状电极66在本实施方式中为直线状的形态,而且,框状构件52及辅助框状构件53以夹持板状电极66的方式成型。这样的板状电极66作为一例而为铜制,为宽度12mm×厚度0.7mm的尺寸。
板状电极66搭载在陶瓷基板10上方,使用传递模塑成型用的模具来固定。在此,在陶瓷基板10中,如在实施方式1中参照图1A说明的那样,作为电源半导体元件的IGBT22及二极管21通过焊锡31进行芯片焊接。而且,在将板状电极66搭载到陶瓷基板10上方时,与实施方式1、2的情况同样,板状电极66的各个贯通部612位于IGBT22的表面主电极221及二极管21的表面主电极211的大致中心。
在这样的状态下,通过板状电极66的各个贯通部612,将熔融的焊锡32注入框状构件52中的研钵形状部523。此时,如在实施方式2中说明的那样,板状电极66中的间隔件54的前端与陶瓷基板10抵接,因此能够限定IGBT22等电源半导体元件与板状电极66之间的焊锡32的接合部32A的高度。
此外,在使用铝制线材4将IGBT22的信号端子222与信号电极62之间进行引线接合之后,将例如环氧树脂制的封固用传递模塑树脂74向传递模塑成型用的模具内注入来进行绝缘封固。
在以上说明的本实施方式3的电源模块103中,由于具有框状构件52及辅助框状构件53,因此能够得到与实施方式1中的电源模块100发挥的效果相同的效果。
另外,板状电极66具有间隔件54,因此能够得到与实施方式2中的电源模块102发挥的效果相同的效果。
另外,在实施方式1、2中所说明的变形例对于本实施方式3的电源模块103也能够适用。
也可以采用将上述各实施方式组合的结构,而且,也可以将不同的实施方式所示的结构部分彼此组合。
虽然参照附图并与优选的实施方式相结合而对本发明充分地进行了记载,但是对于熟知该技术的人员而言可想到各种变形或修正。这样的变形或修正只要不脱离添附的权利要求书所限定的本发明的范围,就应理解为包含于其中。
而且,将2015年12月16日提出申请的日本国特许申请No.特愿2015-245191号的说明书、附图、权利要求书及说明书摘要的全部公开内容作为参考而编入本说明书中。
符号说明
7 封固用凝胶,10陶瓷基板,21二极管,22IGBT,
32 焊锡,32A接合部,51壳体,52框状构件,
53 辅助框状构件,54间隔件,61、66板状电极,
100、102、103 电源模块,
211、221 表面主电极,
521 第一开口部,531第三开口部,
612 贯通部。
Claims (8)
1.一种半导体装置,具备板状电极及半导体元件,并具有将所述半导体元件中的表面电极与所述板状电极利用接合材料进行接合的接合部,其特征在于,
所述板状电极在与所述半导体元件相对的相对面上,具备将所述接合部包围且对所述接合材料具有耐热性的框状构件,
所述框状构件具有面对所述半导体元件且尺寸比所述表面电极小的开口部,且具有包含所述开口部的研钵状形状部,
所述板状电极还具有:使由所述框状构件包围的所述接合材料通过的、贯通了该板状电极的贯通部;设置在所述相对面的相反侧的背面且具有比所述贯通部小的开口部的辅助框状构件。
2.根据权利要求1所述的半导体装置,其中,
所述开口部为大致方形形状。
3.根据权利要求1或2所述的半导体装置,其中,
所述开口部具有圆弧形状的四个角。
4.根据权利要求1或2所述的半导体装置,其中,
所述半导体装置还具有保持所述板状电极的壳体,
所述框状构件为了与所述壳体一体形成而具有与壳体连接的连接部。
5.根据权利要求1或2所述的半导体装置,其中,
所述半导体装置还具有安装了所述半导体元件的基板,
所述板状电极具有与所述基板抵接的间隔件。
6.一种半导体装置的制造方法,其是权利要求1~5中任一项所述的半导体装置的制造方法,其中,
板状电极所具备的框状构件具有尺寸比半导体元件中的表面电极小的开口部,以在所述开口部载置接合材料的方式对所述板状电极进行定向,
使表面电极与所述框状构件中的所述接合材料相对地将半导体元件载置于所述框状构件,
在所述半导体元件与绝缘基板中的导体层之间配置接合材料而将所述绝缘基板保持于壳体,
使所述接合材料熔融,将所述板状电极、所述半导体元件及所述绝缘基板接合。
7.根据权利要求6所述的半导体装置的制造方法,其中,
所述框状构件在成型所述壳体时与壳体一起形成于所述板状电极。
8.根据权利要求6所述的半导体装置的制造方法,其中,
所述框状构件是另行制作的独立部件,通过向所述壳体的固定而形成于所述板状电极。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015245191 | 2015-12-16 | ||
JP2015-245191 | 2015-12-16 | ||
PCT/JP2016/086340 WO2017104500A1 (ja) | 2015-12-16 | 2016-12-07 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108369933A CN108369933A (zh) | 2018-08-03 |
CN108369933B true CN108369933B (zh) | 2021-06-29 |
Family
ID=59056443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201680071859.9A Active CN108369933B (zh) | 2015-12-16 | 2016-12-07 | 半导体装置及其制造方法 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6444537B2 (zh) |
CN (1) | CN108369933B (zh) |
DE (1) | DE112016005807B4 (zh) |
WO (1) | WO2017104500A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017104500A1 (ja) | 2015-12-16 | 2017-06-22 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP6858657B2 (ja) * | 2017-06-27 | 2021-04-14 | 三菱電機株式会社 | 電力用半導体装置 |
CN111788676A (zh) * | 2018-03-07 | 2020-10-16 | 三菱电机株式会社 | 半导体装置以及电力变换装置 |
WO2019194272A1 (ja) * | 2018-04-06 | 2019-10-10 | 三菱電機株式会社 | 半導体装置および電力変換装置ならびに半導体装置の製造方法 |
EP3627544A1 (de) * | 2018-09-20 | 2020-03-25 | Heraeus Deutschland GmbH & Co. KG | Substratanordnung zum verbinden mit zumindest einem elektronikbauteil und verfahren zum herstellen einer substratanordnung |
JP7287164B2 (ja) * | 2019-07-23 | 2023-06-06 | 三菱電機株式会社 | 電力用半導体装置及び電力変換装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003100957A (ja) * | 2001-09-26 | 2003-04-04 | Nec Corp | 半導体パッケージ |
CN101176199A (zh) * | 2005-05-17 | 2008-05-07 | 松下电器产业株式会社 | 倒装片安装体及倒装片安装方法 |
JP2009170596A (ja) * | 2008-01-15 | 2009-07-30 | Nissan Motor Co Ltd | 電力変換装置およびその製造方法 |
JP2010251527A (ja) * | 2009-04-16 | 2010-11-04 | Panasonic Corp | 電子部品および電子部品の製造方法 |
CN102593091A (zh) * | 2011-01-14 | 2012-07-18 | 丰田自动车株式会社 | 半导体模块 |
CN104465591A (zh) * | 2013-09-18 | 2015-03-25 | 精工电子有限公司 | 半导体装置 |
WO2015107871A1 (ja) * | 2014-01-15 | 2015-07-23 | パナソニックIpマネジメント株式会社 | 半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4085639B2 (ja) * | 2002-01-28 | 2008-05-14 | 富士電機デバイステクノロジー株式会社 | 半導体装置およびその製造方法 |
JP4085768B2 (ja) * | 2002-10-08 | 2008-05-14 | トヨタ自動車株式会社 | 上部電極、パワーモジュール、および上部電極のはんだ付け方法 |
JP4281050B2 (ja) * | 2003-03-31 | 2009-06-17 | 株式会社デンソー | 半導体装置 |
JP4640345B2 (ja) | 2007-01-25 | 2011-03-02 | 三菱電機株式会社 | 電力用半導体装置 |
JP4579314B2 (ja) | 2008-06-02 | 2010-11-10 | 本田技研工業株式会社 | 半導体モジュール |
JP5732880B2 (ja) * | 2011-02-08 | 2015-06-10 | 株式会社デンソー | 半導体装置及びその製造方法 |
JP2013211497A (ja) * | 2012-03-30 | 2013-10-10 | Keihin Corp | 部品接合構造 |
DE112014000862T8 (de) * | 2013-07-31 | 2016-01-07 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
JP6000227B2 (ja) * | 2013-11-21 | 2016-09-28 | 三菱電機株式会社 | 半導体装置の製造方法 |
KR102004785B1 (ko) * | 2014-03-18 | 2019-07-29 | 삼성전기주식회사 | 반도체모듈 패키지 및 그 제조 방법 |
JP6293030B2 (ja) * | 2014-10-09 | 2018-03-14 | 三菱電機株式会社 | 電力用半導体装置 |
JP6406975B2 (ja) * | 2014-10-24 | 2018-10-17 | 三菱電機株式会社 | 半導体素子および半導体装置 |
WO2017104500A1 (ja) | 2015-12-16 | 2017-06-22 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
-
2016
- 2016-12-07 WO PCT/JP2016/086340 patent/WO2017104500A1/ja active Application Filing
- 2016-12-07 JP JP2017555999A patent/JP6444537B2/ja active Active
- 2016-12-07 DE DE112016005807.1T patent/DE112016005807B4/de active Active
- 2016-12-07 CN CN201680071859.9A patent/CN108369933B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003100957A (ja) * | 2001-09-26 | 2003-04-04 | Nec Corp | 半導体パッケージ |
CN101176199A (zh) * | 2005-05-17 | 2008-05-07 | 松下电器产业株式会社 | 倒装片安装体及倒装片安装方法 |
JP2009170596A (ja) * | 2008-01-15 | 2009-07-30 | Nissan Motor Co Ltd | 電力変換装置およびその製造方法 |
JP2010251527A (ja) * | 2009-04-16 | 2010-11-04 | Panasonic Corp | 電子部品および電子部品の製造方法 |
CN102593091A (zh) * | 2011-01-14 | 2012-07-18 | 丰田自动车株式会社 | 半导体模块 |
CN104465591A (zh) * | 2013-09-18 | 2015-03-25 | 精工电子有限公司 | 半导体装置 |
WO2015107871A1 (ja) * | 2014-01-15 | 2015-07-23 | パナソニックIpマネジメント株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN108369933A (zh) | 2018-08-03 |
DE112016005807B4 (de) | 2024-05-08 |
DE112016005807T5 (de) | 2018-09-27 |
JP6444537B2 (ja) | 2018-12-26 |
JPWO2017104500A1 (ja) | 2018-05-24 |
WO2017104500A1 (ja) | 2017-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108369933B (zh) | 半导体装置及其制造方法 | |
US9899345B2 (en) | Electrode terminal, semiconductor device for electrical power, and method for manufacturing semiconductor device for electrical power | |
US9673118B2 (en) | Power module and method of manufacturing power module | |
CN106449613B (zh) | 半导体装置 | |
WO2018021322A1 (ja) | 半導体装置 | |
JP6439389B2 (ja) | 半導体装置 | |
US11088042B2 (en) | Semiconductor device and production method therefor | |
US9059153B2 (en) | Semiconductor device | |
WO2022080055A1 (ja) | 半導体モジュール | |
WO2022080063A1 (ja) | 半導体モジュール | |
JP2016134540A (ja) | 電力用半導体装置 | |
JP2013171870A (ja) | 半導体モジュールとその製造方法 | |
WO2022080122A1 (ja) | 半導体モジュール | |
JP5218009B2 (ja) | 半導体装置 | |
US10566308B2 (en) | Semiconductor device manufacturing method and soldering support jig | |
JP2010287726A (ja) | 半導体装置 | |
CN108292642B (zh) | 电力用半导体装置 | |
EP3584834A1 (en) | Semiconductor device | |
US20220301966A1 (en) | Semiconductor device | |
WO2022080072A1 (ja) | 半導体モジュール | |
CN111354709B (zh) | 半导体装置及其制造方法 | |
US20210217721A1 (en) | Semiconductor device | |
US20210351092A1 (en) | Semiconductor apparatus | |
JP7183722B2 (ja) | 板はんだおよび半導体装置の製造方法 | |
JP7172325B2 (ja) | 配線基板、半導体装置、配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |